JPH0574965B2 - - Google Patents

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention provides a clock-synchronized R
-Relating to S flip-flops.

[Background technology and its problems]

For example, as shown in US Pat. No. 3,259,761, a logic circuit is known that has a basic configuration of a differential amplifier in which the emitters of transistors are connected in common. This logic circuit is an ECL (Emitter Coupled
Logic).

The NOR gate of this ECL is shown in Figure 7,
When two NOR gates are used, a set input S is supplied to one input terminal of one NOR gate, a reset input R is supplied to one input terminal of the other NOR gate, and the output of each NOR gate is connected to the other NOR gate. By supplying it to the other input terminal, an R-S flip-flop can be constructed.

FIG. 8 shows such an R-S flip-flop. Reference numerals 61, 62, and 63 indicate transistors whose emitters are commonly connected and connected to a resistor 64 as a constant current source. transistor 61
A reference voltage Vr is supplied to the base of the transistor 62, and a set input S is supplied to the base of the transistor 62.

The collectors of the transistors 62 and 63 are connected to each other, connected to a power supply terminal 67 via a resistor 65, and used as an output terminal via an emitter follower type transistor 66. transistor 6
The emitter of transistor 6 is connected to ground terminal 68 via resistor 69 and to the base of transistor 73 .

Reference numerals 71, 72, and 73 indicate transistors whose emitters are commonly connected and connected to a resistor 74 as a constant current source. A reference voltage Vr is supplied to the base of transistor 71, and a reset input R is supplied to the base of transistor 72.

The collectors of the transistors 72 and 73 are connected to each other, and are connected to a power supply terminal 67 via a resistor 75, and are used as an output terminal via an emitter follower type transistor 76. transistor 7
The emitter of transistor 6 is connected to ground terminal 68 via resistor 79 and to the base of transistor 63 .

As shown in FIG. 9, the reference voltage Vr is at the center of the logic amplitude between the set input S and reset input R low level (denoted as L in the following explanation) and high level (denoted as H in the following explanation). The relationship is said to match the level. For example, in the reset state, when the set input S rises to H when the output Q is L and the output Q is H, the transistor 62 is turned on and the transistor 7 is turned on.
The level supplied to the base of 3 is L. Therefore, transistor 71 is turned on and transistors 72 and 73 are turned off. Therefore, even if the output Q rises to H and the set input S subsequently becomes L,
The set state is maintained.

The R-S flip-flop using ECL described above can operate at high speed because the transistors do not operate in saturation. However, conventional ECL logic circuits compare the reference voltage and input signal, so
Requires a reference voltage generation circuit. In a high-speed logic circuit, since a large current is passed through each logic circuit, a number of reference voltage generation circuits corresponding to the circuit scale are required to absorb the transient current during switching. Of course, as is clear from FIG. 8, the need for a reference voltage means that the number of transistors constituting the differential amplifier is three in order to realize a two-input NOR gate.

Therefore, conventional logic circuits have the disadvantage of having a large number of elements. In addition, a wiring pattern is required to supply a reference voltage to each logic circuit, which increases the proportion of the wiring pattern on the board, resulting in a large chip size.

Furthermore, as shown in FIG. 10, the present invention enables a set input and a reset input to be supplied to a NOR gate, and these inputs to be inhibited by a set input control signal A and a reset input control signal B. It is. Such flip-flops are capable of operating in synchronization with a clock.

When two NOR gates are constructed using conventional ECL, the connection shown in FIG. 11 is obtained. The emitters of transistors 81, 82, and 83 are commonly connected to the ground terminal 8 through a constant current source resistor 84.
8, the collector connection point of transistors 82 and 83 is connected to a power supply terminal 87 via a resistor 85, and the base of a transistor 86 is connected, and the emitter of the transistor 86 is connected to a ground terminal 88 via a resistor 89. It is connected and led out as an output terminal 90. This output terminal 90 is R
- Connected to the set input terminal of the S flip-flop.

Similarly, the emitters of transistors 91, 92, and 93 are commonly connected and connected to a ground terminal 88 via a constant current source resistor 94.
2 and 93 are connected to a power supply terminal 87 via a resistor 95, and a transistor 9
The emitter of the transistor 96 is connected to the ground terminal 88 via a resistor 99 and is led out as an output terminal 97 . This output terminal 97 is connected to the reset input terminal of the R-S flip-flop.

The clock-synchronized flip-flop shown in FIG. 10 is realized by connecting the circuits shown in FIGS. 8 and 11, and therefore has the problem of requiring an extremely large number of elements. However, since each NOR gate requires a reference voltage, problems similar to those described above arise.

[Purpose of the invention]

Therefore, it is an object of the present invention to configure an R-S flip-flop using a logic circuit that does not require a reference voltage, to significantly reduce the number of elements such as transistors and resistors, and to reduce power consumption and delay time. Clock synchronized R-S that can shorten the
The purpose is to provide flip-flops.

According to this invention, when achieving an operating speed comparable to that of an R-S flip-flop using a conventional ECL logic circuit, the value of the constant current source of the differential amplifier can be reduced, so the number of elements can be reduced and As a result, power consumption can be extremely reduced.

Further, in the present invention, since there is no need to supply a reference voltage to each gate circuit, a wiring pattern for supplying the reference voltage is not required, and the chip size of the IC circuit can be reduced.

[Summary of the invention]

In the present invention, the emitters of the first transistor, the second transistor, and the third transistor are connected to a constant current source, and the collectors of the first transistor and the second transistor are commonly connected. The emitters of the differential amplifier, the fourth transistor, the fifth transistor, and the sixth transistor were connected to a constant current source, and the collectors of the fourth transistor and the fifth transistor were commonly connected. a second differential amplifier; a first level shift circuit that receives the collector output of the third transistor; extracts a signal level-shifted by a predetermined voltage; and supplies the signal to the base of the sixth transistor; a second level shift circuit into which the collector output of the sixth transistor is input, extracts a signal level-shifted by a predetermined voltage, and supplies it to the base of the third transistor; and an output of the first level shift circuit. a first output terminal for taking out an output signal from the output of the second level shift circuit; and a second output terminal for taking out the output signal from the output of the second level shift circuit, the base of the first transistor and the second transistor. a set input signal and a set input control signal to the base of the transistor, a reset input signal and a reset input control signal to the base of the fourth transistor and the base of the fifth transistor; The input control signal and the reset input control signal are binary signals having the same level relationship, and the binary signal is the first
This flip-flop is characterized in that the output signals taken out from the output terminal and the second output terminal are shifted by a predetermined voltage level and have substantially equal logic amplitudes.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows the configuration of an embodiment of the present invention.

In this invention, two logic circuits each consisting of a differential amplifier are used. One logic circuit is composed of transistors 1, 2, 3, 7, 10, and the other logic circuit is composed of transistors 21, 22, 23, 27,
Consists of 30. Transistor 1, 2, 3, 7
The emitters of the two are commonly connected and connected to a ground terminal 12 via a resistor 8 serving as a constant current source. A set input S- is supplied to a terminal 4 connected to the base of the transistor 1, and a set input control signal A- is supplied to a terminal 5 connected to the base of the transistor 2 and a terminal 6 connected to the base of the transistor 3, respectively.
and B are supplied.

The collectors of transistors 1, 2, and 3 are commonly connected, and this connection point is connected to a power supply terminal 11.
The collector of the transistor 7 is connected to a power supply terminal 11 via a resistor 9, and is also connected to the base of an emitter follower type transistor 10. The emitter of the transistor 10 is connected to a ground terminal 12 via a resistor 13, and is led out as an output terminal 14. transistor 10
The emitter of transistor 2 of the other differential amplifier
Connected to the base of 7.

The emitters of the transistors 21, 22, 23, and 27 are commonly connected and connected to the ground terminal 12 via a resistor 28 as a constant current source. A reset input R- is supplied to a terminal 24 connected to the base of the transistor 21, and reset input control signals C- and C- are supplied to a terminal 25 connected to the base of the transistor 22 and a terminal 26 connected to the base of the transistor 23, respectively. D- is supplied.

The collectors of the transistors 21, 22, and 23 are commonly connected, and this connection point is connected to the power supply terminal 11. The collector of the transistor 27 is connected to the power supply terminal 11 via a resistor 29, and is also connected to the base of an emitter follower type transistor 30. The emitter of transistor 30 is resistor 33
It is connected to the ground terminal 12 via the ground terminal 12 and is led out as the output terminal 34 of the output Q. The emitter of transistor 30 is connected to the base of transistor 7 of one differential amplifier.

The embodiment of the invention described above is equivalent to the configuration shown in FIG. In other words, one NOR gate has a set input S- and a set input control signal A.
-, B-, and reset input R- and reset input control signals C-, D- to the other NOR gate.
It is configured to supply

The set input S- can pass through the NOR gate only when the set input control signals A- and B- are at L-. Similarly, reset input R- can pass through the NOR gate only when reset input control signals C- and D- are low. By providing the inhibit gate in this way, a clock synchronous type R-S flip-flop can be realized.

FIG. 3 shows the relationship between the input level and the output level in one embodiment of the present invention. The outputs Q and have a high level H and a low level L, and have a logic amplitude VL. Set input S-, reset input R-, set input control signals A-, B-, reset input control signals C-, D are marked with a -.
- have logic amplitudes of VL equal to each other, and a level of 1/2 VL with respect to the output Q and a level of H- and L- shifted lower. Regarding the analog level, if Vcc is the power supply voltage and the voltage drop between the base and emitter of the transistor is VBE, then H=Vcc-VBE L=Vcc-VBE-VL H-=Vcc-VBE-1/2VL L-=Vcc −VBE−VL−1/2VL is selected. Assuming that the constant current source of the differential amplifier defined by the resistors 8 and 28 is R, and the values of the resistors 9 and 29 are R, (IR=VL).

FIG. 4 is a time chart showing the setting operation of the above-mentioned R-S flip-flop. When the flip-flop is in the reset state (Q=L,=H),
And set input control signals A- and B- are both L-.
When the set input S- supplied to the base of transistor 1 falls from H-level to L-level at
Since - is low, transistors 1, 2 and 3 are turned off and transistor 7 is turned on. Therefore, the output Q falls from H to L, transistor 27 of the differential amplifier turns off, transistors 21, 22, and 23 turn on, and the output Q changes from L to H.
stand up. This set state is set by the set input S
- or set input control signals A-, B- are held high.

In addition, in the set state and when the reset input control signals C- and D- are both L-, the reset input R- supplied to the base of the transistor 21 becomes H.
When the voltage falls from the − level to the L− level, the transistors 21, 22, and 23 turn off because L− is lower than the base potential L of the transistor 27.
Transistor 27 turns on. Therefore, the output Q falls from H to L, transistor 7 of the differential amplifier turns off, transistors 1, 2, and 3 turn on, and the output rises from L to H. This reset state is maintained even if the reset input R- or the reset input control signals C- and D- go high.

To generate a 1/2VL level shift in a binary signal with H and L levels, use the method shown in Figure 5 or 6.
The configuration shown in the figure may be used.

In FIG. 5, the emitters of transistors indicated by 41 and 42 are connected to a ground terminal 50 via a resistor 43 for a constant current source, and input terminals 44 and 45 are derived from the base of the transistor 41 and the base of the transistor 42, respectively. has been done. The collector of the transistor 41 is connected to one end of a resistor 48 via a resistor 46, the collector of the transistor 42 is connected to one end of a resistor 48 via a resistor 47, and the other end of this resistor 48 is connected to a power supply terminal 49. There is.

The collector of the transistor 42 is connected to the base of an emitter follower type transistor 51, and the emitter of the transistor 51 is grounded via a resistor 52 and led out as an output terminal 53. Assuming that the values of resistors 46 and 47 are equal to R,
The value of the resistor 48 is set to 1/2R. Therefore, the H and L binary signals supplied to the input terminals 44 and 45 are converted into binary signals having H- and L- levels, and are taken out to the output terminal 53.

FIG. 6 shows another example of a circuit configuration for performing level conversion similar to that described above. Transistors 41 and 42
A differential amplifier is configured, and transistor 4
The collector output of 2 is supplied to the base of an emitter follower type transistor 51. Resistors 52 and 5 are connected between the emitter of this transistor 51 and ground.
4 are inserted in series, and an output terminal 53 is led out from the connection point of the resistors 52 and 54. resistance 54
is for a constant current source, and if the values of resistors 46, 47, and 52 are made equal, the constant current caused by this resistor 54 is set to 1/2 of the constant current of the differential amplifier,
Can perform level conversion.

In the above description, a resistor is used as the constant current source, but it goes without saying that a constant current source configured to apply a predetermined DC voltage between the base and emitter of the transistor may be used. Furthermore, it is sufficient that there is at least one input of the set input control signal and the reset input control signal.

〔Effect of the invention〕

According to this invention, an R-S flip-flop is configured by a logic circuit that does not require a reference voltage,
The number of elements such as transistors and resistors can be significantly reduced, and a clock-synchronized R-S flip-flop with reduced power consumption and shortened delay time can be constructed.

According to this invention, when achieving an operating speed comparable to that of an R-S flip-flop using a conventional ECL logic circuit, the value of the constant current source of the differential amplifier can be reduced, so the number of elements can be reduced and As a result, power consumption can be extremely reduced.

Further, in the present invention, since there is no need to supply a reference voltage to each gate circuit, a wiring pattern for supplying the reference voltage is not required, and the chip size of the IC circuit can be reduced.

[Brief explanation of the drawing]

Fig. 1 is a connection diagram of an embodiment of this invention, Fig. 2 is a circuit diagram showing functions of an embodiment of this invention, and Fig. 3 is a circuit diagram showing functions of an embodiment of this invention.
The figure is a schematic diagram used to explain the level relationship of signals in an embodiment of this invention, FIG. 4 is a waveform diagram used to explain the operation of an embodiment of this invention, and FIGS. 5 and 6 are Connection diagram showing one example of a circuit configuration for an applicable level shift and other examples, No. 7
The figure shows a circuit diagram of an R-S flip-flop constructed from a conventional logic circuit, FIG. 8 is a connection diagram of an R-S flip-flop constructed from a conventional logic circuit, and FIG. 9 shows signal levels of a conventional logic circuit. A schematic diagram used for explanation; FIG. 10 is a circuit diagram of a conventional clock-synchronized R-S flip-flop; and FIG. 11 is a NOR gate required to construct a conventional clock-synchronized R-S flip-flop. It is a connection diagram. 1, 2, 3... One transistor of the differential amplifier, 21, 22, 23... The other transistor of the differential amplifier, 4, 5, 6, 24, 25, 26...
Input terminal, 14, 34... Output terminal, 8, 28...
...Resistor for constant current source, 11...Power terminal, 12...
...Ground terminal.

Claims (1)

[Claims] 1. The emitters of the first transistor, the second transistor, and the third transistor are connected to a constant current source, and the collectors of the first transistor and the second transistor are common. The emitters of the connected first differential amplifier, the fourth transistor, the fifth transistor, and the sixth transistor are connected to a constant current source, and the emitters of the fourth transistor and the fifth transistor are connected to a constant current source.
A second differential amplifier in which the collectors of the transistors of the transistors are connected in common, and a collector output of the third transistor are inputted, and a signal level-shifted by a predetermined voltage is taken out and the base of the sixth transistor is connected to the base of the sixth transistor. a first level shifter for supplying a signal to the base of the third transistor; a first output terminal for taking out an output signal from the output of the first level shifting means; and a second output terminal for taking out the output signal from the output of the second level shifting means. a base of the first transistor and a terminal of the second transistor;
A set input signal and a set input control signal are supplied to the bases of the fourth transistor and the fifth transistor.
A reset input signal and a reset input control signal are supplied to the base of the transistor, and the set input signal, the reset input signal,
The set input control signal and the reset input control signal are binary signals having the same level relationship, and the binary signal corresponds to the output signal taken out from the first output terminal and the second output terminal. A flip-flop characterized by having a predetermined voltage level shifted and having substantially equal logic amplitudes.