JPH0575100A - Semiconductor rectifier - Google Patents
Semiconductor rectifierInfo
- Publication number
- JPH0575100A JPH0575100A JP26127591A JP26127591A JPH0575100A JP H0575100 A JPH0575100 A JP H0575100A JP 26127591 A JP26127591 A JP 26127591A JP 26127591 A JP26127591 A JP 26127591A JP H0575100 A JPH0575100 A JP H0575100A
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- JP
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- Prior art keywords
- semiconductor region
- main surface
- semiconductor
- schottky junction
- conductivity type
- Prior art date
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Abstract
(57)【要約】
【目的】 リーク電流の少ない半導体整流素子素子得
る。
【構成】 半導体基体１の一対の主表面間に、一方の主
表面１１に隣接する第１導電型の第１の半導体領域１３
と、他方の主表面１２及び前記の第１の半導体領域に隣
接し、第１の半導体領域より高不純物濃度を有する第１
導電型の第２の半導体領域１４と、一方の主表面上で第
１の半導体領域との間にショットキー接合を形成する第
１の主電極２と、他方の主表面で第２の半導体領域とオ
ーミック接触する第２の主電極３と、ショットキー接合
の周辺部に一方の主表面上から第１の半導体領域内に延
在し第１の主電極に接する第２導電型の第３の半導体領
域１５によるガードリングと、さらにその内側に第３の
半導体領域よりも低不純物濃度を有する第２導電型の第
４の半導体領域を第３の半導体領域に接するように形成
して構成される。
(57) [Abstract] [Purpose] To obtain a semiconductor rectifier element with little leakage current. A first conductivity type first semiconductor region 13 adjacent to one main surface 11 between a pair of main surfaces of a semiconductor substrate 1.
A first adjacent to the other main surface 12 and the first semiconductor region and having a higher impurity concentration than the first semiconductor region.
A second semiconductor region 14 of conductivity type, a first main electrode 2 forming a Schottky junction between the first semiconductor region on one main surface, and a second semiconductor region on the other main surface. A second main electrode 3 in ohmic contact with the second main electrode 3 extending in the first semiconductor region from one main surface in the peripheral portion of the Schottky junction and in contact with the first main electrode. The semiconductor region 15 is formed of a guard ring, and a fourth semiconductor region of the second conductivity type having a lower impurity concentration than that of the third semiconductor region is formed inside the guard ring so as to be in contact with the third semiconductor region. ..
Description
【０００１】[0001]
【産業上の利用分野】本発明は、半導体整流素子に係
り、特に、リーク電流の少ない半導体整流素子に関す
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor rectifying device, and more particularly to a semiconductor rectifying device having a small leak current.
【０００２】[0002]
【従来の技術】代表的な半導体整流素子として、ショッ
トキーダイオード、ｐｎダイオードが知られている。こ
のうち、ショットキーダイオードは、ｐｎダイオードに
比べ順方向電圧降下が小さいという利点を有するが、一
方、耐圧が低く、またリーク電流が大きいという問題点
を有している。2. Description of the Related Art Schottky diodes and pn diodes are known as typical semiconductor rectifiers. Among them, the Schottky diode has an advantage that the forward voltage drop is smaller than that of the pn diode, but has the problem that the Schottky diode has a low breakdown voltage and a large leak current.
【０００３】ショットキーダイオードの耐圧を向上させ
るための従来技術として、例えば、ＩＥＥＥ Ｔｒａｎ
ｓ Ｖｏｌ．ＥＤ−１６（ ’９１） ｐ５８〜６３等
に記載された技術が知られている。As a conventional technique for improving the breakdown voltage of a Schottky diode, for example, IEEE Tran
s Vol. The technique described in ED-16 ('91) p58-63 and the like is known.
【０００４】この従来技術は、素子の構造上、逆バイア
ス時に電界が強まりやすく、このため、ショットキー接
合部の耐圧が低くなるショットキーダイオードの耐圧向
上のため、ショットキー接合端部にガードリングとして
ｐｎ接合を設け、この部分の耐圧の向上を図ることによ
り、素子の耐圧を向上させるというものである。以下、
この従来技術を図面により説明する。In this prior art, due to the structure of the device, the electric field is apt to be strengthened at the time of reverse bias, and therefore the breakdown voltage of the Schottky junction, which is low, is improved. As a result, a pn junction is provided and the withstand voltage of this portion is improved to improve the withstand voltage of the device. Less than,
This conventional technique will be described with reference to the drawings.
【０００５】図８は従来技術によるガードリング付きシ
ョットキーダイオード構造を示す断面図、図９は図８に
おけるショットキーダイオードの端部構造を拡大して、
等ポテンシャル線を示した図である。図８、図９におい
て、１は半導体基体、２、３は主電極、４は絶縁膜、１
１、１２は主表面、１３は第１の半導体領域、１４は第
２の半導体領域、１５は第３の半導体領域である。FIG. 8 is a sectional view showing a conventional Schottky diode structure with a guard ring, and FIG. 9 is an enlarged view of an end structure of the Schottky diode in FIG.
It is the figure which showed the equipotential line. In FIGS. 8 and 9, 1 is a semiconductor substrate, 2 and 3 are main electrodes, 4 is an insulating film, 1
Reference numerals 1 and 12 are main surfaces, 13 is a first semiconductor region, 14 is a second semiconductor region, and 15 is a third semiconductor region.
【０００６】図８に示す従来技術は、半導体基体１の互
いに反対側に位置する一対の主表面１１、１２間に、一
方の主表面１１に隣接する第一導電型の第１の半導体領
域１３と、他方の主表面１２及び前記の第１の半導体領
域１３に隣接し、第１の半導体領域１３より高不純物濃
度を有する第１導電型の第２の半導体領域１４と、一方
の主表面上１１で第１の半導体領域１３との間にショッ
トキー接合を形成する第１の主電極２と、他方の主表面
１２で第２の半導体領域１４とオーミック接触する第２
の主電極３とを備えて構成され、さらに、前記ショット
キー接合の周辺部に一方の主表面１１上から第１の半導
体領域１３内に延在し第１の主電極３に接する第２導電
型の第３の半導体領域１５とを備えて構成されている。In the prior art shown in FIG. 8, a first conductivity type first semiconductor region 13 adjacent to one main surface 11 is provided between a pair of main surfaces 11 and 12 located on opposite sides of a semiconductor substrate 1. A second semiconductor region 14 of the first conductivity type which is adjacent to the other main surface 12 and the first semiconductor region 13 and has a higher impurity concentration than that of the first semiconductor region 13, and on one main surface A first main electrode 2 forming a Schottky junction with the first semiconductor region 13 at 11 and a second main electrode 12 making ohmic contact with the second semiconductor region 14 at the other main surface 12.
And a main electrode 3 of the second conductivity type, which further extends from above the one main surface 11 into the first semiconductor region 13 in the peripheral portion of the Schottky junction and is in contact with the first main electrode 3. And a third semiconductor region 15 of the mold.
【０００７】この従来技術によるショットキーダイオー
ドは、第２導電型の第３の半導体領域１５と第１の半導
体領域１３とのｐｎ接合によるガードリングを備えるこ
とにより、耐圧の向上を図ることができるものである。This Schottky diode according to the prior art is provided with a guard ring formed by a pn junction between the third semiconductor region 15 of the second conductivity type and the first semiconductor region 13, so that the breakdown voltage can be improved. It is a thing.
【０００８】この従来技術によるショットキーダイオー
ドのガードリング近傍の端部構造を拡大し、第１の半導
体領域内の等ポテンシャル線を示すと、図９に示すよう
になる。この図から、印加電圧の上昇に伴い、素子端部
に形成されたｐｎ接合部によるガードリングの近傍の等
ポテンシャル線５１の密度が高くなり電界が強まること
が判る。この結果、前記従来技術は、この部分に近いシ
ョットキー接合部の表面電界が強まり、この部分でバリ
アハイトの低下が起こり、リーク電流が急増するもので
ある。FIG. 9 is an enlarged view of the end structure in the vicinity of the guard ring of the Schottky diode according to the prior art, showing the equipotential lines in the first semiconductor region. From this figure, it can be seen that as the applied voltage rises, the density of the equipotential lines 51 near the guard ring formed by the pn junction formed at the end of the element increases and the electric field increases. As a result, in the conventional technique, the surface electric field of the Schottky junction near this portion is strengthened, the barrier height is lowered in this portion, and the leak current is rapidly increased.
【０００９】[0009]
【発明が解決しようとする課題】前述したように、従来
技術によるガードリング付きショットキーダイオード
は、ガードリングにより耐圧の向上を図ることができる
という利点を有するが、一方、印加電圧の上昇に伴い、
端部に設けたｐｎ接合部近傍での電界が強まるために、
この部分に近いショットキー接合部の表面電界が強ま
り、この部分でバリアハイトの低下が起こりリーク電流
が急増するという問題点を有している。As described above, the Schottky diode with a guard ring according to the prior art has the advantage that the breakdown voltage can be improved by the guard ring, but on the other hand, as the applied voltage rises. ,
Since the electric field near the pn junction provided at the end is strengthened,
There is a problem that the surface electric field of the Schottky junction portion near this portion is strengthened, the barrier height is lowered in this portion, and the leak current is rapidly increased.
【００１０】本発明の目的は、前記従来技術の問題点を
解決し、印加電圧の上昇に伴うリーク電流の急増を抑
え、従来技術に比較してリーク電流の少ない半導体整流
素子を提供することにある。An object of the present invention is to provide a semiconductor rectifying device which solves the above-mentioned problems of the prior art, suppresses a sudden increase in leak current due to an increase in applied voltage, and has a smaller leak current than the prior art. is there.
【００１１】[0011]
【課題を解決するための手段】本発明によれば前記目的
は、前述の従来技術による半導体整流素子において、第
３の半導体領域に接し、ショットキー接合部の周辺を取
り囲むように、第１の半導体領域内に、第３の半導体領
域よりも低不純物濃度を有する第２導電型の第４の半導
体領域を形成することにより、また、第１の主電極を第
１の半導体領域との間で異なるバリアハイトを有するシ
ョットキー接合を形成する２種類の導電体から構成し、
素子端部に近い外周側に第３の半導体領域に接してバリ
アハイトの高いショットキー接合部を形成する導電体を
用いることにより、あるいは、第３の半導体領域が形成
される側の主表面に凹部を設け、第３の半導体領域とシ
ョットキー接合部とが交わる部分をこの凹部に形成する
ことにより達成される。According to the present invention, the above-mentioned object is to provide a first semiconductor rectifying device according to the above-mentioned prior art so as to contact the third semiconductor region and surround the periphery of the Schottky junction. By forming a fourth semiconductor region of the second conductivity type having a lower impurity concentration than that of the third semiconductor region in the semiconductor region, the first main electrode is formed between the fourth semiconductor region and the first semiconductor region. It is composed of two kinds of conductors that form Schottky junctions having different barrier heights,
By using a conductor that forms a Schottky junction having a high barrier height in contact with the third semiconductor region on the outer peripheral side near the element end, or by forming a recess on the main surface on the side where the third semiconductor region is formed. And forming a portion where the third semiconductor region and the Schottky junction intersect with each other in this recess.
【００１２】[0012]
【作用】本発明による半導体整流素子における第４の半
導体領域は、第１の半導体領域と第３の半導体領域との
接合付近に生じる電界を緩和する作用を有し、これによ
り、ショットキー接合端部の電界を弱め、この電界によ
るショットキーバリアの低下を防ぐことができる。The fourth semiconductor region in the semiconductor rectifying device according to the present invention has a function of relaxing an electric field generated in the vicinity of the junction between the first semiconductor region and the third semiconductor region, whereby the Schottky junction end. It is possible to weaken the electric field of the portion and prevent the Schottky barrier from being lowered by this electric field.
【００１３】また、バリアハイトの高いショットキー接
合部を形成する導電体は、電界の強い部分のショットキ
ー接合部のバリアハイトを高くすることができる。Further, the conductor forming the Schottky junction having a high barrier height can increase the barrier height of the Schottky junction in a portion having a strong electric field.
【００１４】さらに、凹を設けることにより、ｐｎ接合
部とショットキー接合部とを鈍角で交叉させることがで
き、これにより、ショットキー接合端部の電界を弱める
ことができる。Further, by providing the recess, the pn junction and the Schottky junction can be intersected at an obtuse angle, and the electric field at the Schottky junction end can be weakened.
【００１５】本発明は、これらにより、逆方向電圧印加
時のリーク電流の上昇を抑えることができる。The present invention makes it possible to suppress an increase in leak current when a reverse voltage is applied.
【００１６】[0016]
【実施例】以下、本発明による半導体整流素子の実施例
を図面により詳細に説明する。Embodiments of the semiconductor rectifying device according to the present invention will be described below in detail with reference to the drawings.
【００１７】図１は本発明の第１の実施例を示す素子の
断面図、図２は図１におけるショットキーダイオードの
端部構造を拡大して、等ポテンシャル線を示した図、図
３は逆バイアス電圧ＶRとリーク電流ＩRとの関係を説明
する図である。図１、図２において、１６は第４の半導
体領域であり、他の符号は図８の場合と同一である。FIG. 1 is a sectional view of an element showing a first embodiment of the present invention, FIG. 2 is an enlarged view of an end structure of the Schottky diode in FIG. 1 and shows equipotential lines, and FIG. it is a diagram illustrating the relationship between the reverse bias voltage V R and the leakage current I R. In FIGS. 1 and 2, 16 is a fourth semiconductor region, and other reference numerals are the same as those in FIG.
【００１８】図１に示す本発明の第１の実施例におい
て、半導体基体１は、互いに反対側に位置する一対の主
表面１１、１２を有し、主表面間には一方の主表面１１
に隣接する第１導電型の第１の半導体領域１３と、他方
の主表面１２及び前記の第１の半導体領域１３に隣接
し、第１の半導体領域１３より高不純物濃度を有する第
１導電型の第２の半導体領域１４とを備えている。第１
の主電極２は、一方の主表面１１上で第１の半導体領域
１３との間にショットキー接合を形成する電極であり、
Ａｌ、Ｍｏ、Ｔｉ等の材料により形成される。第２の主
電極３は、他方の主表面１２上で第２の半導体領域１４
とオーミック接触する電極である。In the first embodiment of the present invention shown in FIG. 1, the semiconductor substrate 1 has a pair of main surfaces 11 and 12 located on opposite sides of each other, and one main surface 11 is located between the main surfaces.
The first conductivity type first semiconductor region 13 adjacent to the first conductivity type, and the first conductivity type adjacent to the other main surface 12 and the first semiconductor region 13 and having a higher impurity concentration than the first semiconductor region 13. Second semiconductor region 14 of. First
Main electrode 2 is an electrode that forms a Schottky junction with the first semiconductor region 13 on one main surface 11.
It is formed of a material such as Al, Mo, or Ti. The second main electrode 3 has the second semiconductor region 14 on the other main surface 12.
The electrode is in ohmic contact with.
【００１９】そして、前記ショットキー接合の周辺部に
は、一方の主表面上から第１の半導体領域１３内に延在
する、第１の主電極３に接する第２導電型の第３の半導
体領域１５によるガードリングと、その内側に第３の半
導体領域に接して第３の半導体領域よりも低不純物濃度
を有する第２導電型の第４の半導体領域１６とが形成さ
れている。Then, in the peripheral portion of the Schottky junction, a second semiconductor of the second conductivity type extending from the one main surface into the first semiconductor region 13 and in contact with the first main electrode 3. A guard ring formed of the region 15 and a second conductivity type fourth semiconductor region 16 having a lower impurity concentration than the third semiconductor region are formed inside the guard ring and are in contact with the third semiconductor region.
【００２０】なお、第１の主電極２と第１の半導体領域
１３との間でショットキー接合を形成する部分は、第３
の半導体領域１５によるガードリングの内側のみであ
り、ガードリングの外側の第１の半導体領域１３の主表
面１１は、絶縁膜４により覆われている。また、ガード
リングの平面形状は、一般には円形に形成されるが、四
角形、多角形等任意の形状とすることができる。The portion forming the Schottky junction between the first main electrode 2 and the first semiconductor region 13 is the third portion.
The main surface 11 of the first semiconductor region 13 outside the guard ring is covered with the insulating film 4 only inside the guard ring formed by the semiconductor region 15. Further, the plane shape of the guard ring is generally formed in a circular shape, but may be any shape such as a quadrangle or a polygon.
【００２１】前述の用に構成される本発明の第１の実施
例によるダイオードは、第１の半導体領域１３内に、第
３の半導体領域１５よりも低不純物濃度を有する第２導
電型の第４の半導体領域１６を新たに設けている点で、
図８により説明した従来技術のダイオードと相違し、そ
の他の点では従来技術の場合と同様に形成されいる。The diode according to the first embodiment of the present invention configured as described above has a second conductivity type second diode having a lower impurity concentration in the first semiconductor region 13 than in the third semiconductor region 15. In that the semiconductor region 16 of 4 is newly provided,
The diode is different from the conventional diode described with reference to FIG. 8 and is otherwise formed similarly to the conventional diode.
【００２２】次に、この本発明の第１の従来技術によ
り、リーク電流が低減される理由について説明する。Next, the reason why the leakage current is reduced by the first conventional technique of the present invention will be described.
【００２３】電界強度は電位勾配で決まるため、等ポテ
ンシャル線の密度が高いほど電界強度が大きい。図９に
示すように、従来技術によるショットキーダイオード内
部は、素子端部のｐｎ接合部のポテンシャル分布が密と
なって、電界強度が強くなっている。このため、従来技
術によるダイオードは、素子中央のショットキー接合部
のポテンシャル分布に比べ、ｐｎ接合部に近い端部近傍
のショットキー接合部におけるポテンシャル分布が密と
なり、この部分で電界強度の増加が生じている。Since the electric field strength is determined by the potential gradient, the electric field strength increases as the density of the equipotential lines increases. As shown in FIG. 9, in the Schottky diode according to the related art, the electric field strength is high because the potential distribution of the pn junction at the device end is dense. Therefore, in the diode according to the related art, the potential distribution in the Schottky junction near the end near the pn junction is denser than that in the Schottky junction in the center of the device, and the electric field strength increases at this portion. Has occurred.
【００２４】ショットキー接合部のリーク電流は、その
接合部の電界強度に大きく依存して変化し、電界強度が
強いとリーク電流が増加する。従って、従来技術による
ダイオードは、逆バイアス電圧の増加と共に端部電界が
増加してリーク電流が急増する。The leakage current of the Schottky junction changes largely depending on the electric field strength of the junction, and when the electric field strength is strong, the leakage current increases. Therefore, in the diode according to the related art, the electric field at the end portion increases with an increase in the reverse bias voltage, and the leakage current sharply increases.
【００２５】一方、本発明によるダイオードは、図２に
示すような、素子端部構造と、逆バイアス時の等ポテン
シャル線５２の分布を有している。この図から判るよう
に、図１に示す本発明の第１の実施例によるダイオード
は、新たに設けた第４の半導体領域１６の周辺における
ポテンシャル線の間隔が、第３の半導体領域１５の近傍
のポテンシャル線の間隔に比較して広く、電界が緩和さ
れていることが判る。この結果、本発明の第１の実施例
は、ショットキー接合端部のポテンシャル線の間隔を、
従来技術の場合より広くすることができ、素子中央部の
ポテンシャル線と同程度とすることができ、素子端部の
ショットキー接合部のリーク電流の増加を低く保つこと
ができる。On the other hand, the diode according to the present invention has the element end structure and the distribution of the equipotential lines 52 at the time of reverse bias as shown in FIG. As can be seen from this figure, in the diode according to the first embodiment of the present invention shown in FIG. 1, the distance between the potential lines around the newly provided fourth semiconductor region 16 is in the vicinity of the third semiconductor region 15. It can be seen that the electric field is relaxed because it is wider than the interval of the potential lines of. As a result, in the first embodiment of the present invention, the spacing between the potential lines at the Schottky junction end is
It can be made wider than in the case of the prior art, can be made to be almost the same as the potential line in the central portion of the element, and the increase in the leak current at the Schottky junction at the element end can be kept low.
【００２６】図３には、素子の逆バイアス電圧ＶRとリ
ーク電流ＩRとの関係が示されているが、点線で示す従
来技術のダイオードが逆バイアス電圧ＶR の増加と共
に、リーク電流ＩR が急増しているのに対して、実線で
示す本発明の第１の実施例によるダイオードは、逆バイ
アス電圧ＶRを上げたときのリーク電流ＩRが低く保たれ
ていることが判る。FIG. 3 shows the relationship between the reverse bias voltage V R of the device and the leak current I R. In the diode of the prior art shown by the dotted line, the leak current I increases as the reverse bias voltage V R increases. It can be seen that, while R increases sharply, the diode according to the first embodiment of the present invention shown by the solid line keeps the leakage current I R low when the reverse bias voltage V R is increased.
【００２７】図４は本発明の第２の実施例を示す素子の
断面図である。図４において、１７は第５の半導体領域
であり、他の符号は図１の場合と同一である。FIG. 4 is a sectional view of an element showing a second embodiment of the present invention. In FIG. 4, 17 is a fifth semiconductor region, and other reference numerals are the same as those in FIG.
【００２８】この本発明の第２の実施例は、図１により
説明した本発明の第１の実施例において、第３の半導体
領域よりも低不純物濃度を有する第２導電型の第５の半
導体領域１７を、第３の半導体領域の外周側に設けて構
成したものである。The second embodiment of the present invention is the fifth semiconductor of the second conductivity type which has a lower impurity concentration than the third semiconductor region in the first embodiment of the present invention described with reference to FIG. The region 17 is provided on the outer peripheral side of the third semiconductor region.
【００２９】本発明の第２の実施例は、第４の半導体領
域１６によるリーク電流の低減に加え、第５の半導体領
域１７により、第３の半導体領域１５の外周部における
ｐｎ接合部の電界緩和を図ることができ、耐圧の向上を
図ることができるという効果を得ることができる。In the second embodiment of the present invention, in addition to the reduction of the leakage current by the fourth semiconductor region 16, the fifth semiconductor region 17 causes the electric field of the pn junction in the outer peripheral portion of the third semiconductor region 15. It is possible to obtain an effect that it is possible to alleviate and to improve the breakdown voltage.
【００３０】図５は本発明の第３の実施例を示す素子の
断面図である。図５において、２１は第１の導電体、２
２は第２の導電体であり、他の符号は図１の場合と同一
である。FIG. 5 is a sectional view of an element showing a third embodiment of the present invention. In FIG. 5, 21 is a first conductor, 2
Reference numeral 2 is a second conductor, and other reference numerals are the same as those in FIG.
【００３１】この本発明の第３の実施例は、図８により
説明した従来技術によるダイオードにおいて、第１の主
電極２を、第１の半導体領域との間で異なるバリアハイ
トを有するショットキー接合を形成することのできる２
種類のメタルから構成したものである。すなわち、素子
中央部の第１の導電体２１に対し、素子端部に近い外周
側には第３の半導体領域に接してバリアハイトの高いシ
ョットキー接合部を形成する第１の導電体とは別の第２
の導電体２２が用いられている。In the third embodiment of the present invention, in the diode according to the prior art described with reference to FIG. 8, the first main electrode 2 is formed with a Schottky junction having a barrier height different from that of the first semiconductor region. 2 that can be formed
It is composed of various types of metal. That is, with respect to the first conductor 21 in the central portion of the element, it is different from the first conductor which forms a Schottky junction portion having a high barrier height in contact with the third semiconductor region on the outer peripheral side near the end portion of the element. Second
The conductor 22 is used.
【００３２】これにより、この本発明の第３の実施例
は、図９に示した電界強度の大きい部分のショットキー
接合のバリアハイトを高くすることができるため、電界
強度の増加に伴うリーク電流の急増を抑えることがで
き、図１により説明した本発明の第１の実施例の場合と
同様の効果を得ることができる。As a result, according to the third embodiment of the present invention, the barrier height of the Schottky junction in the portion where the electric field strength is large as shown in FIG. 9 can be increased, so that the leakage current due to the increase of the electric field strength is increased. The sudden increase can be suppressed, and the same effect as that of the first embodiment of the present invention described with reference to FIG. 1 can be obtained.
【００３３】図６は本発明の第４の実施例を示す素子の
断面図である。図６における符号は図８の場合と同一で
ある。FIG. 6 is a sectional view of an element showing a fourth embodiment of the present invention. The reference numerals in FIG. 6 are the same as those in FIG.
【００３４】この本発明の第３の実施例は、第３の半導
体領域１５を形成する側の主表面１１に凹部を設け、第
３の半導体領域１５の少なくとも一部とショットキー接
合部をこの凹部に形成して構成されている。In the third embodiment of the present invention, a recess is provided in the main surface 11 on the side where the third semiconductor region 15 is formed, and at least a part of the third semiconductor region 15 and the Schottky junction are formed. It is formed in the recess.
【００３５】この実施例は、ｐｎ接合とショットキー接
合部とが鈍角で交わるため、第３の半導体領域１５の内
周部におけるｐｎ接合部近傍の電界の変化を滑らかにす
ることができ、図９に示すような局所的な電界強度の増
加を生じさせることがなく、ショットキー接合部の端部
におけるリーク電流の急増を抑えることができるもので
ある。In this embodiment, since the pn junction and the Schottky junction intersect at an obtuse angle, it is possible to smooth the change of the electric field in the vicinity of the pn junction in the inner peripheral portion of the third semiconductor region 15. It is possible to suppress a sudden increase in leak current at the end of the Schottky junction without causing a local increase in electric field strength as shown in FIG.
【００３６】なお、前述の図５、図６に示した本発明の
第３、第４の実施例は、さらに、図４により説明した第
５の半導体領域を設けるように変形することができ、こ
れにより、これらの実施例においても、耐圧の向上を図
ることができる。The third and fourth embodiments of the present invention shown in FIGS. 5 and 6 can be further modified to provide the fifth semiconductor region described with reference to FIG. As a result, the withstand voltage can be improved also in these embodiments.
【００３７】図７は本発明の第５の実施例を示す素子の
断面図であり、図の符号は図８の場合と同一である。FIG. 7 is a sectional view of an element showing a fifth embodiment of the present invention, and the reference numerals in the figure are the same as those in FIG.
【００３８】この本発明の第５の実施例は、従来技術の
場合と同様に第３の半導体領域１５を形成後、その第１
の主表面側の点線で示す部分を一部削った後、表面に電
極を形成したものである。In the fifth embodiment of the present invention, as in the case of the prior art, after the third semiconductor region 15 is formed, the first semiconductor region 15 is formed.
The electrode is formed on the surface after a part of the main surface side indicated by the dotted line is shaved.
【００３９】この実施例は、これにより、第３の半導体
領域１５と第１の半導体領域１３とによるｐｎ接合とシ
ョットキー接合部とが鈍角で交わることになり、図６に
より説明した本発明の第４の実施例と同様、端部ショッ
トキー接合部のリーク電流の急増を抑えることができる
ものである。In this embodiment, this causes the pn junction and the Schottky junction formed by the third semiconductor region 15 and the first semiconductor region 13 to intersect at an obtuse angle. Similar to the fourth embodiment, it is possible to suppress a sudden increase in the leak current at the end Schottky junction.
【００４０】以上、本発明による半導体整流素子を代表
的な実施例を用いて説明したが、本発明は、これらの実
施例に限定されるものではなく、本発明の技術思想内で
種々の変更が可能である。The semiconductor rectifying device according to the present invention has been described above by using the typical embodiments, but the present invention is not limited to these embodiments, and various modifications can be made within the technical idea of the present invention. Is possible.
【００４１】[0041]
【発明の効果】以上説明したように本発明によれば、従
来技術による半導体整流素子に比べリーク電流の少ない
優れた半導体整流素子を提供することができる。As described above, according to the present invention, it is possible to provide an excellent semiconductor rectifier having less leakage current than the conventional semiconductor rectifier.
【図１】本発明の第１の実施例を示す素子の断面図であ
る。FIG. 1 is a sectional view of an element showing a first embodiment of the present invention.
【図２】図１におけるショットキーダイオードの端部構
造を拡大して、等ポテンシャル線を示した図である。FIG. 2 is an enlarged view of an end potential structure of the Schottky diode in FIG. 1 showing equipotential lines.
【図３】逆バイアス電圧ＶRとリーク電流ＩRとの関係を
説明する図である。FIG. 3 is a diagram illustrating a relationship between a reverse bias voltage V R and a leak current I R.
【図４】本発明の第２の実施例を示す素子の断面図であ
る。FIG. 4 is a sectional view of an element showing a second embodiment of the present invention.
【図５】本発明の第３の実施例を示す素子の断面図であ
る。FIG. 5 is a cross-sectional view of an element showing a third embodiment of the present invention.
【図６】本発明の第４の実施例を示す素子の断面図であ
る。FIG. 6 is a sectional view of an element showing a fourth embodiment of the present invention.
【図７】本発明の第５の実施例を示す素子の断面図であ
る。FIG. 7 is a sectional view of an element showing a fifth embodiment of the present invention.
【図８】従来技術によるショットキーダイオードの構造
を示す断面図である。FIG. 8 is a sectional view showing a structure of a Schottky diode according to a conventional technique.
【図９】図８におけるショットキーダイオードの端部構
造を拡大して、等ポテンシャル線を示した図である。9 is a diagram showing an equipotential line by enlarging the end structure of the Schottky diode in FIG.
１ 半導体基体 ２、３ 主電極 ４ 絶縁膜 １１、１２ 主表面 １３ 第１の半導体領域 １４ 第２の半導体領域 １５ 第３の半導体領域 １６ 第４の半導体領域 １７ 第５の半導体領域 ２１ 第１の導電体 ２２ 第２の導電体 ５１、５２ 等ポテンシャル線 DESCRIPTION OF SYMBOLS 1 semiconductor base body 2, 3 main electrode 4 insulating film 11, 12 main surface 13 1st semiconductor region 14 2nd semiconductor region 15 3rd semiconductor region 16 4th semiconductor region 17 5th semiconductor region 21 1st Conductor 22 Second conductor 51, 52 Equipotential line
Claims (9)
付きの半導体整流素子において、前記ガードリングは、
該ガードリングと該ガードリングを内在させている半導
体領域とによるｐｎ接合部が前記ショットキー接合と鈍
角で交叉するように形成されることを特徴とする半導体
整流素子。1. A semiconductor rectifying device with a guard ring having a Schottky junction, wherein the guard ring is
A semiconductor rectifying device, characterized in that a pn junction portion formed by the guard ring and a semiconductor region having the guard ring therein is formed so as to intersect the Schottky junction at an obtuse angle.
付きの半導体整流素子において、半導体領域との間で前
記ショットキー接合を形成する電極を、異なるバリアハ
イトのショットキー接合を形成する２種類の導電体によ
り構成し、素子端部の外周側にバリアハイトの高いショ
ットキー接合部を形成したことを特徴とする半導体整流
素子。2. In a semiconductor rectifying device with a guard ring having a Schottky junction, two types of conductors that form Schottky junctions with semiconductor regions and Schottky junctions having different barrier heights are used. And a Schottky junction portion having a high barrier height is formed on the outer peripheral side of the element end portion.
主表面に隣接する第１導電型の第１の半導体領域と、他
方の主表面及び前記の第１の半導体領域に隣接し、前記
第１の半導体領域より高不純物濃度を有する第１導電型
の第２の半導体領域と、一方の主表面上で第１の半導体
領域との間にショットキー接合を形成する第１の主電極
と、他方の主表面で第２の半導体領域とオーミック接触
する第２の主電極とを備え、かつ、前記ショットキー接
合の周辺部に一方の主表面上から第１の半導体領域内に
延在し第１の主電極に接する第２導電型の第３の半導体
領域とを備えて構成されるガードリング付きの整流素子
において、前記第３の半導体領域の内周側にショットキ
ー接合部の周辺を取り囲むように第１の半導体領域内
に、第３の半導体領域よりも低不純物濃度を有する第２
導電型の第４の半導体領域を形成したことを特徴とする
半導体整流素子。3. A first semiconductor region of a first conductivity type adjacent to one main surface, between the pair of main surfaces of the semiconductor substrate, and adjacent to the other main surface and the first semiconductor region, A first main electrode forming a Schottky junction between a second semiconductor region of the first conductivity type having a higher impurity concentration than that of the first semiconductor region and the first semiconductor region on one main surface. And a second main electrode that makes ohmic contact with the second semiconductor region on the other main surface, and extends from the one main surface into the first semiconductor region in the peripheral portion of the Schottky junction. A rectifying element with a guard ring configured to include a third semiconductor region of a second conductivity type in contact with the first main electrode, the periphery of the Schottky junction being on the inner peripheral side of the third semiconductor region. A third semiconductor region in the first semiconductor region so as to surround the Second with a lower impurity concentration than
A semiconductor rectifying device, wherein a conductive fourth semiconductor region is formed.
主表面に隣接する第１導電型の第１の半導体領域と、他
方の主表面及び前記の第１の半導体領域に隣接し、前記
第１の半導体領域より高不純物濃度を有する第１導電型
の第２の半導体領域と、一方の主表面上で第１の半導体
領域との間にショットキー接合を形成する第１の主電極
と、他方の主表面で第２の半導体領域とオーミック接触
する第２の主電極とを備え、かつ、前記ショットキー接
合の周辺部に一方の主表面上から第１の半導体領域内に
延在し第１の主電極に接する第２導電型の第３の半導体
領域とを備えて構成されるガードリング付きの整流素子
において、前記第１の主電極を第１の半導体領域との間
で異なるバリアハイトを有するショットキー接合を形成
する２種類の導電体により構成し、素子端部に近い外周
側に前記第３の半導体領域に接してバリアハイトの高い
ショットキー接合部を形成したことを特徴とする半導体
整流素子。4. A first semiconductor region of a first conductivity type, which is adjacent to one main surface, and between the other main surface and the first semiconductor region, between a pair of main surfaces of a semiconductor substrate, A first main electrode forming a Schottky junction between a second semiconductor region of the first conductivity type having a higher impurity concentration than that of the first semiconductor region and the first semiconductor region on one main surface. And a second main electrode that makes ohmic contact with the second semiconductor region on the other main surface, and extends from the one main surface into the first semiconductor region in the peripheral portion of the Schottky junction. A third semiconductor region of the second conductivity type in contact with the first main electrode, the rectifying element with a guard ring, wherein the first main electrode is different from the first semiconductor region. Two kinds of conductors forming a Schottky junction having a barrier height And a Schottky junction having a high barrier height is formed on the outer peripheral side near the element end in contact with the third semiconductor region.
主表面に隣接する第１導電型の第１の半導体領域と、他
方の主表面及び前記の第１の半導体領域に隣接し、前記
第１の半導体領域より高不純物濃度を有する第１導電型
の第２の半導体領域と、一方の主表面上で第１の半導体
領域との間にショットキー接合を形成する第１の主電極
と、他方の主表面で第２の半導体領域とオーミック接触
する第２の主電極とを備え、かつ、前記ショットキー接
合の周辺部に一方の主表面上から第１の半導体領域内に
延在し第１の主電極に接する第２導電型の第３の半導体
領域とを備えて構成されるガードリング付きの整流素子
において、前記第３の半導体領域形成後の表面を一部削
った後、第１の主電極を形成することにより、前記第３
の半導体領域が前記ショットキー接合と鈍角で交叉する
ように形成されることを特徴とする半導体整流素子。5. A first semiconductor region of a first conductivity type, which is adjacent to one of the main surfaces, and between the other main surface and the first semiconductor region, between a pair of main surfaces of the semiconductor substrate. A first main electrode forming a Schottky junction between a second semiconductor region of the first conductivity type having a higher impurity concentration than that of the first semiconductor region and the first semiconductor region on one main surface. And a second main electrode that makes ohmic contact with the second semiconductor region on the other main surface, and extends from the one main surface into the first semiconductor region in the peripheral portion of the Schottky junction. In a rectifying device with a guard ring, which is configured to include a third semiconductor region of the second conductivity type that is in contact with the first main electrode, after partially scraping the surface after the formation of the third semiconductor region, By forming the first main electrode, the third main electrode is formed.
The semiconductor rectifying device is characterized in that the semiconductor region of is crossed with the Schottky junction at an obtuse angle.
主表面に隣接する第１導電型の第１の半導体領域と、他
方の主表面及び前記の第１の半導体領域に隣接し、前記
第１の半導体領域より高不純物濃度を有する第１導電型
の第２の半導体領域と、一方の主表面上で第１の半導体
領域との間にショットキー接合を形成する第１の主電極
と、他方の主表面で第２の半導体領域とオーミック接触
する第２の主電極とを備え、かつ、前記ショットキー接
合の周辺部に一方の主表面上から第１の半導体領域内に
延在し第１の主電極に接する第２導電型の第３の半導体
領域とを備えて構成されるガードリング付きの整流素子
において、前記第３の半導体領域を形成する側の主表面
に凹部を設け、前記第３の半導体領域とショットキー接
合部とが交わる部分をこの凹部に形成したことを特徴と
する半導体整流素子。6. A first semiconductor region of a first conductivity type, which is adjacent to one main surface, is adjacent to a pair of main surfaces of the semiconductor substrate, and is adjacent to the other main surface and the first semiconductor region. A first main electrode forming a Schottky junction between a second semiconductor region of the first conductivity type having a higher impurity concentration than that of the first semiconductor region and the first semiconductor region on one main surface. And a second main electrode that makes ohmic contact with the second semiconductor region on the other main surface, and extends from the one main surface into the first semiconductor region in the peripheral portion of the Schottky junction. In a rectifying element with a guard ring, which is configured to include a third semiconductor region of the second conductivity type that is in contact with the first main electrode, a recess is provided in the main surface on the side where the third semiconductor region is formed. , Where the third semiconductor region and the Schottky junction intersect A semiconductor rectifying device having a recess formed in the recess.
主表面に隣接する第１導電型の第１の半導体領域と、他
方の主表面及び前記の第１の半導体領域に隣接し、前記
第１の半導体領域より高不純物濃度を有する第１導電型
の第２の半導体領域と、一方の主表面上で第１の半導体
領域との間にショットキー接合を形成する第１の主電極
と、他方の主表面で第２の半導体領域とオーミック接触
する第２の主電極とを備え、かつ、前記ショットキー接
合の周辺部に一方の主表面上から第１の半導体領域内に
延在し第１の主電極に接する第２導電型の第３の半導体
領域とを備えて構成されるガードリング付きの整流素子
において、前記第３の半導体領域の内周側にショットキ
ー接合部の周辺を取り囲むように第１の半導体領域内
に、第３の半導体領域よりも低不純物濃度を有する第２
導電型の第４の半導体領域を形成すると共に、第３の半
導体領域よりも低不純物濃度を有する第２導電型の第５
の半導体領域を第３の半導体領域の外周側に形成したこ
とを特徴とする半導体整流素子。7. A first-conductivity-type first semiconductor region adjacent to one main surface, between the pair of main surfaces of the semiconductor substrate, and adjacent to the other main surface and the first semiconductor region, A first main electrode forming a Schottky junction between a second semiconductor region of the first conductivity type having a higher impurity concentration than that of the first semiconductor region and the first semiconductor region on one main surface. And a second main electrode in ohmic contact with the second semiconductor region on the other main surface, and extending from the one main surface into the first semiconductor region in the peripheral portion of the Schottky junction. A rectifying element with a guard ring, the rectifying element having a second conductivity type third semiconductor region in contact with the first main electrode, the Schottky junction being provided on the inner peripheral side of the third semiconductor region. A third semiconductor region in the first semiconductor region so as to surround the Second with a lower impurity concentration than
A fourth semiconductor region of the conductivity type is formed, and a fifth semiconductor of the second conductivity type having a lower impurity concentration than that of the third semiconductor region is formed.
The semiconductor rectifying device, wherein the semiconductor region is formed on the outer peripheral side of the third semiconductor region.
主表面に隣接する第１導電型の第１の半導体領域と、他
方の主表面及び前記の第１の半導体領域に隣接し、前記
第１の半導体領域より高不純物濃度を有する第１導電型
の第２の半導体領域と、一方の主表面上で第１の半導体
領域との間にショットキー接合を形成する第１の主電極
と、他方の主表面で第２の半導体領域とオーミック接触
する第２の主電極とを備え、かつ、前記ショットキー接
合の周辺部に一方の主表面上から第１の半導体領域内に
延在し第１の主電極に接する第２導電型の第３の半導体
領域とを備えて構成されるガードリング付きの整流素子
において、前記第１の主電極を第１の半導体領域との間
で異なるバリアハイトを有するショットキー接合を形成
する２種類の導電体により構成し、素子端部に近い外周
側に第３の半導体領域に接してバリアハイトの高いショ
ットキー接合部を形成すると共に、第３の半導体領域よ
りも低不純物濃度を有する第２導電型の第５の半導体領
域を第３の半導体領域の外周側に形成したことを特徴と
する半導体整流素子。8. Between a pair of main surfaces of a semiconductor substrate, a first semiconductor region of the first conductivity type adjacent to one main surface, and adjacent to the other main surface and the first semiconductor region, A first main electrode forming a Schottky junction between a second semiconductor region of the first conductivity type having a higher impurity concentration than that of the first semiconductor region and the first semiconductor region on one main surface. And a second main electrode that makes ohmic contact with the second semiconductor region on the other main surface, and extends from the one main surface into the first semiconductor region in the peripheral portion of the Schottky junction. In a rectifying element with a guard ring, the rectifying element having a second conductivity type third semiconductor region in contact with the first main electrode, the first main electrode being different from the first semiconductor region. Two kinds of conductors forming a Schottky junction having a barrier height And forming a Schottky junction portion having a high barrier height in contact with the third semiconductor region on the outer peripheral side close to the device end portion, and having a second impurity type having a lower impurity concentration than the third semiconductor region. 5. A semiconductor rectifying device, wherein the semiconductor region 5 is formed on the outer peripheral side of the third semiconductor region.
主表面に隣接する第１導電型の第１の半導体領域と、他
方の主表面及び前記の第１の半導体領域に隣接し、前記
第１の半導体領域より高不純物濃度を有する第１導電型
の第２の半導体領域と、一方の主表面上で第１の半導体
領域との間にショットキー接合を形成する第１の主電極
と、他方の主表面で第２の半導体領域とオーミック接触
する第２の主電極とを備え、かつ、前記ショットキー接
合の周辺部に一方の主表面上から第１の半導体領域内に
延在し第１の主電極に接する第２導電型の第３の半導体
領域とを備えて構成されるガードリング付きの整流素子
において、前記第３の半導体領域を形成する側の主表面
に凹部を設け、前記第３の半導体領域とショットキー接
合部とが交わる部分をこの凹部に形成すると共に、第３
の半導体領域よりも低不純物濃度を有する第２導電型の
第５の半導体領域を第３の半導体領域の外周側に形成し
たことを特徴とする半導体整流素子。9. A first semiconductor region of a first conductivity type adjacent to one main surface, between the pair of main surfaces of the semiconductor substrate, and adjacent to the other main surface and the first semiconductor region, A first main electrode forming a Schottky junction between a second semiconductor region of the first conductivity type having a higher impurity concentration than that of the first semiconductor region and the first semiconductor region on one main surface. And a second main electrode that makes ohmic contact with the second semiconductor region on the other main surface, and extends from the one main surface into the first semiconductor region in the peripheral portion of the Schottky junction. In a rectifying element with a guard ring, which is configured to include a third semiconductor region of the second conductivity type that is in contact with the first main electrode, a recess is provided in the main surface on the side where the third semiconductor region is formed. , Where the third semiconductor region and the Schottky junction intersect Is formed in this recess, and the third
5. A semiconductor rectifying device, characterized in that a fifth semiconductor region of the second conductivity type having a lower impurity concentration than that of the third semiconductor region is formed on the outer peripheral side of the third semiconductor region.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26127591A JP3117506B2 (en) | 1991-09-13 | 1991-09-13 | Semiconductor rectifier |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26127591A JP3117506B2 (en) | 1991-09-13 | 1991-09-13 | Semiconductor rectifier |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0575100A true JPH0575100A (en) | 1993-03-26 |
| JP3117506B2 JP3117506B2 (en) | 2000-12-18 |
Family
ID=17359560
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP26127591A Expired - Fee Related JP3117506B2 (en) | 1991-09-13 | 1991-09-13 | Semiconductor rectifier |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3117506B2 (en) |
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| JP2001094095A (en) * | 1999-09-21 | 2001-04-06 | Denso Corp | Silicon carbide semiconductor device and method of manufacturing the same |
| JP2001508950A (en) * | 1997-01-21 | 2001-07-03 | エービービー リサーチ リミテッド | Junction toe of silicon carbide Schottky diode |
| JP2009064977A (en) * | 2007-09-06 | 2009-03-26 | Renesas Technology Corp | Semiconductor device and manufacturing method thereof |
| JP2009516391A (en) * | 2005-11-15 | 2009-04-16 | ヴェロックス セミコンダクター コーポレーション | Second Schottky contact metal layer to improve Schottky diode performance |
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|---|---|---|---|---|
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| JP2001094095A (en) * | 1999-09-21 | 2001-04-06 | Denso Corp | Silicon carbide semiconductor device and method of manufacturing the same |
| JP2009516391A (en) * | 2005-11-15 | 2009-04-16 | ヴェロックス セミコンダクター コーポレーション | Second Schottky contact metal layer to improve Schottky diode performance |
| JP2009064977A (en) * | 2007-09-06 | 2009-03-26 | Renesas Technology Corp | Semiconductor device and manufacturing method thereof |
| JP2009277806A (en) * | 2008-05-13 | 2009-11-26 | Shindengen Electric Mfg Co Ltd | Semiconductor device |
| JP2013008997A (en) * | 2012-09-05 | 2013-01-10 | Renesas Electronics Corp | Semiconductor device |
| WO2014061724A1 (en) * | 2012-10-19 | 2014-04-24 | 日産自動車株式会社 | Semiconductor device and method for manufacturing same |
| EP2911205A4 (en) * | 2012-10-19 | 2016-03-02 | Nissan Motor | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME |
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| KR101502306B1 (en) * | 2013-09-26 | 2015-03-13 | 주식회사 실리콘웍스 | Semiconductor rectification device and method for fabricating the same |
| WO2016002057A1 (en) * | 2014-07-03 | 2016-01-07 | 株式会社日立製作所 | Semiconductor device, power module, power conversion device, three-phase motor system, automobile, and railway vehicle |
| CN105826399A (en) * | 2016-05-25 | 2016-08-03 | 上海安微电子有限公司 | Soft fast recovery diode of multi-mixture structure and preparation method thereof |
| WO2023243537A1 (en) | 2022-06-17 | 2023-12-21 | 新電元工業株式会社 | Semiconductor device |
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| Publication number | Publication date |
|---|---|
| JP3117506B2 (en) | 2000-12-18 |
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