JPH0575140B2 - - Google Patents

Description

Detailed Description of the Invention Technical Field The present invention relates to a multiprocessor system, and particularly to a multiprocessor system that is composed of a plurality of microprocessor systems and a system bus to which these microprocessor systems are commonly connected. This invention relates to a multiprocessor system that transfers data between processor systems by direct memory access.

BACKGROUND ART Conventionally, data transfer between a plurality of microprocessor systems is generally performed via a system bus that can be commonly used by each microprocessor system.

This type of system bus uses IEEE-796 (The
Institute of Electrical and Electroncs
Engineer-796) multibus and IEEE-P1014
VME bus is used.

As shown in FIG. 5, in the multi-bus system, a plurality of master microprocessor systems 40, 50, 60 can exist on the multi-bus 101, and each master microprocessor system 40,
When using the multi-bus 101, 50 and 60 receive arbitration from the bus exchange control circuits 42, 52, and 62 provided in their respective systems via the multi-bus 102 with a bus exchange control signal, and the local bus 4
4, 56, 67 and buffer circuits 43, 53, 63
Address signals, data signals, and control signals are output onto the multi-bus 101 via the multi-bus 101.

As shown in FIG. 4, the architecture of the multi-bus 101 is such that address signals, data signals, and control signals have timings as shown in the figure, and each signal is transmitted to the master microprocessor system 40, 5.
CPU (central processing unit) within 0,60 41,51,
61 and performs data transfer with other master microprocessor systems 40, 50, 60 and slave system 70.

In FIG. 5, a master microprocessor system 50 includes an input/output device (I/O) 54 and a memory circuit 55, and a master microprocessor system 60 includes an input/output device 64, a memory circuit 65, and a bidirectional control circuit. 66, the slave system 70 is provided with a memory circuit 71 and a buffer circuit 72, respectively.

In such a conventional multiprocessor system, microprocessor systems 40, 50, 6
The speed of data transfer between CPUs 41, 51,
61 clock signal frequency, data transfer instruction execution speed, and whether the CPU is 8-bit or 16-bit.
It depends largely on the CPU, but
Data transfer can be performed at high speed using direct memory access (hereinafter referred to as DMA) technology, which allows large amounts of data to be transferred at high speed without CPU intervention.

However, in a multiprocessor system, microprocessor systems 40, 50, 6
0 to other microprocessor systems 40, 50, 60 via multibuses 101, 102.
When transferring data using DMA, the DMA
is started, the multibuses 101 and 102
While data transfer by DMA is being performed, even if there is a request to use the multibus 101, 102 from another microprocessor system 40, 50, 60, the multibus 1 is not used until the data transfer is completed.
There is a drawback that 01 and 102 are exclusively used for data transfer.

Purpose of the Invention The present invention was made in order to eliminate the above-mentioned drawbacks of the conventional system.It is an object of the present invention to achieve high-speed and efficient data transfer without being exclusively used for a specific data transfer even if the system bus is required to be used repeatedly. The purpose of this invention is to provide a multiprocessor system that can perform the following functions.

Structure of the Invention A multiprocessor system according to the present invention is constituted by a plurality of microprocessor systems and a system bus to which the microprocessor systems are commonly connected, and the microprocessor systems are connected to each other by direct memory access. A multiprocessor system that performs data transfer, comprising: a control unit that outputs a first address strobe signal and a second address strobe signal to perform data transfer for each microprocessor system; and from the control unit. frequency dividing means for dividing the frequency of the first and second address strobe signals by 1/2, and responding to an output signal of the frequency dividing means when the output signal is input as a bus use request to the system bus. bus exchange control means for arbitrating the right to use the system bus, the control section reading data from the storage circuit to the control section by outputting the first address strobe signal; By outputting the second address strobe signal, data is transferred from the control section to another microprocessor system by the direct memory access using the system bus, and with this configuration, the microprocessor system and the It is characterized by intermittent connection time with the system bus.

Embodiment Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. In the figure, one microprocessor system that makes up the multiprocessor system is
A CPU 1, a control signal generation circuit 2, a data controller 3 that controls data transfer by DMA,
An address latch circuit 4 that separates addresses and data that are multiplexed and output on the address/data signal bus 13, and data transceiver circuits 5 and 1.
1, an address decoder circuit 6 that decodes the address and sends it to the storage circuit 7, and a storage circuit 7.
A control signal logic circuit 8 that generates signals to control each circuit, a control signal bus 14, and a multibus 10
1, a control signal buffer circuit 9 that interfaces with the address signal bus 15, and a multibus 101.
and a bus exchange control circuit 12 that arbitrates the right to use the multi-bus 101.

Here, the data transceiver circuit 11 interfaces the address/data signal bus 13 and the multi-bus 101. Further, address/data signal bus 13, control signal bus 14, and address signal bus 15 are local buses of this microprocessor system.

FIG. 2 is a timing chart showing the operation of one embodiment of the present invention, and FIG. 3 is a configuration diagram of a frequency dividing circuit of the control signal logic circuit 8 of FIG. 1. The operation of one embodiment of the present invention will be explained using these figures and FIG. 1. In one embodiment of the present invention, a multiprocessor system is constructed by adding the same contents as the microprocessor system shown in FIG. 1 to the configuration of each master microprocessor system 40, 50, and 60 shown in FIG. It shall be.

When the CPU 1 issues a data transfer request to another master microprocessor system or slave system, it sends a DMA activation command to the DMA controller 3. The DMA controller 3 outputs a bus hold request signal 18 indicating a request to use the local buses (address/data signal bus 13, control signal bus 14, and address signal bus 15) to the CPU 1. When CPU 1 accepts this request to use the local bus, it transmits bus hold permission signal 19 to DMA.
It outputs to the controller 3 and control signal logic circuit 8. After this handshake sequence, the right to use the local bus is transferred to the DMA controller 3.

The DMA controller 3 outputs an address strobe signal 21 to the control signal logic circuit 8, and this address strobe signal 21 is input to a frequency divider circuit 30 (see FIG. 3) of the control signal logic circuit 8. The frequency dividing circuit 30 receives the address initial setting signal 27,
28 and address strobe signal 21 to 1/
Bus exchange control circuit 12 as a bus use request signal 25 which requests the use of multi-bus 101 by dividing the frequency by two.
At the same time, it is logically ANDed with the bus use permission signal 26 that permits the use of the multi-bus 101 from the bus exchange control circuit 12, and is output as a buffer permission signal 24 to the control signal buffer circuit 9, address signal buffer circuit 10, and data transceiver. circuit 1
1 and is output. Control signal buffer circuit 9, address signal buffer circuit 10, and data transceiver circuit 11 are controlled by this buffer enable signal 24.

The first address strobe signal 2 after the DMA controller 3 obtains the right to use the local bus.
1 pulse is input to the control signal logic circuit 8, the control signal logic circuit 8 outputs a bus enable/disable signal 22 to the control signal generation circuit 2, address latch circuit 4, and data transceiver circuit 5.
Address latch circuit 4 latches addresses from address/data signal bus 13, i.e.
The first pulse of the address strobe signal 21 from the DMA controller 3 is output as a timing pulse for latching the address to the memory circuit 7.

The control signal generation circuit 2 outputs a read control signal to the storage circuit 7 via the control signal bus 14, data is read from the storage circuit 7, and the data signal is transferred to the data signal bus 16.
DMA via data transceiver circuit 5
The data is sent to the controller 3 and temporarily held in the DMA controller 3.

The second pulse of the address strobe signal 21 is frequency-divided by 1/2 by the frequency dividing circuit 30 and outputted to the bus exchange control circuit 12 as a bus use request signal 25. This second pulse also serves as a timing pulse for latching the addresses of the memory circuits of other master microprocessor systems and slave systems.

In response to the bus enable/disable signal 22 from the control signal logic circuit 8 due to this second pulse, the control signal generating circuit 2 outputs a write control signal to other processors to be transferred via the control signal bus 14. The write signal is sent to the multi-bus 101 via the control signal buffer circuit 9. Further, the address to be transferred to another processor latched by the second pulse is also sent to the multi-bus 101 via the address signal buffer circuit 10.

However, output permission for the control signal buffer circuit 9, address signal buffer circuit 10, and data transceiver circuit 11 is granted by outputting the bus use request signal 25 to the bus exchange control circuit 12 and receiving arbitration for the right to use the multibus 101. A bus use permission signal 26 is output from the exchange control circuit 12, and this signal is further logically controlled by the control signal logic circuit 8, and after the buffer permission signal 24 becomes active, the output permission state is established.

The data held in the DMA controller 3 is written to the memory circuits of other master microprocessor systems and slave systems targeted for DMA, but this write operation is performed by the multibus 10.
1, data is transferred until a response signal is returned.

The third pulse of the address strobe signal 21 performs the same operation as the first pulse, but since the multibus 101 is not being used by this microprocessor system, it is not used by other master microprocessor systems. will be used. When the fourth pulse of address strobe signal 21 is output, this microprocessor system uses multibus 101 again to transfer data.

The bus usage state in FIG. 2 shows the usage state of the multi-bus 101 when one embodiment of the present invention is applied to the multiprocessor system shown in FIG. That is, data transfer between the other master microprocessor systems 50 and 60 is performed via the control signal bus 14 when the read control signal is output.

In this way, the data for data transfer is temporarily held in the DMA controller 3 (control unit), and when this data is held, the data is transferred to the other master microprocessor systems 50 and 60, and this master microprocessor system During data transfer in the system 40, by having the DMA controller 3 send out the data held, the system bus is not monopolized for a specific data transfer even if the system bus is requested to use the system bus at high speed. can perform efficient data transfer.

Effects of the Invention As explained above, according to the present invention, data read out from the storage circuit is temporarily held in the control unit, the temporarily held data is sent to the control unit during data transfer, and data read out from the storage circuit is sent to the control unit. By having another microprocessor system perform the data transfer when the data is temporarily held, this system bus can be dedicated to a specific data transfer even if there is a request to use the system bus overlappingly. This has the effect of enabling high-speed and efficient data transfer without any unnecessary processing.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention;
FIG. 2 is a timing chart showing the operation of an embodiment of the present invention, FIG. 3 is a configuration diagram showing a frequency dividing circuit of the control signal logic circuit of FIG. 1, and FIG. 4 is a timing chart showing the multi-bus architecture. Chart,
FIG. 5 is a block diagram showing a conventional example. Explanation of symbols of main parts, 3...DMA (direct memory access) controller, 8... Control signal logic circuit, 12... Bus exchange control circuit,
21... Address strobe signal, 24... Buffer permission signal, 25... Bus use request signal, 26
... Bus use permission signal, 30 ... Frequency division circuit, 10
1...Multibus.

Claims (1)

[Scope of Claims] 1. A multiprocessor system comprising a plurality of microprocessor systems and a system bus to which the microprocessor systems are commonly connected, and which transfers data between the microprocessors by direct memory access. The processor system includes a control section 3 that outputs a first address strobe signal and a second address strobe signal to transfer data for each microprocessor system, and a control section 3 that outputs a first address strobe signal and a second address strobe signal to transfer data; and frequency dividing means for dividing the frequency of the second address strobe signal by 1/2; and when the output signal of the frequency dividing means is input as a bus use request to the system bus, the system bus is divided in response to the output signal. bus exchange control means for arbitrating the right to use the first address strobe signal, the control section 3 performs an operation of reading data from the storage circuit to the control section 3 by outputting the first address strobe signal; 2
By outputting an address strobe signal of the system bus, data is transferred from the control unit 3 to another microprocessor system by the direct memory access, and with this configuration, the microprocessor system and the system bus A multiprocessor system characterized by intermittent connection time.