JPH0575172B2 - - Google Patents
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- Publication number
- JPH0575172B2 JPH0575172B2 JP62171496A JP17149687A JPH0575172B2 JP H0575172 B2 JPH0575172 B2 JP H0575172B2 JP 62171496 A JP62171496 A JP 62171496A JP 17149687 A JP17149687 A JP 17149687A JP H0575172 B2 JPH0575172 B2 JP H0575172B2
- Authority
- JP
- Japan
- Prior art keywords
- region
- emitter
- base
- mesh
- emitter region
- Prior art date
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Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明はメツシユエミツタ型トランジスタに関
する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a mesh emitter type transistor.
従来メツシユエミツタ型トランジスタの基本構
造は第４図ａ，ｂのようになつていた。
The basic structure of conventional mesh emitter type transistors was as shown in FIGS. 4a and 4b.
コレクタ領域であるｎ型半導体基板１内に、ｐ
型拡散層からなるベース領域２が形成され、ベー
ス領域２内にメツシエ状のｎ型不純物領域からな
るエミツタ領域が形成されていた。また、この基
本構造に、P+型拡散層を、ベース領域２内の表
面部全面に形成したダブルベース構造と、ベース
コンタクト５の部分に選択的に形成したコンタク
トベース構造とがあつた。 In the n-type semiconductor substrate 1 which is the collector region, p
A base region 2 made of a type diffusion layer was formed, and an emitter region made of a Messier-shaped n-type impurity region was formed within the base region 2. Furthermore, this basic structure includes a double base structure in which a P + type diffusion layer is formed on the entire surface of the base region 2, and a contact base structure in which the P + type diffusion layer is selectively formed in the base contact 5 portion.
上述した従来の半導体装置の共通の問題点とし
て、メツシユ状のエミツタ領域中央部直下のベー
ス領域に注入されたキヤリアが第５図ａ，ｂに示
したベース横方向抵抗分R1によつて引き出され
難くなり、スイツチング特性の低下の原因となつ
ていた。
A common problem with the conventional semiconductor devices described above is that the carriers injected into the base region directly under the center of the mesh-shaped emitter region are drawn out by the base lateral resistance R 1 shown in FIGS. 5a and 5b. This made it difficult for switching to occur, causing a decline in switching characteristics.
また、第５図ａ，ｃに示した、ベース横方向抵
抗分R2とベース横方向抵抗分R1に差があり、R1
＞R2となるため、エミツタ領域直下のベース領
域中に注入されたキヤリア分布に偏りができ、特
に、トランジスタのオフ時には、エミツタコンタ
クト６直下のベース領域中にキヤリアが残り、他
のエミツタ領域がオフ状態となつても、エミツタ
コンタクト６付近はオン状態となり、インダクタ
ンス負荷時に生ずる、強いコレクタベース間逆バ
イアスにより、電流集中が起り易く、最悪の場合
二次降状により破壊に至り逆方向安全動作領域が
狭いという欠点がある。また、前述のダブルベー
ス構造では、全体のベース横方向抵抗分を減少で
きるが、キヤリア分布の偏りは改善されず、hFE
が低いという欠点がある。 In addition, there is a difference between the base lateral resistance R 2 and the base lateral resistance R 1 shown in Figure 5 a and c, and R 1
> R 2 , the distribution of carriers injected into the base region directly under the emitter region becomes biased. Especially when the transistor is off, carriers remain in the base region directly under the emitter contact 6, and the carriers injected into the base region directly under the emitter region become biased. Even if it is in the off state, the area around the emitter contact 6 is in the on state, and the strong reverse bias between collector and base that occurs when inductance is loaded tends to cause current concentration. The disadvantage is that the safe operating area is narrow. In addition, although the double base structure described above can reduce the overall base lateral resistance, it does not improve the carrier distribution bias, and h FE
It has the disadvantage of being low.
更に、前述のコンタクトベース構造では、ベー
スコンタクト付近の抵抗分を減少できるが、エミ
ツタ直下のベース横方向抵抗は改善されない。 Furthermore, in the contact base structure described above, although the resistance near the base contact can be reduced, the lateral resistance of the base directly under the emitter is not improved.
本発明のメツシユエミツタ型トランジスタは、
第１導電型半導体基板の主表面から所定の深さに
わたつて選択的に形成された第２導電型不純物領
域からなる第１ベース領域と、前記第１ベース領
域の表面部に形成されたメツシユ状の第１導電型
不純物領域からなるエミツタ領域と、前記エミツ
タ領域と所定の角度をもつて交差し前記エミツタ
領域の節および目にそれぞれ対応する位置に節を
有するメツシユ状の高濃度第２導電型不純物領域
であつて前記交差部で前記エミツタ領域の底部と
PN接合をなしその余の部分で前記半導体基板の
主表面から前記エミツタ領域の底面より深い処に
かけて設けられた第２ベース領域と、前記エミツ
タ領域の節部に接触するエミツタ電極と、前記エ
ミツタ領域の目に対応する前記第２ベース領域の
節部に接触するベース電極とを含むというもので
ある。
The mesh emitter type transistor of the present invention is
A first base region made of a second conductivity type impurity region selectively formed to a predetermined depth from the main surface of the first conductivity type semiconductor substrate, and a mesh formed on the surface of the first base region. an emitter region consisting of a first conductivity type impurity region having a shape, and a mesh-like high concentration second conductor which intersects the emitter region at a predetermined angle and has nodes at positions corresponding to nodes and eyes of the emitter region, respectively. type impurity region, which intersects with the bottom of the emitter region at the intersection.
a second base region that forms a PN junction and is provided in the remaining portion from the main surface of the semiconductor substrate to a place deeper than the bottom surface of the emitter region; an emitter electrode that contacts a node of the emitter region; and an emitter electrode that contacts a node of the emitter region; and a base electrode that contacts a node of the second base region corresponding to the eye of the eye.
次に、本発明の実施例について図面を参照して
説明する。
Next, embodiments of the present invention will be described with reference to the drawings.
第１図ａは本発明の第１の実施例の主要部を示
す半導体チツプの平面図、第１図ｂ及びｃはそれ
ぞれ第１図ａのＡ−A′線断面図及びＢ−B′線断
面図、第２図は第１の実施例の不純物プロフアイ
ル図である。 FIG. 1a is a plan view of a semiconductor chip showing the main parts of the first embodiment of the present invention, and FIGS. 1b and 1c are sectional views taken along line A-A' and line B-B' in FIG. 1a, respectively. The cross-sectional view, FIG. 2, is an impurity profile diagram of the first embodiment.
この実施例は、ｎ型半導体基板の主表面から所
定の深さにわたつて選択的に形成されたｐ型不純
物領域からなる第１ベース領域２′と、第１ベー
ス領域２′の表面部に形成されたメツシユ状のｎ
型不純物領域からなるエミツタ領域４と、エミツ
タ領域４と45°の角度をもつて交差しエミツタ領
域４の節および目にそれぞれ対応する位置に節を
有するメツシユ状の高濃度ｐ型不純物領域であつ
て前述の交差部でエミツタ領域４の底部とPN接
合をなしその余の部分で前述の半導体基板の主表
面からエミツタ領域４の底部より深い処にかけて
設けられた第２ベース領域３と、エミツタ領域４
の節部に接触するエミツタ電極８−１，８−２，
……，と、エミツタ領域４の目に対応する第２ベ
ース領域３の節部に接触するベース電極７−１，
７−２，……，とを含んでいる。 This embodiment includes a first base region 2' consisting of a p-type impurity region selectively formed to a predetermined depth from the main surface of an n-type semiconductor substrate, and a surface portion of the first base region 2'. The mesh-like n formed
The emitter region 4 is a mesh-like high concentration p-type impurity region which intersects the emitter region 4 at an angle of 45° and has nodes at positions corresponding to the nodes and eyes of the emitter region 4, respectively. The second base region 3 forms a PN junction with the bottom of the emitter region 4 at the above-mentioned intersection, and the second base region 3 provided from the main surface of the semiconductor substrate to a depth deeper than the bottom of the emitter region 4 in the remaining part. 4
Emitter electrodes 8-1, 8-2, which contact the nodes of
. . . , and the base electrode 7-1 that contacts the node of the second base region 3 corresponding to the eye of the emitter region 4,
7-2, ..., and are included.
すなわちコレクタ領域であるｎ型半導体基板１
内に、エミツタ領域４を包含する形で、第１ベー
ス領域２′が形成され、エミツタ領域４は第１ベ
ース領域２′内にメツシユ状に形成されている。
更に、第２ベース領域３は、エミツタ領域４のメ
ツシユ方向と45°の方向で交差し、エミツタコン
タクト６の位置で節の一部がエミツタ領域の節と
重なり、且つ、第１ベース領域２′よりも不純物
濃度が高く、エミツタ領域４よりも深く形成され
ている。 In other words, the n-type semiconductor substrate 1 which is the collector region
A first base region 2' is formed therein to include the emitter region 4, and the emitter region 4 is formed in a mesh shape within the first base region 2'.
Further, the second base region 3 intersects the mesh direction of the emitter region 4 at 45°, and a portion of the node overlaps with a node of the emitter region at the position of the emitter contact 6, and the first base region 2 ', and is formed deeper than the emitter region 4.
エミツタ領域の節部直下に高濃度の第２ベース
領域３がくるので横方向抵抗分R1が減少し、他
のエミツタ領域近辺のベース横方向抵抗分R2と
均衡を取ることができる。 Since the highly concentrated second base region 3 is placed directly under the node of the emitter region, the lateral resistance R 1 is reduced and balanced with the base lateral resistance R 2 near the other emitter regions.
従つて、トランジスタのオン、オフ時のキヤリ
ア分布の偏りが少なくなり、スイツチング特性と
インダクタンス負荷時の逆方向安全動作領域が改
善できる。 Therefore, the bias in the carrier distribution when the transistor is turned on and off is reduced, and the switching characteristics and the safe operation region in the reverse direction when loaded with inductance can be improved.
第３図ａは本発明の第２の実施例の主要部を示
す半導体チツプの平面図、第３図ｂは第３図ａの
Ｘ−X′線断面図である。 FIG. 3a is a plan view of a semiconductor chip showing main parts of a second embodiment of the present invention, and FIG. 3b is a sectional view taken along the line X--X' of FIG. 3a.
この実施例は、第２ベース領域３の形状がエミ
ツタボンデイングパツド直下部で異なつている
が、その外は第１の実施例と同じである。エミツ
タボンデイングパツド９直下の第１ベース領域
２′内にエミツタコンタクト６′と重ならない状態
でメツシユ状の第２ベース領域３が形成されてい
る。つまり、第２ベース領域３の目の位置にエミ
ツタコンタクト６′がくる。 This embodiment is the same as the first embodiment except that the shape of the second base region 3 is different directly below the emitter bonding pad. A mesh-shaped second base region 3 is formed in the first base region 2' directly below the emitter bonding pad 9 without overlapping the emitter contact 6'. In other words, the emitter contact 6' is located at the position of the second base region 3.
スイツチング動作のオン状態からオフ状態への
遷移時にエミツタボンデイングパツド９直下のベ
ース領域に蓄積されたキヤリアを、エミツタコン
タクト６′から離れた部分のエミツタ領域直下
（そこに高濃度の第２ベース領域がある）を通し
て引き出すようにして、エミツタ電流の集中を緩
和し、インダクタンス負荷時の逆方向安全動作領
域が一層広くできる利点がある。 During the transition from the on state to the off state of the switching operation, the carriers accumulated in the base region directly under the emitter bonding pad 9 are removed from the emitter region directly under the emitter region away from the emitter contact 6' (therein a high concentration second There is an advantage in that the concentration of emitter current can be alleviated and the safe operation area in the reverse direction can be further widened when an inductance load is applied.
以上説明したように本発明は、メツシユ状エミ
ツタ領域の節の部分直下に節を有するメツシユ状
の高濃度の第２ベース領域を設けることにより、
hFEを落すことなくエミツタ中央部のキヤリア分
布の偏りを少なくできるので、メツシユエミツタ
型トランジスタのスイツチング特性及びインダク
タンス負荷時の逆方向安全動作領域を改善できる
効果がある。
As explained above, the present invention provides a mesh-like high-concentration second base region having knots directly below the knots of the mesh-like emitter region.
Since it is possible to reduce the bias in the carrier distribution at the center of the emitter without lowering the FE , it has the effect of improving the switching characteristics of the mesh emitter transistor and the safe reverse operation area under inductance load.
第１図ａは本発明の第１の実施例の主要部を示
す半導体チツプの平面図、第１図ｂ及びｃはそれ
ぞれ第１図ａのＡ−A′線断面図及びＢ−B′線断
面図、第２図は第１の実施例の不純物プロフアイ
ル図、第３図ａは第２の実施例の主要部を示す半
導体チツプの平面図、第３図ｂは第３図ａのＸ−
X′線断面図、第４図ａは従来例の基本構造を示
す半導体チツプの平面図、第４図ｂは第４図ａの
Ｘ−X′線断面図、第５図ａは従来例の動作を説
明するための平面模式図、第５図ｂ及びｃはそれ
ぞれ第５図ａのＡ−A′線断面図及びＢ−B′断面
図である。
１……ｎ型半導体基板、２……ベース領域、
２′……第１ベース領域、３……第２ベース領域、
４……エミツタ領域、５……ベースコンタクト、
６，６′……エミツタコンタクト、７，７−１〜
７−４……ベース電極、８，８−１〜８−３……
エミツタ電極、９……エミツタボンデイングパツ
ド。
FIG. 1a is a plan view of a semiconductor chip showing the main parts of the first embodiment of the present invention, and FIGS. 1b and 1c are sectional views taken along line A-A' and line B-B' in FIG. 1a, respectively. 2 is an impurity profile diagram of the first embodiment, FIG. 3a is a plan view of a semiconductor chip showing the main parts of the second embodiment, and FIG. 3b is a cross-sectional view of −
4a is a plan view of a semiconductor chip showing the basic structure of the conventional example, FIG. 4b is a sectional view taken along line X-X' of FIG. 4a, and FIG. FIGS. 5b and 5c, which are schematic plan views for explaining the operation, are a cross-sectional view taken along line A-A' and line B-B' in FIG. 5a, respectively. 1... n-type semiconductor substrate, 2... base region,
2′...first base region, 3...second base region,
4... Emitter area, 5... Base contact,
6,6'...Emitsuta contact, 7,7-1~
7-4... Base electrode, 8, 8-1 to 8-3...
Emitter electrode, 9... Emitter bonding pad.
Claims (1)
さにわたつて選択的に形成された第２導電型不純
物領域からなる第１ベース領域と、前記第１ベー
ス領域の表面部に形成されたメツシユ状の第１導
電型不純物領域からなるエミツタ領域と、前記エ
ミツタ領域と所定の角度をもつて交差し前記エミ
ツタ領域の節および目にそれぞれ対応する位置に
節を有するメツシユ状の高濃度第２導電型不純物
領域であつて前記交差部で前記エミツタ領域の底
部とPN接合をなしその余の部分で前記半導体基
板の主表面から前記エミツタ領域の底面より深い
処にかけて設けられた第２ベース領域と、前記エ
ミツタ領域の節部に接触するエミツタ電極と、前
記エミツタ領域の目に対応する前記第２ベース領
域の節部に接触するベース電極とを含むことを特
徴とするメツシユエミツタ型トランジスタ。 ２ 第２ベース領域は、エミツタボンデイングパ
ツド直下においては、エミツタ領域の節直下にく
る目をもつメツシユ構造を有している特許請求の
範囲第１項記載のメツシユエミツタ型トランジス
タ。[Scope of Claims] 1. A first base region consisting of a second conductivity type impurity region selectively formed to a predetermined depth from the main surface of the first conductivity type semiconductor substrate; an emitter region made of a mesh-shaped impurity region of a first conductivity type formed on a surface portion; and a mesh that intersects the emitter region at a predetermined angle and has nodes at positions corresponding to nodes and eyes of the emitter region, respectively. a highly concentrated impurity region of the second conductivity type, which forms a PN junction with the bottom of the emitter region at the intersection, and extends from the main surface of the semiconductor substrate to a depth deeper than the bottom of the emitter region in the remaining region; A mesh emitter comprising: a second base region, an emitter electrode that contacts a node of the emitter region, and a base electrode that contacts a node of the second base region corresponding to the eye of the emitter region. type transistor. 2. The mesh emitter type transistor according to claim 1, wherein the second base region has a mesh structure with an opening directly below the node of the emitter region directly below the emitter bonding pad.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62171496A JPS6414961A (en) | 1987-07-08 | 1987-07-08 | Mesh-emitter type transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62171496A JPS6414961A (en) | 1987-07-08 | 1987-07-08 | Mesh-emitter type transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6414961A JPS6414961A (en) | 1989-01-19 |
| JPH0575172B2 true JPH0575172B2 (en) | 1993-10-20 |
Family
ID=15924177
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62171496A Granted JPS6414961A (en) | 1987-07-08 | 1987-07-08 | Mesh-emitter type transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6414961A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7439608B2 (en) * | 2006-09-22 | 2008-10-21 | Intel Corporation | Symmetric bipolar junction transistor design for deep sub-micron fabrication processes |
| JP2014232883A (en) * | 2014-07-28 | 2014-12-11 | ローム株式会社 | Bipolar semiconductor device |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5026480A (en) * | 1973-07-09 | 1975-03-19 | ||
| JPS5222885A (en) * | 1975-08-14 | 1977-02-21 | Matsushita Electronics Corp | Transistor and manufacturing system |
| JPS62142356A (en) * | 1985-12-17 | 1987-06-25 | Sanken Electric Co Ltd | transistor |
-
1987
- 1987-07-08 JP JP62171496A patent/JPS6414961A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6414961A (en) | 1989-01-19 |
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