JPH057642Y2 - - Google Patents

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to an input port circuit for a setting switch, and is applied to a microprocessor (hereinafter referred to as "CPU").
The present invention relates to an input port circuit for a setting switch that initializes the operating functions of a CPU in a device using a computer, such as a control device such as a printer.

[Prior Art] A computer and peripheral devices such as a printer connected to the computer have a built-in CPU that controls these devices. These CPUs execute device control sequences according to control programs written in advance in nonvolatile memory such as EP-ROM, but depending on the usage environment, it may be better to change part of this control program. Sometimes it's good.

For example, taking a thermal printer as an example, thermal printers have two printing principles: one uses a thermal transfer ribbon to print on plain paper, and the other prints directly on thermal paper. Generally, both printing methods can be used. It's structured.

However, when using a thermal transfer ribbon, it is possible to print only in the direction in which the ribbon is driven (unidirectional printing), but when using thermal paper, there are no restrictions on the printing direction, so printing can be performed in both directions ( (reciprocating printing) is possible.

However, if the above control program is set to unidirectional printing using a thermal transfer ribbon,
For users who exclusively use thermal paper, a printer capable of reciprocating printing is desired in order to increase printing efficiency. Therefore, two programs, a program for unidirectional printing and a program for reciprocating printing, are stored in the control program as subroutines in advance, and these operations can be selected and set using a depth switch, etc. for initial operating condition setting/peripheral environment setting. There is.

The CPU reads the setting state of this depth switch when the printer is started up, and performs an operation according to the setting state, thereby performing the printing operation desired by the user.

However, in recent years, with advances in office automation, various application programs have been provided, and the environmental conditions and characteristics of connected equipment required by these programs have also diversified. Along with this, devices such as printers are equipped with functions that allow users to change many settings in order to respond to various user requests. The number of setting switches such as a deep switch for selecting and setting is also increasing.

[Problems to be solved by the invention] However, in the past, one input port was assigned to each setting switch, and the number of input ports of the CPU corresponding to these switches is increasing.

Further, it is necessary to arrange setting switches on the board and to arrange these setting switches at a position where they can be operated from outside the case of the printer or the like. Due to the design convenience of arranging the device in a position where it can be operated from outside the case, providing a number of port circuits corresponding to the number of dip switches becomes an obstacle to the degree of freedom in circuit design.

[Means for Solving the Problems] The present invention has been made with the aim of solving the above problems. For example, it provides a port circuit for setting switches that can support two sets of setting switches with one port. The purpose is to

As a means for solving the above-mentioned problems and achieving the above-mentioned objectives, this embodiment includes the following configuration.

That is, the input port circuit for setting switches for the operating state of the CPU includes a first setting switch group and a second setting switch group, one terminal of which is connected to each port of the CPU, and a first setting switch group whose collector terminal is connected to a first setting switch group. is connected to the common line that connects the other terminals of each of the setting switch groups, and the base terminal is
Connected to the switch group switching control port of the CPU,
A PNP transistor whose emitter terminal is connected to a predetermined voltage source, whose emitter terminal is connected to a common line that connects the other terminal of each of the second setting switch group, and whose base terminal is connected to the switch group switching control port of the CPU. and an NPN transistor whose collector terminal is connected to a predetermined voltage source.

[Function] In the above configuration, when the switch group switching control port of the CPU is at a high level, the setting state of the second setting switch group connected to the NPN transistor can be read, and the switch group switching control port of the CPU When the level is low, the setting state of the first setting switch group connected to the PNP transistor can be input.

[Embodiment] Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

The figure is a circuit diagram showing the configuration of a dip switch port circuit according to an embodiment of the present invention.

In microcomputer application equipment, the microprocessor (CPU) controls the entire equipment according to the built-in program.
Input ports a to n for inputting function settings, an output port SET for setting port impedance, and an output port CON for controlling switch selection are provided.

Each input port a to n has one terminal each of high impedance deep switch (second setting switch group) 1a to 1n and low impedance deep switch (first setting switch group) 2a to n. are connected one by one. Each of the ports a to n is connected via a resistor R to the collector of the impedance setting transistor Tr3.

High impedance deep switch 1a~1
The other terminal of the low impedance switches 2a to 2n is connected to the emitter terminal of the PNP transistor Tr1, and the other terminal of the low impedance switches 2a to 2n is connected to the emitter terminal of the PNP transistor Tr1.
2 collector.

The bases of Tr1 and Tr2 are connected to the CPU's output port CON for switch selection control.
Further, the collector terminal of Tr1 and the emitter terminal of Tr2 are grounded.

On the other hand, the collector terminal of the NPN transistor Tr3 is connected to the power supply Vcc via a predetermined resistor, and the base terminal is connected to the output port SET of the CPU. Further, the emitter terminal is grounded. This causes the output port SET to be “L” (low level).
When this happens, the transistor Tr3 is in the off state, the Vcc level is applied to the resistor R, and when the connection switch of input ports a to n is closed, the input port is "L", and when it is open, the input port is "L". It becomes "H" (high level) and the switch setting state can be determined.

On the other hand, the output port SET is “H” (high level)
In this case, the transistor TR3 is activated, the ground level is applied to the resistor R, and the "L" level is supplied to each input port regardless of the setting state of the switch. Therefore, in such a case, the setting state of the switch can be ignored, and there is no possibility that the input port state will be read inadvertently during operation and the program execution procedure will be disrupted.

The initial setting operation by the setting switch input port circuit of this embodiment having the above configuration will be explained below.

When the power is turned on, the CPU performs a self-check according to the initial setting sequence of the control program that is built in or pre-written in a non-volatile memory such as an EP-ROM (not shown), and then the input port a is
A sequence is entered to read the status of each setting dip switch connected to n.

First, set the output port SET for setting the port impedance of the CPU to “L” level, and
is turned "OFF" and the other terminal of the resistor R connected to each input port a to n is held at the Vcc level, making it possible to read the setting state of each setting deep switch.

Then, output port CON is set to "L". At this time, if none of the switches 1a to 1n are turned on, the emitter terminal of the PNP transistor TR1 is in a high impedance state.
The PNP transistor TR1 is not "ON", all of the input ports a to n are in a high impedance state, and each of the switches 1a to 1n can be recognized as being in an "OFF" state. On the other hand, when any one of the switches 1a to 1n is "ON", the Vcc level is applied to the emitter terminal of the PNP transistor TR1, turning Tr1 into the "ON" state. At this time, the NPN transistor Tr2 is in the "OFF" state, and only the voltage at the collector terminal of the PNP transistor Tr1 becomes the ground level. Therefore, the CPU can read which switch among the dip switches 1a to 1n connected to the transistor TR1 is closed.

Next, the CPU sets the output port CON to "H" and turns the NPN transistor Tr2 into the "ON" state when any one of the dip switches 2a to 2b is "ON". At this time PNP
Transistor Tr1 is in “OFF” state and NPN
Only the voltage at the emitter terminal of transistor Tr2 becomes the ground level. Therefore, the transistor
Deep switch 2a to 2n connected to TR2
The CPU determines which of the switches are closed.
can be loaded.

When the input is completed, the CPU sets the port impedance setting output terminal SET to "H", turns TR3 "ON", holds the other terminal of the resistor R connected to each input port a to n at the ground level, and changes each setting. The settings of the deep switch cannot be read. The CPU then enters the next control stage, and unless the power is turned off and on again, the CPU settings will not change even if the status of these terminals changes.

In addition, Tr3 follows the output of the CPU's SET pin.
Anything that turns ON/OFF is fine, even an NPN type.
It may be a PNP type or another FET type.

As explained above, according to this embodiment, the number of ports set for the deep switch can be reduced to approximately 1/2.
Although the above description has been made regarding the device initialization input port, the present invention is not limited to initialization, and can be applied to the status input section of any switch. For example, it can be applied to all kinds of switch setting ports, such as changing the selection of subroutines during general operation, changing the output printer, etc. during operation.

Note that if it is clear that the above-mentioned setting switch is to be read only when the power is "ON", the output port SET and the transistor TR3 can be omitted, and the resistor R connected to each input port a to n can be omitted. The other terminal may be directly held at the Vcc level.

[Effects of the invention] As explained above, according to the invention, the number of status setting read ports can be reduced to approximately half of the number of setting switches, so the degree of freedom in circuit design of control boards etc. can be increased.

[Brief explanation of the drawing]

The figure is a setting switch port circuit diagram of an embodiment of the present invention. In the figure, 1a to 1n...high impedance deep switch, 2a to 2n...low impedance deep switch, Tr1...PNP transistor, Tr2...NPN transistor, Tr3...impedance setting transistor, CPU...micropro Setsa, a~n...Input port, SET
...Output port for port impedance setting,
CON: Output port for switch selection control.

Claims (1)

[Claims for Utility Model Registration] An input port circuit for setting switches for the operating state of a CPU, comprising a first setting switch group and a second setting switch group, one terminal of which is connected to each port of the CPU. , the collector terminal is connected to a common line connecting the other terminals of each of the first setting switch group, the base terminal is connected to the switch group switching control port of the CPU, and the emitter terminal is connected to a predetermined voltage source. The PNP transistor has an emitter terminal connected to a common line connecting the other terminals of each of the second setting switch group, a base terminal connected to the switch group switching control port of the CPU, and a collector terminal connected to a predetermined setting switch group. an NPN transistor connected to a voltage source, when a switch group switching control port of the CPU is at a high level, the setting state of the second setting switch group connected to the NPN transistor can be read; An input port circuit for a setting switch, characterized in that the setting state of the first setting switch group connected to a PNP transistor can be input when a switch group switching control port of a CPU is at a low level.