JPH0577112B2 - - Google Patents

Description

[Detailed description of the invention]

[Field of Application of the Invention] The present invention relates to a method and apparatus for inspecting a pattern such as a printed circuit pattern, and more particularly to a pattern defect detection method and apparatus suitable for non-contact and high-speed detection of defects related to electrical continuity. [Background of the Invention] Conventionally, as a method for testing electrical continuity of a printed circuit pattern, specific pad positions are memorized in advance, contact pins are brought into contact with them, voltage is applied between the two contact pins, and a voltage is applied between the two contact pins. There were devices that detected continuity/disconnection and separation/short circuit based on the presence or absence of current and its magnitude. In this method, the contact pin is brought into direct contact with the circuit pattern, so inspection reliability is low due to fluctuations in contact resistance.If the contact pin becomes worn or damaged, it must be replaced, and the circuit pattern may be damaged by contact. There were many drawbacks, such as damage to the pattern or, in the worst case, damage to the pattern. In addition, if the circuit pattern is partially thin or if the adjacent circuit pattern is closer than the specified value,
Concentration of current, electric field, etc. can adversely affect circuit operation and long-term circuit reliability, but it is extremely difficult to detect these defects using this method. . Another conventional method for inspecting printed circuit patterns is to detect an optical image of the pattern in a non-contact manner. This method includes methods that directly compare an inspection pattern with a design pattern, methods that directly compare two test patterns, and methods that detect the presence or absence of a pattern in a particularly important specific part of a pattern obtained from design information. There is. In these methods, the defect judgment criterion is whether there is a pattern with the correct size at a predetermined position.In many printed circuit patterns, where only large differences in continuity and pattern dimensions are considered defects, There was a possibility of erroneously identifying defects as defects, which caused a major problem in terms of inspection performance. [Object of the Invention] The object of the present invention is to eliminate the drawbacks of the above-mentioned prior art, and to print at high speed without contact, significantly reducing the amount of data to be compared, and with high reliability without erroneous detection. It is an object of the present invention to provide a method and a table for detecting wiring pattern defects such as potential defects that are likely to cause short circuits due to small wiring pattern intervals and potential defects that are likely to cause disconnections due to small wiring pattern widths. [Summary of the Invention] In order to achieve the above object, the present invention captures an optical image of a wiring pattern to be inspected by an imaging means, converts it into an image signal, and converts the image signal into a binarized image by a binarization means. The binary image signal converted over the entire wiring pattern to be inspected is then enlarged and image processed to identify potential defective areas such as short circuits where the wiring pattern spacing does not meet a predetermined value on the image. An enlarged processed image signal of the wiring pattern to be inspected in which the wiring pattern is short-circuited is formed, and a first image signal between a plurality of points of interest indicating the connection relationship of each wiring pattern is generated for the enlarged processed image signal of the formed wiring pattern to be inspected. Connecting information is created, and the binary image signal converted over the entire wiring pattern to be inspected is subjected to reduction image processing to identify potential defects that are likely to cause disconnection where the width of the wiring pattern does not meet a predetermined value on the image. Forms a reduced processed image signal of the wiring pattern to be inspected with parts cut off,
Create second connection information between a plurality of points of interest indicating the connection relationship of each wiring pattern with respect to the formed reduced image processing signal of the wiring pattern to be inspected, and connect the created first and second connections. Comparing each piece of information with reference connection information between a plurality of points of interest indicating a normal connection relationship between each wiring pattern to detect potential defects that are likely to cause a short circuit or potential defects that are likely to cause a disconnection in the wiring pattern to be inspected. This is a wiring pattern defect detection method characterized by the following. Moreover, the present invention
An imaging device that captures an optical image of the wiring pattern to be inspected and converts it into an image signal, a binarization device that converts the image signal obtained by the imaging device into a binary image signal, and the binarization device The binarized image signal obtained over the entire wiring pattern to be inspected is subjected to enlarged image processing to short-circuit potential defective parts where the wiring pattern spacing does not meet a predetermined value on the image. An enlarged image signal forming means for forming an enlarged image signal of the wiring pattern to be inspected, and connection of each wiring pattern to the enlarged image signal of the interconnection pattern to be inspected formed by the enlarged image signal forming means. a first connection information creation means for creating first connection information between a plurality of points of interest indicating a relationship; and a binarized image signal obtained over the entire wiring pattern to be inspected by the binarization means. A reduced image signal forming means for forming a reduced image signal of a wiring pattern to be inspected in which a potential defective portion that is likely to be cut and whose wiring pattern width does not meet a predetermined value is cut on the image by performing reduced image processing; , a second method for creating second connection information between a plurality of points of interest indicating the connection relationship of each wiring pattern with respect to the reduced processed image signal of the wiring pattern to be inspected formed by the reduced image signal forming means; Connection information creation means;
Comparing each of the first and second connection information created by the first and second connection information creation means with reference connection information between a plurality of points of interest indicating a normal connection relationship of each wiring pattern. This is a wiring pattern defect detection device characterized by comprising a latent defect detection means for detecting a latent defect that is likely to cause a short circuit or a latent defect that is likely to cause a disconnection in a wiring pattern to be inspected. By the way, when a pattern P exists as shown in Fig. 1, the small pattern width and small pattern interval can be reduced by reducing the binary pattern (Fig. 2) and enlarging it (Fig. 3), respectively. Therefore, if disconnections and short circuits are actively detected, it becomes possible to detect and inspect them. In FIG. 1, a indicates a location where the pattern width is small, and b indicates a location where the pattern spacing is small. These points appear as disconnections in FIG. 2, which shows the pattern that has undergone the reduction process, and as short circuits in FIG. 3, which shows the pattern that has undergone the enlargement process. Furthermore, the output data of the connectivity processing for the enlarged pattern and the reduced pattern are calculated by comparing the pad of interest and the pair of pads connected to it (the first and second points between the plurality of points of interest indicating the connection relationship of each wiring pattern). 2 connection information), and the connection relationship data from the design information (standard connection information between multiple points of interest indicating the connection relationship of each normal wiring pattern),
For example, a circular list structure or a matrix list structure is used (hereinafter, in this specification, the former will be referred to as connection data and the latter will be referred to as design data), and pair data will be extracted one by one from the connection data and each pair will be placed on the list of design data. The purpose of this method is to inspect defects by checking whether or not a pad (point of interest) exists. First, connection data will be explained in more detail. FIG. 4 shows connection data. As shown in the figure, the data is a pair of a pad number of interest and a parent pad number in a connected relationship. A pad number is a number assigned to a pad on a circuit pattern that requires testing for continuity, etc., according to specific rules. For example, as shown in FIG. 5, the numbers are sequentially numbered from top to bottom and from left to right, starting from 1. Among the pads, the parent pad is a specific pad representing each connected circuit pattern. The method for determining the parent pad may be determined by setting a specific standard, for example, the one located at the upper leftmost position on the circuit pattern. Table 1 shows connection data using the pattern of FIG. 6 as an example. In the figure, the parent pads are pad numbers 1 and 4, and as shown in Table 1, the storage order (address) of the pad number pairs is arbitrary.

[Table] Next, the design data will be explained in more detail. The design data is a data structure expressed as a circular list consisting of an address, that is, a pad number, and the pad number that appears first when the number representing that number is changed in a circular manner. I have it. Each circular list shows the connection relationship of all pad numbers on one connected circuit pattern.
Here, the connection relationship means only a simple connection relationship between pads, and does not indicate a geometric positional relationship. The pointing order is from the youngest number to the oldest number. Table 2 shows design data using the pattern shown in FIG. 6 as an example.

[Embodiments of the invention]

First, the most basic embodiment of the present invention will be described. FIG. 7 shows the configuration of a device that specifically executes this embodiment. As shown in the figure, first, an optical image of a pattern to be inspected is converted into an electrical signal by the imaging device 21. The image capturing device 21 may be a two-dimensional image capturing device such as a TV camera, or may be an image capturing device using a combination of a linear sensor and a unidirectional drive mechanism. The electric signal is converted into a binarizer 22
It is converted into a binary signal (binary pattern) by . For the binarization method, a fixed threshold method may be used, or in order to obtain a stable pattern, a floating threshold method or a shading correction means may be used. The binary signal is input to the connectivity processing device 23 to create the connection data shown in FIG. In order to know the pad number during connectivity processing, a correspondence relationship between pad positions and pad numbers is created in advance from design information and stored in the pad position data memory 27. The connectivity processing device is more specifically the device described in the applicant's previously filed application entitled "Image Processing Apparatus and Method." The created connection data is stored in the connection data memory 24. On the other hand, design data is created in advance from circuit pattern design information and stored in the design data memory 26. After the connection data of all the circuit patterns are created (after all the circuit patterns are imaged by the imaging device), the processing device 25
The defect detection algorithm described above is executed, attribute data is output to the attribute data memory 28, and defects are determined. An actual defect detection process will be described using the pattern to be inspected shown in FIG. 8 as an example. Table 3 shows the contents of the connection data stored in the connection data memory 24 after the binarization process and the connectivity process. On the other hand, Table 4 shows design data when the normal pattern is the pattern shown in FIG. The left column of Table 4 shows addresses, the center column shows pad numbers (pointers), and the right column shows attribute data. Initialize the attribute data to 0. First, when the data at the beginning of the connection data memory 24 is checked, both the left and right pad numbers are 1, so the attribute data at address 1 of the design data is set to 1. The following connection data and left and right pad numbers

[Table] Since it is 2, the attribute data of address 2 of the design data is set to 1. The next connection data has a left pad number of 3 and a parent pad number of 2. First, when the data (pointer) at address 3 of the design data is checked, it is 1, which does not match the parent pad number 2. Therefore, next, the data at address 1 pointed to by the pointer is examined. Since the data is 2 and matches the parent pad number, the attribute data of address 3 is set to 2. The left pad number of the next connection data is parent pad number 2. When the data at address 4 of the design data is checked, it is 5, and the parent pad number does not match 2. So when we look at the data at address 5, we get 4.
, and not only does it not match the parent pad number 2, but
The data matches pad number 4 on the left side of the connection data, meaning that the parent pad could not be found even after going through the circular list. Therefore, the attribute data of address 4 is set to 3. Regarding the next connection data, the parent pad cannot be found even after going through the circular list, so the attribute data of address 5 is set to 3. The next connection data is the left pad number 6 and the parent pad number 6, so the attribute data of address 6 is set to 1. In the next connection data, the left pad number is 8, the parent pad number is 6, and when the data at address 8 in the design data is checked, it is 6, so the attribute data at address 8 is set to 2. This completes the search for all connection data in this case and creates attribute data. Therefore, this time, attribute data is examined for each circular list and defect determination is performed. First, since the pattern consisting of pad numbers 1, 2, and 3 has two 1's in the attribute data, it is determined that the wire is broken. Next, since the pattern consisting of pad numbers 4 and 5 has all attribute data of 3, it is determined to be a short circuit. Also, the pattern consisting of pad numbers 6, 7, and 8 has 0 in the attribute data, so
There is a defective pad without pad (pad number 7). In this way, the determination results correctly point out defects on the pattern. However, one of the short-circuited patterns does not appear in the determination result. However, this cannot be a significant drawback. In this way, according to this embodiment, short circuits and disconnections in patterns can be detected in a non-contact manner with a relatively simple configuration. Next, a second embodiment of the present invention will be described. FIG. 10 shows the configuration of an apparatus specifically implementing this embodiment. The difference from the embodiment shown earlier (FIG. 7) is that a reduction processing device 29 is included between the binarization device 22 and the connectivity processing device 23.
The other configurations are exactly the same. An embodiment of the reduction processing device 29 is shown in FIG. The device consists of 31 (m ₂ -1) n-bit shift registers and 2 m _1- bit shift registers _32m . These shift registers are driven by the same sampling clock. n is made to match the number of sampling points of the imaging device 21 in the horizontal direction. Also, m ₁ ,
m ₂ is determined by the sampling time interval, the vertical resolution of the imaging device, and the size of the defect to be detected. For example, the sampling time interval and vertical resolution are each equivalent to 10 μm, and the size of the defect is
If it is 30 μm square, m ₁ =m ₂ =3. and,
The output of the m ₁ ×m ₂ shift register 32 is led to an AND circuit 33 and output to the connectivity processing device 23 . Although the outputs of all shift registers are taken out in FIG. 11, they may be taken out selectively depending on the type of defect to be detected. FIG. 13 shows the result of reduction processing of the binary pattern shown in FIG. 12 by the apparatus of FIG. 11. A square whose side is the shortest line segment represents one pixel. FIG. 15 shows the pattern after the reduction process of the pattern to be inspected shown in FIG. 14, Table 5 shows the connection data generated by the connectivity process, and Table 6 shows the design data. Furthermore, the attribute data and defect determination results generated in the same manner as in the first embodiment described above are shown in the right column of Table 6.

[Table] As is clear from this result, a pattern width smaller than the specified value (30 μm in this example) can be detected as a disconnection. However, it is not possible to distinguish between wire breaks and small pattern widths, and there is a possibility that minute short circuits may be overlooked. As described above, according to this embodiment, a pattern defect detection device can be realized with a relatively simple configuration when it is sufficient to detect wire breaks and small pattern widths without distinction. Next, a third embodiment will be explained. FIG. 16 shows the configuration of an apparatus that specifically executes this embodiment. As is clear from the figure, in this example, the first
This is a combination of the above embodiment and the second embodiment. Attribute data and defect determination results detected from the pattern to be inspected shown in FIG. 14 are shown in Table 7 together with the design data.

【table】

[Table] The device shown in Figure 16 is the same as the device shown in Figure 7.
It is a combination of the devices shown in Figure 0, and reference numbers common to those figures represent the same parts as in those figures, and the a appended to the reference number indicates that it belongs to the series that processes the original pattern. where b represents belonging to a series that processes reduced patterns. The processing in each series is exactly the same as in the previous two examples, and finally, processing is added to comprehensively judge the judgment results obtained from the original pattern and the judgment results obtained from the reduced pattern. That is, the seventh
As shown in the table, the two judgment results make it possible to distinguish between wire breaks and small pattern widths, and also eliminate the possibility of overlooking minute short circuits. In this manner, according to the present embodiment, wire breakage and small pattern width can be detected separately. Next, a fourth embodiment of the present invention will be described. FIG. 17 shows the configuration of a device that specifically executes this embodiment. The difference from the first embodiment (FIG. 7) is that an enlargement processing device 30 is included between the binarization device 22 and the connectivity processing device 23, and the other configurations are exactly the same. be. Enlargement processing device 3
An example of 0 is shown in FIG. The device consists of 31 (m ₂ -1) n-bit shift registers and 2 m _1- bit shift registers _32m . These shift registers are driven by the same sampling clock. n is made to match the number of sampling points in the horizontal direction of the imaging device. Also, m ₁ , m ₂
is determined by the sampling time interval, the vertical resolution of the imaging device 21, and the size of the defect to be detected. For example, if the sampling time interval and vertical resolution are each equivalent to 10 μm, and the size of the defect is 30 μm square, m ₁ = m ₂ = 3 (18th
figure). and a shift register 32 of m ₁ ×m ₂
The output of
Output for 3. In FIG. 18, the outputs of all the shift registers 32 are led to the R circuit 34, but they may be selectively taken out depending on the type of defect to be detected. 19 shows the result of enlarging the binary pattern shown in FIG. 12 by the apparatus shown in FIG. 18.
As shown in the figure. Further, the pattern after the enlargement process of the pattern to be inspected shown in FIG. 14 is shown in FIG. 20, and the connection data generated by the connectivity process is shown in Table 8. Furthermore, attribute data and defect determination results generated in the same manner as in the first embodiment are shown in Table 9 together with design data.

[Table] As is clear from this result, a pattern spacing smaller than the specified value (30 μm in this example) can be detected as a short circuit. However, it is not possible to distinguish between small short-circuit pattern intervals, and there is a possibility that minute disconnections may be overlooked. As described above, according to this embodiment, a pattern defect detection device can be realized with a relatively simple configuration when it is sufficient to detect short circuits and small pattern intervals without distinction. Next, a fifth embodiment will be explained. FIG. 21 shows the configuration of a device that specifically executes this embodiment. As is clear from the figure, in this example, the first
This is a combination of the above embodiment and the fourth embodiment. Table 10 shows the attribute data and defect determination results detected from the pattern to be inspected shown in FIG. The apparatus shown in Figure 21 is adapted from the apparatus shown in Figures 7 and 17, and reference numbers common to those figures represent the same parts as in those figures, and reference numbers are As in FIG. 16, the appended a indicates that the pattern belongs to the series that processes the original pattern, and the appended c indicates that it belongs to the series that processes the enlarged pattern. The processing in each series is exactly the same as the processing in the first and fourth examples, but finally, as in the third example, the judgment results obtained from the enlarged pattern of the judgment results obtained from the original pattern are Add processing to make a comprehensive judgment. That is, as shown in Table 10, the two judgment results make it possible to distinguish between short circuits and small pattern intervals, and also eliminate the possibility of overlooking minute breaks. In this way, according to this embodiment, short circuits and small pattern intervals can be detected separately.

[Table] Next, a sixth embodiment of the present invention will be described. FIG. 22 shows the configuration of a device that specifically executes this embodiment. As is clear from the figure, this embodiment is a combination of the second embodiment and the fourth embodiment. Attribute data and defect determination results detected from the pattern to be inspected shown in FIG. 14 are shown in Table 11 together with the design data. The process to reach this point is the second step.
This is exactly the same as the fourth example. However, at the end, processing is added to comprehensively judge the judgment results obtained from the reduced pattern and the judgment results obtained from the enlarged pattern. In other words, as shown in Table 12, from the two judgment results, it is not possible to distinguish between a small pattern interval and a minute short circuit, and between a small pattern width and a minute disconnection, but it is possible to completely distinguish and detect the others. It's there, and you can't miss it. As described above, according to this embodiment, it is possible to distinguish and detect complete short circuits, complete wire breaks, small pattern spacing or fine short circuits, and small pattern widths or fine wire breaks.

【table】

[Table] Next, a seventh embodiment of the present invention will be described. FIG. 23 shows the configuration of an apparatus that specifically executes this embodiment. As is clear from the figure, this embodiment is a composite of the first, second, and fourth embodiments. Attribute data and defect determination results detected from the pattern to be inspected shown in FIG. 14 are shown in Table 13 together with the design data.

[Table] The processing up to this point is exactly the same as in the first, second, and fourth examples. However, at the end, a process is added to comprehensively judge the judgment results obtained from the reduced pattern, the judgment results obtained from the enlarged pattern, and the judgment results obtained from the original pattern. In other words, as shown in Table 14, from the three judgment results, complete disconnection,
Complete short circuits, minute disconnections, minute short circuits, small pattern widths, and small pattern spacings can be completely distinguished and detected, and nothing will be overlooked. in this way,
According to this embodiment, it is possible to detect defects by completely distinguishing their types.

[Table] Next, the memory capacity and processing time required for the seven embodiments described above will be considered. Assuming that there are 256 x 256 pads on one board,
First, calculate the memory capacity. In this case, the pad number can be expressed in 16 bits (2 bytes). Assuming that all pads are detected by connectivity processing, the generated connection data is (16bit + 16bit) × 256 ² = 2097152bit = 262.144kbyte, and the design data is 16bit × 256 ² = 1048.576bit = 131.072kbyte, and the attribute data is: If expressed in 4 bits including the reserve, it becomes 4 bits x 256 ² = 262144 bits = 32.768 kbytes. The total memory capacity is calculated for each of the first to seventh embodiments. First example 425.984 kbyte 2nd 425.984 kbyte 3rd 720.896 kbyte 4th 425.984 kbyte 5th 720.896 kbyte 6th 720.896 kbyte 7th 1015.808 kbyte. With 64kbytes of RAM, these are:
Although 52 to 124 pieces are required, this is a sufficiently achievable capacity and should not pose any problems considering future increases in RAM capacity. For example, the amount of information in the original image when detecting a 150mm square board with a resolution of 5μm
Compared to 900Mbit (=112.5Mbyte), these can be said to be extremely compact. Furthermore, processing time shall be evaluated based on the number of times the design data is referenced. If the average number of pads on one connected pattern is n, then the average number of references required to discover the parent pad when generating attribute data is as follows, assuming that all patterns are defect-free.

〔Effect of the invention〕

According to the present invention, an enlarged image signal of the wiring pattern to be inspected is obtained by performing enlargement and reduction image processing on the image signal of the entire wiring pattern to be inspected detected by the imaging means to short-circuit potential defective parts that may cause a short circuit. and forming a reduced processed image signal of the wiring pattern to be inspected in which the potential defective portion that is likely to be cut has been cut, and a first and second Create second connection information, and compare each of the created first and second connection information with reference connection information between a plurality of points of interest indicating normal connection relationships of each wiring pattern to be inspected. By detecting latent defects such as half-short circuits and half-open wires in wiring patterns, the amount of information used to compare potential defects that affect reliability even after long-term use is reduced. This has the effect of being able to perform detection at high speed and with high reliability without erroneous detection.

[Brief explanation of drawings]

Fig. 1 is a plan view of an example of the original pattern, Fig. 2 is a plan view of a pattern obtained by applying reduction processing to the pattern shown in Fig. 1, and Fig. 3 is a plan view of the pattern shown in Fig. 1. FIG. 4 is a diagram showing the structure of connection data, FIGS. 5 and 6 are plan views showing two different examples of circuit patterns, and FIG. A block diagram showing the configuration of an apparatus for carrying out the method according to the first embodiment of the present invention, FIG. 8 is a plan view of an example of a pattern to be inspected, and FIG. FIG. 10 is a plan view of a normal pattern corresponding to an inspection pattern, FIG. 10 is a block diagram showing the configuration of an apparatus for carrying out the method according to the second embodiment of the present invention, and FIG. 11 is a diagram showing the configuration of a reduction processing apparatus. Block diagram shown,
Figure 12 is a diagram showing an example of a binary pattern;
The figure is a pattern diagram obtained by applying a reduction process to the pattern shown in FIG. 12, FIG. 14 is a plan view of another example of the pattern to be inspected, and FIG.
FIG. 16 is a plan view of a pattern obtained by applying reduction processing to the pattern shown in the figure; FIG. 16 is a block diagram showing the configuration of an apparatus for carrying out the method according to the third embodiment of the present invention; FIG. is a block diagram showing the configuration of an apparatus for carrying out the method according to the fourth embodiment of the present invention, FIG. 18 is a block diagram showing the configuration of an enlargement processing apparatus, and FIG. A pattern diagram obtained by enlarging the pattern; FIG. 20 is a plan view of the pattern obtained by enlarging the pattern shown in FIG. 14;
FIGS. 21, 22, and 23 are block diagrams showing the configuration of an apparatus for carrying out the methods according to the fifth, sixth, and seventh embodiments of the present invention, respectively. 21...imaging device, 22...value conversion device, 23,
23a, 23b, 23c... Connectivity processing device, 2
4, 24a, 24b, 24c...Connection data/memory, 25...Processing device, 26...Design data/memory
Memory, 27...Pad position data memory, 2
8...Attribute data memory, 29...Reduction processing device, 30...Enlargement processing device, 31, 32...Shift register, 33...AND circuit, 34...OR
circuit.

Claims (1)

[Scope of Claims] 1. An optical image of the wiring pattern to be inspected is captured by an imaging means and converted into an image signal, the image signal is converted to a binary image signal by a binarization means, and the wiring pattern to be inspected is Enlargement of the wiring pattern to be inspected by performing enlargement image processing on the entire converted binary image signal to short-circuit potential defective parts where the wiring pattern spacing does not meet a predetermined value on the image A first image signal between a plurality of points of interest that forms a processed image signal and shows the connection relationship of each wiring pattern with respect to the formed enlarged processed image signal of the wiring pattern to be inspected.
connection information is created, and the binary image signal converted over the entire wiring pattern to be inspected is subjected to reduction image processing to identify potential disconnections where the width of the wiring pattern does not meet a predetermined value on the image. A reduced processed image signal of the wiring pattern to be inspected with the defective portion cut is formed, and a signal between a plurality of points of interest indicating the connection relationship of each wiring pattern is calculated for the reduced image processed signal of the formed wiring pattern to be inspected. 2 connection information is created, and each of the created first and second connection information is compared with reference connection information between a plurality of points of interest indicating normal connection relationships of each wiring pattern to determine the wiring to be inspected. A method for detecting defects in wiring patterns, the method comprising detecting latent defects in a pattern that are likely to cause a short circuit and potential defects that are likely to cause a disconnection. 2. Imaging means for capturing an optical image of the wiring pattern to be inspected and converting it into an image signal, and 2. Converting the image signal obtained by the imaging means into a binary image signal.
A short circuit in which the interval between the wiring patterns on the image does not satisfy a predetermined value is detected by enlarging image processing on the digitized image signal obtained by the digitization means and the entire wiring pattern to be inspected by the digitization means. an enlarged image signal forming means for forming an enlarged image signal of a wiring pattern to be inspected in which a potential defective portion is short-circuited; and an enlarged processing of the wiring pattern to be inspected formed by the enlarged image signal forming means. a first connection information creation means for creating first connection information between a plurality of points of interest indicating the connection relationship of each wiring pattern with respect to the image signal; A reduced image signal of a wiring pattern to be inspected in which a potential defective part where the width of the wiring pattern does not meet a predetermined value on the image and is likely to be cut is cut by performing reduction image processing on the obtained binary image signal. A reduced image signal forming means for forming a reduced image signal forming means, and a reduced image signal forming means for forming a reduced processed image signal of a wiring pattern to be inspected formed by the reduced processed image signal forming means. A second connection information creation means for creating second connection information, and a normal connection between each of the first and second connection information created by the first and second connection information creation means and each wiring pattern. It is characterized by comprising a latent defect detection means for detecting a latent defect that is likely to cause a short circuit or a latent defect that is likely to cause a disconnection in the wiring pattern to be inspected by comparing reference connection information between a plurality of points of interest showing a relationship. Wiring pattern defect detection device.