JPH0577352B2 - - Google Patents

Description

[Detailed Description of the Invention] [Summary] This invention relates to a power supply regulator, particularly a regulator used in a power supply circuit that supplies power to a Josephson logic gate in a Josephson integrated circuit, and has a large duty ratio and a timing function. In addition, the purpose of the present invention is to provide a power supply regulator that is configured with a simple circuit and occupies a small area. a second branch connected in parallel to said first branch and having a second plurality of Josephson junctions and a second resistor connected in series; and a magnetic field control line that is magnetically coupled to the plurality of Josephson junctions of 2 and controls a critical current, and a connection point between the first plurality of Josephson junctions and the first resistor and/or the second plurality of Josephson junctions. Josephson junction and the second
The configuration is such that power is extracted from the connection point with the resistor.

[Industrial Field of Application] The present invention relates to a power supply regulator, and more particularly to a regulator used in a power supply circuit that supplies power to a Josephson logic gate in a Josephson integrated circuit.

Generally, Josephson logic gates are biased below their critical current when an input signal is applied to them, and switching occurs when the input signal causes the critical current to be exceeded. In order to perform the operation stably, it is necessary that the bias current be stable. For this reason, a power supply circuit that supplies bias current is provided with a regulator that stabilizes the bias current.

[Prior Art] A conventional power supply regulator will be explained using FIG. 6.

In FIG. 6, the power supply regulator 13 inserted between the AC power supply v ₀ and the ground GND includes a plurality of Josephson junctions J ₃₁ , J ₃₂ , J ₃₃ ,
J ₃₄ are connected in series.

Now, when the sine wave current supplied from the power supply v ₀ gradually increases from zero, at first all the current flows from the power supply regulator 13 to the ground GND, and the output of the power supply regulator 13 is zero. . This power supply regulator 13
The current flowing through Josephson junctions J ₃₁ , J ₃₂ , J ₃₃ ,
When the critical current of J ₃₄ is exceeded, the power supply regulator 13 is switched and the output current of the power supply regulator 13 is changed to the supply resistance.
It begins to flow through Josephson logic gates G ₃₁ , G ₃₂ , G ₃₃ , . . . via R ₅₁ , R ₅₂ , R ₅₃ , .

The output voltage is nVg (Vg is the gap voltage,
n is the number of Josephson junctions connected in series; in FIG. 6, n=4).
At this time, Josephson junctions J ₃₁ , J ₃₂ , J ₃₃ , and J ₃₄ exhibit low voltage characteristics, and the output voltage does not change even if the current supplied from the power supply increases. Therefore, the output voltage is clipped at nVg and no further output current flows through Josephson logic gates G ₃₁ , G ₃₂ , G ₃₃ , .

When the current from the power source v ₀ decreases and the output voltage drops below nVg, the Josephson junctions J ₃₁ , J ₃₂ , J ₃₃ ,
_J34 enters the sub-gap region, and the output current decreases sinusoidally.

In this way, the sinusoidal power from the AC power source v ₀ is converted into bipolar pulses and supplied to Josephson logic gates G ₃₁ , G ₃₂ , G ₃₃ , .

However, in the above-mentioned conventional power supply regulator, it is actually impossible to eliminate variations in the critical current of multiple Josephson junctions, and therefore, due to variations in critical current, the Josephson junctions sequentially undergo voltage transitions. As a result, the output waveform of the power supply regulator becomes a stepped waveform, resulting in a problem that the duty ratio, which is the time ratio during which the voltage amplitude is constant within one cycle, becomes small.

In order to solve this problem, a power supply regulator as shown in FIG. 7 has been proposed (see Japanese Patent Application No. 62-171551).

In Fig. 7, the power supply regulator 14 inserted between the power supply v ₀ and the ground GND
is multiple Josephson junctions J ₄₁ , J ₄₂ , J ₄₃ , J ₄₄
and a first branch in which a resistor R ₆₁ is connected in series, and a plurality of Josephson junctions J ₄₅ , J ₄₆ , J ₄₇ ,
J ₄₈ and a second branch in which the resistor R ₆₂ is connected in series are connected in parallel.
The connection point between the resistors R61 and R62 is connected to the power supply _v0 , and the connection point between the Josephson junction _J44 and the Josephson junction _J48 is connected to the ground GND.

Furthermore, multiple Josephson junctions J ₄₁ , J ₄₂ , J ₄₃ ,
Output terminals A and B are provided at the connection point between J ₄₄ and the resistor R61 and the connection point between the plural Josephson junctions J ₄₅ , J ₄₆ , J ₄₇ , J ₄₈ and the resistor R62, respectively. These output terminals A and B are connected to Josephson logic gates G ₄₁ , G ₄₂ , G ₄₃ , . . . via supply resistors R ₇₁ , R ₇₂ , R ₇₃ , .

According to this proposal, if the current from the power supply v ₀ exceeds the critical current of the Josephson junction with the smallest critical current value and the Josephson junction J ₄₁ with the first branch switches to the voltage state, then this first The current flowing in one branch flows into the other second branch. This causes the current flowing in the second branch to flow through Josephson junctions J ₄₅ , J ₄₆ , J ₄₇ ,
J ₄₈ becomes sufficiently larger than the critical current of all Josephson junctions of the second branch J ₄₅ , J ₄₆ , J ₄₈ ,
Immediately switch J ₄₈ to voltage state. As a result, the current flowing in the second branch is now
branch, and switches all unswitched Josephson junctions J ₄₂ , J ₄₃ , and J ₄₄ of the first branch.

In this way, all Josephson junctions J ₄₁ , J ₄₂ ,..., J ₄₈ of the power supply regulator 14
By switching both at the same time, the duty ratio can be increased.

By the way, when manufacturing an integrated circuit, it is often necessary to vary the timing at which a bias current rises. For example, a power supply circuit for a logic gate such as an exclusive OR gate or a timed inverter must generate a bias current with a timing different from that of a control current. However, the power supply regulator proposed above cannot make the rise timing of the bias current variable.

In order to solve this problem, a series SQUID (quantum interference device) type power supply regulator as shown in Fig. 8 has been proposed (Transactions of the Institute of Electronics and Communication Engineers '86/5 Vol. J69-C No.5
(See p629).

In Figure 8a, the power supply regulator inserted between the power supply v ₀ and the ground GND is
Magnetic coupling type SQUID151, 152, 153,
Connect 154 in series and connect the output line to SQUID151,
152, 153, and 154 as magnetic field control lines 16. In addition, the resistances R ₈₁ and R ₉₁ in the figure
are a resistance provided for convenience of measurement and an equivalent load resistance, respectively.

And these SQUID151, 152, 15
3 and 154 are superconducting rings having two Josephson junctions J ₅₁ and J ₅₂ and two inductances L ₂₁ and L ₂₂ , respectively, as shown in FIG. 8b.
A terminal for applying a bias current is provided at the connection point between the two inductances L ₂₁ and L ₂₂ . And this 2-junction SQUID151, 152, 153, 15
The magnetic field bonding wires 16 are coupled twice to each of the 4s.

This conventional series SQUID type power supply regulator changes the critical current using a magnetically coupled SQUID, and feeds back the output current to the magnetic field control line of the SQUID, so that one SQUID can control the voltage. When the SQUID transfers, the remaining SQUIDs also undergo voltage transfer.

Therefore, even if there are variations in the critical current values, all SQUIDs can undergo voltage transition almost simultaneously, and the timing of the switch can be controlled by controlling the critical current using the magnetic field junction line.

[Problems to be Solved by the Invention] However, the above conventional series SQUID type power supply regulator having a timing function has a problem in that the circuit configuration is complicated because SQUIDs are used.

Furthermore, in order to increase the degree of magnetic coupling between the SQUID and the magnetic coupling line, it is necessary to increase the inductance, which causes the problem that the occupied area becomes large.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a power supply regulator that has a large duty ratio and a timing function, is configured with a simple circuit, and occupies a small area.

[Means for Solving the Problem] The above problem provides a first branch that is inserted between a power source and a ground, and in which a first plurality of Josephson junctions and a first resistor are connected in series;
a second branch connected in parallel to the branch of the invention and having a second plurality of Josephson junctions and a second resistor connected in series, and magnetically coupled to the first and second plurality of Josephson junctions, the critical current and a connection point between the first plurality of Josephson junctions and the first resistor and/or a connection point between the second plurality of Josephson junctions and the second resistor. This is achieved by extracting power from the

[Function] That is, in the present invention, since branches having a plurality of Josephson junctions are connected in parallel, even if there are variations in the critical current of the Josephson junctions,
By exchanging current between the two branches, all Josephson junctions are switched to a voltage state at approximately the same time. The timing of the switch is also controlled by controlling the critical current of all Josephson junctions by means of magnetic field coupling lines.

[Example] The present invention will be specifically described below based on an illustrative example.

FIG. 1 is a circuit diagram showing a power supply regulator according to a first embodiment of the present invention, and FIG.
A top view of the power supply regulator shown in the figure,
3 and 4 are a partial perspective view and a partial sectional view, respectively, of the power supply regulator shown in FIG. 2.

In FIG. 1, a power supply regulator 1 is inserted between an AC power source v ₀ and ground GND. This regulator 1 includes a first branch in which a resistor R ₁₁ and a plurality of Josephson junctions J ₁₁ , J ₁₂ , JJ ₁₃ , J ₁₄ are connected in series, a resistor R ₁₂ and a plurality of Josephson junctions J ₁₅ , J ₁₆ , _J17 , _J18
are connected in series, and a second branch is connected in parallel.

Also, all Josephson junctions J ₁₁ , J ₁₂ ,…,
A magnetic field control line 2 is coupled to _J18 . This magnetic field control line 2 is connected to a current source i ₀ .

The connection point between the resistor R ₁₁ and the resistance R ₁₂ is connected to the power supply v ₀ , and the connection point between the Josephson junction J ₁₄ and the Josephson junction J ₁₈ is connected to the ground GND.

Furthermore, output terminals A and B are provided at the connection point between the resistor R ₁₁ and the Josephson junction J ₁₁ and the connection point between the resistor R ₁₂ and the Josephson junction J ₁₅ , respectively, and the output terminals are connected to each other via supply resistors R21, R22, R23, and R24. , Josephson logic gates G ₁₁ , G ₁₂ , G ₁₃ ,
Each is connected to... In FIG. 2, the base electrode 31 connected to the power source v ₀ has a resistance R ₁₁ ,
It is connected to base electrodes 32 and 33 via _R12 . These base electrodes 32 and 33 are connected to the counter electrode 4 via Josephson junctions J ₁₁ and J ₁₅ , respectively.
1 and 42. These counter electrodes 4
1 and 42 are Josephson junctions J ₁₂ and J ₁₆ , respectively.
It is connected to base electrodes 34 and 35 via. These base electrodes 34, 35 are connected to counter electrodes ₄₃ , ₄₄ via Josefson junctions J13, J17. These counter electrodes 43, 44
are connected to the base electrode 36 via Josefson junctions J ₁₄ and J ₁₈ . And this base electrode 3
6 is connected to ground GND.

Note that these base electrodes 31, 32,..., 36
The counter electrodes 41, 42, 43, and 44 are all made of a superconductor, such as niobium Nb.

Furthermore, magnetic field control lines 2 are provided on Josephson junctions J ₁₁ , J ₁₂ , . . . , J ₁₈ to provide magnetic field coupling. Furthermore, although not shown, the base electrodes 32 and 33 are connected to each other via supply resistors R ₂₁ , R ₂₂ , R ₂₃ ,...
They are connected to Josephson logic gates G ₂₁ , G ₂₂ , G ₂₃ , . . . , respectively.

In addition, the magnetic field control line 2, the base electrodes 31, 32,
..., 36, and counter electrodes 41, 42, 43, 4
4 are both made of a superconductor, for example niobium Nb.

A perspective view and a sectional view of the Josephson junction _J11 in the power supply regulator 1 shown in FIG. 2 are shown in FIGS. 3 and 4, respectively. A ground plane 6 made of a superconductor such as niobium Nb is formed on a silicon Si substrate 5. A base electrode 32 is formed on this ground plane 6 with a ground plane insulating layer 7 interposed therebetween. On this base electrode 32, a counter electrode 41 is formed with a tunnel oxide film 8 made of _AlOx , for example, interposed therebetween, and a Josephson junction is formed.
It makes up J ₁₁ . The base electrode 32 and the counter electrode 41 other than the Josephson junction _J11 are insulated by an interlayer insulating layer 91. Furthermore, a magnetic field control line 2 is provided above the Josephson junction J ₁₁ via an interlayer insulating layer 92 .

Next, the operation will be explained.

If the current from the source v ₀ exceeds the critical current of the Josephson junction with the smallest critical current value and a Josephson junction with one branch, for example the Josephson junction J ₁₁ of the first branch, switches to a voltage state, this Josephson junction 1st including J ₁₁
The current flowing in one branch flows into the other second branch.

As a result, the current flowing in the second branch becomes sufficiently larger than the critical current of these Josephson junctions J ₁₅ , J ₁₆ , J ₁₇ , and J ₁₈ , and the Josephson junction
J ₁₅ , J ₁₆ , J ₁₇ , and J ₁₈ all quickly switch to voltage state.

As a result, the Josephson junctions J ₁₅ , J ₁₆ ,
The first current is sufficiently larger than the critical current of J ₁₇ and J ₁₈ .
flows into the branch of this first branch that has not yet switched Josephson junction J ₁₂ ,
Switch all J ₁₃ and J ₁₄ .

In this way, according to the first embodiment, even if there are variations in the critical current of each Josephson junction, by exchanging current between two branches connected in parallel, all Josephson junctions can be ₁₁ , J ₁₂ , ..., J ₁₈ can be switched almost simultaneously. This allows the duty ratio to be increased.

Further, the critical currents of all the Josephson junctions J ₁₁ , J ₁₂ , . . . , J ₁₈ are controlled by the magnetic field control line 2 . When the current supplied from the power supply v ₀ exceeds this controlled critical current, the Josephson junction is switched to the power state. The magnetic field control line 2 thus makes it possible to control the timing of the switches of the Josefson junctions J ₁₁ , J ₁₂ , . . . , J ₁₈ and thus of the power supply regulator 1 . That is, this power supply regulator 1 can have a timing function necessary for the operation of logic gates such as exclusive OR gates and timed inverters. Thus, it can be widely applied to Josephson integrated circuits.

The power supply regulator 1 according to the first embodiment has a single junction Josephson junction J ₁₁ ,
Since J ₁₂ , ..., J ₁₈ are used, the circuit configuration is simplified and the area occupied is also reduced.

Furthermore, in the first embodiment, the magnetic field control line 2
Since the sensitivity of the sensor is not strictly questioned, the occupied area does not become large.

In this way, a power supply regulator with a timing function, which has a simple circuit configuration and occupies a small area, is formed.

Next, a second embodiment of the present invention will be described using FIG. 5.

FIG. 5 is a circuit diagram showing a power supply regulator according to a second embodiment of the present invention.

This second embodiment is based on Josephson junction in the power supply regulator 1 shown in FIG.
In place of J ₁₁ , J ₁₂ , ..., J ₁₈ , two-junction SQUID is used in each power supply regulator 10.
111, 112, . . . , 118 are used.

That is, in FIG. 5a, a first branch in which a resistor R ₃₁ and a plurality of SQUIDs 111, 112, 113, 114 are connected in series, and a resistor R ₃₂
and multiple SQUIDs 115, 116, 117,
118 are connected in series, and the second branch is connected in parallel. Also, all
A magnetic field control line 12 is coupled to the SQUIDs 111, 112, ..., 118, and this magnetic field control line 12 is
Connected to current source i ₀ .

Then, the connection point between resistor R31 and resistor R32 is connected to AC power supply v ₀ , and SQUID114 and SQUID1
The connection point with 18 is connected to the ground GND.
Furthermore, output terminals A and B are provided at the connection point between the resistor R31 and the SQUID 111 and the connection point between the resistor _{R32 and} the SQUID ₁₁₅ , respectively, and the Josephson logic gate They are connected to G ₂₁ , G ₂₂ , G ₂₃ , ..., respectively.

These SQUID111, 112,...,118
As shown in FIG. 6a, there are two Josephson junctions J ₂₁ , J ₂₂ and two inductances L ₁₁ ,
A superconducting ring having L ₁₂ is provided with a terminal for applying a bias current to the connection point of two inductances L ₁₁ and L ₁₂ . and these two junctions
The magnetic field control line 12 is coupled once to the SQUIDs 111, 112, . . . , 118.

The operation of the power supply regulator 10 according to the second embodiment is similar to the first embodiment shown in FIG.
This is similar to the embodiment.

Note that in the second embodiment, two-junction SQUID
However, 3-junction SQUIDs may be used instead of these, or even more junctions may be used.
SQUIDs may also be used.

In addition, in the first and second embodiments, the two output terminals A and B are used to output to the Josephson logic gate, but it is not necessary to use two terminals, and it is also possible to output from only one terminal. good.

[Effects of the Invention] As described above, according to the present invention, branches having a plurality of Josephson junctions are connected in parallel, and the critical current of these Josephson junctions is controlled by a magnetic coupling line, so that A circuit configuration that allows all Josephson junctions to be switched substantially simultaneously and the timing of this switch to be controlled.

As a result, a power supply regulator that can supply a highly stable bias current with a large duty ratio can occupy a small area and have a timing function.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing a power supply regulator according to a first embodiment of the present invention, and FIG.
A top view of the power supply regulator shown in the figure,
3 and 4 are a partial perspective view and a partial sectional view, respectively, of the power supply regulator shown in FIG. 2, and FIG. 5 is a circuit diagram showing a power supply regulator according to a second embodiment of the present invention. , Fig. 6 is a circuit diagram showing a conventional power supply regulator, Fig. 7 is a circuit diagram showing a proposed power supply regulator, and Fig. 8 is a circuit diagram showing a conventional power supply regulator.
FIG. 2 is a circuit diagram showing a SQUID type power supply regulator. In the figure, 1, 10, 13, 14... power supply regulator, 2, 12, 16... magnetic field control line, 31, 32,..., 36... base electrode, 4
1, 42, 43, 44... Counter electrode, 5... Silicon Si substrate, 6... Ground plane, 7... Ground plane insulating layer, 8... Tunnel oxide film,
91, 92... interlayer insulating layer, 111, 112,
..., 118, 151, 152, 153, 154...
…SQUID, J ₁₁ , J ₁₂ ,…, J ₁₈ , J ₂₁ , J ₂₂ , J ₃₁ ,
J ₃₂ , J ₃₃ , J ₃₄ , J ₄₁ , J ₄₂ , …, J ₄₈ , J ₅₁ , J ₅₂ …
Josephson junction, R ₁₁ , R ₁₂ , R ₃₁ , R ₃₂ , R ₆₁ ,
R ₆₂ , R ₈₁ , R ₉₁ ...Resistance, R ₂₁ , R ₂₂ , R ₂₃ , R ₄₁ ,
R ₄₂ , R ₄₃ , ₅₁ , R 52 , R ₅₃ , R ₇₁ , R ₇₂ , R ₇₃ ... Supply resistance, G _{11 ,} G ₁₂ , G ₁₃ , G ₂₁ , G ₂₂ , G ₂₃ ,
G ₃₁ , G ₃₂ , G ₃₃ , G ₄₁ , G ₄₂ , G ₄₃ ... Josephson logic gate, L ₁₁ , L ₁₂ , L ₂₁ , L ₂₂ ... Inductance, v ₀ ... Power supply, GND ... Ground, i ₀ ... Constant current source, A, B... Output terminal.

Claims (1)

[Claims] 1. A first branch inserted between a power source and ground, and having a first plurality of Josephson junctions and a first resistor connected in series, and connected in parallel to the first branch. a second branch having a second plurality of Josephson junctions and a second resistor connected in series; and a second branch magnetically coupled to the first and second plurality of Josephson junctions to control a critical current. the first plurality of Josephson junctions and the first
and/or a connection point between the second plurality of Josephson junctions and the second resistor.