JPH057739B2 - - Google Patents

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention divides main memory into a hardware area that cannot be accessed by normal programs and a software area that stores normal programs. Regarding a data processing system configured to use for exchanging hardware information within the system, specifically, in a data processing system that uses a virtual memory method, prohibiting general instructions from accessing the hardware area. Concerning the composition method for

[Background of the invention]

In recent years, in addition to the software area (SA) that stores regular programs on the main memory (MS),
A system has been realized in which a hardware area (HA) that cannot be accessed by normal programs is allocated so that only the hardware can use the HA.
No. 124952). Figure 4 shows the MS of such a system.
MS1 is divided into software area (SA) 2 and hardware area (HA) 3. Normal programs are stored in SA2, and HA
3 stores information used by the system hardware (hardware information). Furthermore, 4 is
This is a boundary address that separates SA2 and HA3.

When trying to implement such a system,
A mechanism is required to prevent normal programs from accessing the HA, but this was conventionally achieved using the configuration shown in Figure 5. In Figure 5, MS
When there is an access request to the MS access address, the MS access address is set in the register 10. On the other hand, the boundary address that separates the SA and HA on the MS is set in the register 11 in advance. As shown in Figure 4, the address area below the boundary address is SA, and the address area above the boundary address is SA.
HA. Comparator 12 compares the contents of register 10 and register 11, and outputs "0" if the MS access address is a boundary address, and outputs "1" if MS access>boundary address. Signal line 13
is a control line that becomes "1" when the relevant main memory reference is permitted to access HA, and becomes "0" otherwise. When the signal line 13 is “0”, the output of the inverting circuit 15 is “1”, and at this time, the output of the comparator 1
2 is "1", the AND condition of the AND circuit 16 is satisfied, and the output of the OR circuit 17 is "1".
becomes. This means that the HA was accessed by a main memory reference that is not permitted to access the HA. In other words, an addressing exception is established and the corresponding
MS access is prohibited. The signal line 14 is a control line that becomes "1" when another address command exception condition is satisfied.

Incidentally, conventionally, access exception detection means having the configuration shown in FIG. 5 was provided on both the central processing unit (CPU) side and the storage control unit (SC) side. this is,
In general, an SC has an input processing device (IOP) in addition to the CPU.
is also connected, and it is necessary to check HA access from the IOP, so it is necessary to provide an access exception detection means in the SC.On the other hand, the CPU uses the access exception detection means of the SC. This is due to the fact that there are delays and interrupt processing does not go well, and it is necessary to have access exception detection means in the CPU as well.

However, when distributing multiple HAs and placing them on an MS, one HA requires two boundary registers (for the HA start address and HA end address) and two comparators (for the HA start address and HA end address). for comparison) is required, and this is
A problem arises in that the amount of hardware required increases by the number of HAs.

[Purpose of the invention]

The purpose of the present invention is to divide MS into SA and HA,
The purpose of this invention is to reduce the amount of hardware by eliminating the access exception detection means in the CPU in a virtual memory data processing system that uses HA to exchange hardware information within the system.

[Summary of the invention]

In a virtual memory data processing system, an address translation buffer (TLB) that stores frequently used pairs of logical addresses and real addresses is used to quickly convert logical addresses to real addresses.
Equipped with: The present invention focuses on this point,
A flag is set for each entry in the TLB to indicate whether the real address in the entry points to HA, and when the TLB is referenced, the corresponding logical address is determined based on the comparison result between the flag and the type of main memory reference. Forcibly even if is registered in the TLB
It is determined that the TLB is not registered, performs normal address translation operation, and uses the access exception detection means in the SC to
By determining whether or not to permit access to the HA, the access exception detection means within the CPU is removed.

[Embodiments of the invention]

FIG. 1 is a block diagram of one embodiment of the present invention. In FIG. 1, 20 is the TLB, which is assumed to consist of 512 entries here. Applicable
In addition to the logical address LA and real address RA, each entry in TLB20 contains a flag (F
bits) are included. The F bit is "1" if the real address in the corresponding entry is HA, and "0" if it is SA.

The logical address issued from the MS access request source is set in the logical address register 21.
A predetermined logical operation (hashing) is performed on the upper bits of this logical address register 21, and the TLB 20 is
and read one entry. The comparator 22 compares the logical address LA read from the TLB 20 and the upper address of the logical address register 21, and outputs "1" if the two match. That is, this is logical address register 2
This indicates that the real address RA corresponding to the logical address set to 1 exists in the TLB20. This is called “In TLB”. On the other hand, in the case of a mismatch, the comparator 22 outputs "0", which indicates that the real address corresponding to the logical address does not exist in the TLB 20. This is called “Not inTLB”.

The output of the comparator 22 is applied to the access control circuit 23 together with the F bit read out from the corresponding entry of the TLB 20 at the same time. This access control circuit 23 is further connected to the HA by a signal line 13.
Access bits are also provided. FIG. 2 summarizes the operations of the access control circuit 23 in a table. From Figure 2, under the condition that In TLB, that is, the comparator output is “1”, if the HA access bit is “0” and the F bit of the corresponding entry in TLB20 is “1”, Not in TLB is forced. In order to do so, the access control circuit 23 outputs "0".
When the output of the access control circuit 23 is "0", the AND circuit 24 becomes inactive, and transfer of the real address RA read from the corresponding entry of the TLB 20 to the MS is prohibited. When the output of the access control circuit 23 is "1", the real address RA read from the corresponding entry of the TLB 20 passes through the ANDRESS circuit 24, is merged with the lower address of the logical address register 21, and is transferred to the MS. .

Note that when “Not in TLB”, address translation operation is started and the pair of logical address and real address is
Newly registered in TLB20. Since this address fluctuation operation is well known, further explanation will be omitted, but at this time, the storage control device SC has the access exception detection means explained in FIG. Check whether the real address points to HA. If no addressing exception related to HA access is detected, the result of this check is reflected as the output of the comparator 12 in FIG. 5, so the output of the comparator 12 is obtained via the signal line 25 and the as
Register in the corresponding entry of TLB20.

In the above explanation, an addressing exception is assumed when a main memory reference that is not allowed to access HA attempts to access HA, but depending on the hardware configuration, a main memory reference that is allowed to access HA may It is also conceivable that it would be detected as an abnormal case if a user attempts to access SA.
If the access control circuit 23 operates as shown in FIG. 3, the addressing exception report signal line can be shared in such a case.

The HA access bit may also be provided as a mode signal.

〔Effect of the invention〕

As is clear from the above explanation, according to the present invention, there is no need to have an addressing exception detection mechanism for HA access in the CPU, so the amount of hardware can be reduced, and in particular, it is possible to reduce the amount of hardware required by distributing multiple HAs on the MS. The effect increases when multiple CPUs are placed or when multiple CPUs are connected to one SC. Also, TLBs are generally configured to read at high speed, so
If no addressing exception occurs for HA access, main memory references can be executed at high speed. Note that in the case of Not in TLB, it is necessary to use the access exception detection means in the SC, so the timing of access exception detection is delayed, but the probability of this happening is lower than in In TLB, and the impact on the system is minimal. be.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention;
Figures 2 and 3 are an explanatory diagram of the operation of the access control circuit in Figure 1, Figure 4 is an explanatory diagram of dividing the main memory into a hardware area (HA) and a software area (SA), and Figure 5 is an explanatory diagram of the operation of the access control circuit in Figure 1. The figure is a block diagram showing a conventional HA access addressing exception detection means. 1...Main memory, 2...Software area,
3...Hardware area, 20...Address translation buffer, LA...Logical address, RA...
Real address, F...flag.

Claims (1)

[Claims] 1. A main memory that is divided into a hardware area that cannot be accessed by normal programs and a software area that stores normal programs, a central processing unit, an input/output processing unit, , access exception detection means that determines whether access to the hardware area from the central processing unit or input/output processing unit is permitted, and generates an access exception by ORing with other address exception detections. In a data processing system that employs a virtual memory method and has a storage control device including a and a flag indicating whether the main memory address points to a hardware area is provided corresponding to each entry of the address translation buffer, and when the address translation buffer is referenced, the flag of the entry is set. Based on the comparison result between the address conversion buffer reference result and the type of main memory reference, the address translation buffer reference result is forcibly determined to be unregistered, and the subsequent access exception detection means in the storage control device performs normal address translation operation. What is claimed is: 1. A data processing system that determines whether or not the real address obtained by the method allows the main memory reference, and generates an access exception by ORing with other address exception detections.