JPH057891B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to a synthesizer type radio receiver, and particularly to a radio receiver in which a tuning operation is performed by changing an analog input by operating a tuning knob. It is related to.

<Prior art> By the way, as a radio receiver that can perform tuning operation by changing the analog input based on the operation of the tuning knob, the
There is one as disclosed in Publication No. 24421.

In this method, the voltage generated by the change in resistance value of a variable resistor due to the operation of a tuning knob is compared with the voltage obtained from a low-pass filter in a phase lock loop (PLL circuit). The down counter is placed in an addition or subtraction state to count the reference frequency from the reference oscillator, and the counted value is supplied as the frequency division ratio of the programmable frequency divider in the PLL circuit.

However, as mentioned above, with this conventional system, the voltage generated based on the resistance value of the variable resistor is
Compare it with the voltage value obtained from the low-pass filter in the PLL circuit, and increase or decrease depending on the comparison value.
Since this method involves executing the counting operation of a down counter, it has the disadvantage of becoming circuit-wise complicated.

<Object of the present invention> The present invention was invented in view of the problems of the conventional radio receiver described above, and is basically different from the conventional radio receiver in that the tuning operation is performed by changing the analog input. It is an object of the present invention to provide a radio receiver that can perform tuning operations using a simpler circuit configuration.

<Configuration of the Present Invention> Hereinafter, one embodiment of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a block circuit diagram when the present invention is implemented in an FM tuner. In the figure, 1 is an antenna, and 2 is a signal from 76.0 to
High frequency amplifier that amplifies the reception frequency of 108MHz,
3 is a frequency for obtaining an intermediate frequency of 10.7 MHz, which is the difference between the received frequency from the high frequency amplifier 2 and the local oscillation frequency of 65.3 MHz to 97.3 MHz oscillated by the phase lock loop (hereinafter referred to as PLL circuit) 7. The mixer 4 is an intermediate frequency amplifier that amplifies the intermediate frequency obtained from the mixer 3, and 5 is a detector that obtains an audio signal based on the signal from the intermediate frequency amplifier 4 and supplies it to a terminal 6.

The PLL circuit 7 is a voltage controlled oscillator 8 that outputs the local frequency to be introduced into the frequency mixer 3.
and a programmable frequency divider 10 which digitally divides the output frequency of the voltage controlled oscillator 8 by pre-dividing the frequency into an appropriate frequency divided wave by the pre-frequency divider 9.
The phase of the output frequency of the programmable frequency divider 10 and the reference frequency oscillated by the reference oscillator 13 and divided into an appropriate frequency by the frequency divider 14 are compared, and the comparison contents are passed through the low-pass filter 12. and a phase comparator 11 which applies the voltage to the voltage controlled oscillator 8 to change the output frequency (the local oscillator frequency) of the oscillator 8, and is a well-known device.

Reference numeral 15 designates a division ratio setting unit for the programmable frequency divider 10, which is the main part of the present invention, and includes an analog signal generator 16, an A/D converter 17 for converting an analog signal into a digital signal, and a data It consists of a converter 18.

Specifically, the configuration is as shown in FIG. 2, and the analog signal generator 16 has a constant voltage +
The A/D converter 17 converts the analog output obtained from the slider of the variable resistor 19 into a sampling pulse of an appropriate frequency applied to a terminal 20. Capacitor C as sampling and holding capacitance
It consists of an analog switch 21 that holds the voltage, and an A/D conversion circuit 22 that converts the voltage sampled and held by the capacitor C into 9-bit digital data (input data).

The data converter 18 is composed of an adder 23 in which three binary counters, for example, TTL elements _{74LS283 ,} are cascaded. The input data from the A/D conversion circuit 22 input from the second input terminals B ₁ to B ₉ is added to the reference value, and the result is sent to the programmable frequency divider 10 as a frequency division value N with a frequency division ratio of 1/N. supply.

By the way, the minimum value of the frequency division value N of the frequency division ratio of the programmable frequency divider 10 is not 0, and
For FM broadcasting, such as receiving frequency: 76 to 108 MHz, inter-station frequency: 100 KHz, intermediate frequency: 10.7 MHz, local frequency: 65.3 to 97.3 MHz, the division ratio of the programmable frequency divider 10 is 1/
Since the frequency division value N of N is 653 to 973, if the minimum value is Nmin, the necessary frequency division value N of the programmable frequency divider 10 is N=Nmin (653) + input data (0 to 320). Become.

In this case, since the minimum value Nmin of the required frequency division value N is 653 and the maximum value Nmax is 973 as described above, the input data may be changed within the range of 0 to 320.

In order to change the input data, according to the present invention, the A/D conversion circuit 22 outputs input data of 0 to 320 as a digital value according to the operation of the variable resistor 19, and the adder 23 outputs the input data as a digital value. Input data is received at the second input terminals B ₁ to B ₉ , and the required amount is added to the reference value (minimum value 653) set in advance by fixed input to the first input terminals A ₁ to A ₁₀ . Obtain the frequency value N and use the programmable frequency divider 1
The voltage is applied to 0.

Incidentally, since the number of output bits of the A/D conversion circuit 22 is 9 bits, the actual number of steps is 0 to 9 bits.
512 can be obtained, but if 320 is output when the level of the analog signal from the variable resistor 19 is maximum, the input data obtained from the A/D conversion circuit 22 can be changed from 0 to 320 as described above. It can be adjusted within the range.

Also, the minimum value of the frequency division value N of the adder 23
The fixed inputs related to 653 are the first input terminals A ₁ , A ₃ ,
It is set with a fixed input of binary code [1010110101] by applying voltage +V ₀ to A ₅ , A ₆ , A ₈ and A ₁₀ and grounding terminals A ₂ , A ₄ , A ₇ and A ₉ . .

The above fixed input determines the minimum value Nmin of the frequency division value N. Therefore, if it is necessary to change the minimum value and number of steps of the frequency division value N due to a change in the receiving band or destination, the first By changing the fixed inputs to the input terminals _A1 to _A10 and changing the constant voltage +V applied to the variable resistor 19, the number of steps can be changed to any desired number. The number of steps can also be changed by manipulating each bit of the A/D conversion circuit.

In addition, in the circuit, the second input terminal B ₈ of the adder 23,
A switch 24 provided between _B9 and ground is a step number changing switch which drops the output of the upper two bits of the A/D converter circuit 22 to ground as necessary to correspond to radio broadcasting with a small number of steps.

<Operation of the present invention> Since the present invention is constructed as described above, after setting the radio receiver to the receiving state, turn the tuning knob to move the slider of the variable resistor 19 to a predetermined position. Set to position.

Then, the variable resistor 19 is connected to the capacitor C.
A voltage corresponding to the resistance value is held, and the held voltage (analog output) is converted into a digital value by the A/D conversion circuit 22 and output as input data.

Here, if this input data is "65", this input data is sent to the second input terminals B ₁ to B _9.
is input to the adder 23 of the data converter 18 through the adder 23, where it is added to the reference value (minimum value) 653 of the frequency division value N set in advance, resulting in a frequency division value of "718", which is programmable frequency division. Vessel 1
0.

Therefore, the frequency division ratio of the programmable frequency divider 10 is 1/718, and the frequency divider 10 divides the local oscillator frequency provided from the voltage controlled oscillator 8 via the prescaler 9 by this frequency division ratio. The phase comparator 11 compares the phase with a reference frequency to control the local frequency of the voltage controlled oscillator 8.

As a result, when the local oscillation frequency becomes 71.8MHz, the phase lock loop becomes locked and the FM broadcast station with the reception frequency of 82.5MHz is received.

Thereafter, the analog output output from the variable resistor 19 of the analog signal generator 16 is changed by turning the tuning knob in the same manner, and the analog output is changed to the data converter 18.
By changing the digital input data given to the adder 23, the frequency division value N output from the adder 23 can be changed to sequentially sweep the local oscillator frequency, and it is possible to obtain a broadcasting station with a predetermined receiving frequency. can.

As described above, the present invention A/D converts an analog signal output from an analog signal generator consisting of a variable resistor, and adds the digital data after A/D conversion to a preset reference value. By converting to the required frequency division value, the phase lock
The frequency division ratio of the programmable frequency divider in the loop can be obtained, and the circuit configuration is extremely simple.If the above reference value is set to the minimum value of the necessary frequency division value, for example, the frequency division ratio of the variable resistor can be obtained. It is only necessary to change the output within a relatively narrow range, and the operating stroke of the variable resistor is shortened, resulting in excellent operability.

[Brief explanation of drawings]

FIG. 1 is a block circuit diagram showing an embodiment of the radio receiver of the present invention, and FIG. 2 is a specific circuit diagram of a frequency division value setting section in the same radio receiver. 7... Phase lock loop, 10... Programmable frequency divider, 16... Analog signal generator, 17... A/D conversion, 18... Data converter, 19... Variable resistor.

Claims (1)

[Claims] 1. A local oscillation frequency is obtained from a phase lock loop, and the local oscillation frequency is swept to a predetermined value by varying the division ratio of a programmable frequency divider in the phase lock loop. In devices that receive radio broadcasts, there is an analog signal generator that consists of a variable resistor that changes analog output when operated, and an analog signal generator that converts the analog output of the analog signal generator into digital data and converts it into input data. and an adder that adds the data obtained from the A/D converter to a preset reference value and converts it into a necessary frequency division value, 1. A synthesizer-type radio receiver, characterized in that the frequency division ratio of the programmable frequency divider is set by supplying the necessary frequency division value obtained from the programmable frequency divider to the programmable frequency divider.