JPH057896B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a signal cutoff circuit capable of cutting and turning an output signal on and off using a control gate signal.

Conventional configuration and its problems A signal cutoff circuit normally obtains an output signal intermittently by a combination of a differential input signal circuit and a switching circuit, but the conventional signal cutoff circuit shown in Fig. 1 However, the problem is that the gate offset is noticeable. To explain in detail, in the circuit shown in Figure 1,
The base of each transistor Q ₁ and Q ₂ is connected to a resistor R ₁
A common base bias V ₁ is applied to the base of one transistor _{Q 1 through} a coupling capacitor C ₁ and
Input signal V _io is applied from input signal terminal 1 .
The emitter of the transistor _Q1 is connected to one end (ground point) of the circuit power supply through the resistor _R3 , and the collector is connected to the common emitter point of the pair of transistors _Q3 and _Q4 . Also, transistor Q ₂
The emitter is connected to one end (ground point) of the circuit power supply through the resistor _R4 , and the collector is connected to the common emitter point of the pair of transistors _Q5 and _Q6 . Both of the pair of transistors are cross-coupled, and the collectors of transistors Q ₃ and Q ₅ are commonly connected and coupled to the other end of the circuit power supply (V _CC point), and transistors Q ₄ and Commonly connect each collector with the same Q ₆ through resistor R ₅ ,
Connect it to the other end of the circuit power supply (V _CC point) and take out the output signal (V _put ) from the output signal terminal 2 of the resistor _R5 end. Furthermore, the bases of both of the pair of transistors are connected in common to transistors _Q3 and _Q6 ,
Base bias coupled to V ₂ and transistor Q ₄
and _Q5 are commonly connected, and a switching control signal _V3 is applied to the input terminal 3 of this common base point.

FIG. 2 is a timing diagram of each point showing the circuit operation. First, the input signal V _io is connected to the coupling capacitor C ₁
When applied to the base of the transistor Q ₁ through the input signal V 1 , the base potential V _B1 of the transistor Q ₁ fluctuates with the input signal V _io around the base bias V ₁ as shown in FIG. The emitter voltage V _E1 of the transistor Q ₁ becomes V _E1 = V ₁ + V _io − V _BE1 considering the base-emitter voltage V _BE1 . On the other hand, since the base voltage V _B2 of transistor Q ₂ is the base bias V ₁ ,
The emitter voltage V _E2 of Q ₂ becomes V _E2 = V ₁ − V _BE2 . As a result, the emitter currents I _E1 and I _E2 of the transistors Q ₁ and Q ₂ are as follows.

I _E1 = (V ₁ + V _io − V _BE1 )/R ₃ I _E2 = (V ₁ − V _BE2 )/R ₄ Next, a switching control signal V ₃ as shown in FIG. 2 is applied to input terminal 3. Given this switching control signal V ₃ is the base bias V ₂
When the voltage is larger than that, transistors Q ₃ and Q ₆ are non-conductive, transistors Q ₄ and Q ₅ are conductive, and a transistor is connected to output signal terminal 2.
Due to the current I _E1 flowing through Q ₄ , the output voltage V _put V _put = V _CC − (V ₁ + V _io − V _BE1 ) R ₅ /R ₃ ……1 is obtained, and the input The signal V _io is transmitted. When the switching control signal V ₃ is less than the base bias V ₂ , the transistor Q ₃
Q ₆ is in a conductive state, transistors Q ₄ and Q ₅ are in a non-conductive state, and the transistor is connected to the output signal terminal 2.
Due to the current I _E2 flowing through Q ₆ , the output voltage V _put , V _put = V _CC − (V ₁ − V _BE2 ) R ₅ /R ₄ ...2 is output, and as shown in Fig. 2, the input signal V _io is cut off.

Here, when V _io = 0, R ₃ = αR ₄ , and comparing the DC potential of output signal terminal 2 when switching control signal V ₃ is large and small, the difference ΔV _put between equations 1 and 2 is , ΔV _put = (V ₁ − V _BE1 ) R ₅ / R ₃ − (V ₁ − V _BE2 ) R ₅ / R ₄ = (V ₁ − V _BE1 ) R ₅ / αR ₄ − (V _{1 −} V _BE2 ) R ₅ /R ₄ =R ₅ /R ₄ {(1/α−1)V ₁ +(V _BE2 −1/αV _BE1 )
} ...3. α is the relative ratio between R ₃ and R ₄ , and a variation of 1±0.02 is considered due to the manufacturing of integrated circuits. In addition, generally considered circuit conditions, V ₁ = 2 (V), V _BE = 0.7 (V), (V _BE1 − V _BE2 ) ± 2
Estimating the variation of ΔV _put under the condition of (mV),
The first item in {} in equation 3 is ±40 (mV), the second item is ±14 (mV), and the relative error between resistors R ₃ and R ₄ is a factor in the offset voltage of output signal terminal 2.
It is amplified by the amplifier gain R ₅ /R ₄ and output.
As described above, there has been a problem in that the switching operation of the signal cutoff circuit generates a level difference in the DC voltage at the output signal terminal 2, that is, a so-called gate offset voltage. In addition, in the circuit configuration of FIG. 1, as can be seen from equation 1, the input signal of input signal terminal 1 and the output signal of output signal 2 are inverted in phase.
Only a negative phase output can be obtained, and if it is desired to obtain an in-phase output, another phase inversion circuit must be added.

OBJECTS OF THE INVENTION The present invention provides a signal cutoff circuit that can suppress gate offset voltage and also obtain an in-phase output.

Configuration of the Invention To summarize, the present invention includes a first pair of transistors in which the emitters of first and second transistors Q ₇ and Q ₈ are connected in common, and third and fourth transistors Q ₉ ,
a second transistor pair whose emitters of _Q10 are commonly connected; and _a fifth transistor _Q11 whose base is connected to the emitter of the first transistor Q7.
and a sixth transistor Q12, the emitter of the fifth transistor _Q11 being connected to the emitter via the first resistor _R10 , and the base being connected to the emitter of the fourth transistor _{Q10 .} and a current mirror circuit that mirror-inverts the collector current of the fifth transistor _Q11 and supplies the mirror-inverted current to the collector of the sixth transistor _Q12 . and a second resistor _R11 connected between the collector of the sixth transistor _Q12 and a predetermined potential point _V5 , the second and third transistors _Q8 , _Q9
A switching control signal is applied to the bases of the transistors Q 7 and Q 10 , the same bias potential is applied to the bases of the first and fourth transistors Q ₇ and Q ₁₀ , and an input signal is applied to the bases of the first or fourth transistors. This is a signal cut-off circuit with a special feature, and with this configuration,
Both when an input signal is applied and when the input signal is cut off, the operation can be switched while applying a common potential to both ends of the differential input, and the gate offset voltage is the same as the relative variation in the base-emitter voltage of the transistor. level can be suppressed.

DESCRIPTION OF EMBODIMENTS FIG. 3 is a circuit diagram of an embodiment of the present invention. Transistors Q ₇ and Q ₈ and transistors Q ₉ and Q ₁₀ are transistor pairs in which respective emitters and collectors are connected in common, and the bases of each of these transistor pairs are connected to each other, that is, Connect the bases of transistor Q ₇ and transistor Q ₁₀ in common and connect them with resistor R ₁ and the same
A base bias V ₁ is applied through R ₂ and its one base, e.g.
To the base electrode of Q ₇ , through the coupling capacitor C ₁ ,
An input signal is given from terminal 1. Further, the bases of the other transistor pairs, that is, the bases of the transistor Q ₈ and the base of the transistor Q ₉ are commonly connected to each other, and the switching control signal V ₃ is applied to the terminal 3 of this connection point. Resistors _R6 and _R7 are connected to the common emitter portions of both transistor pairs, respectively. Further, each common collector portion of both transistor pairs is connected to a terminal 4 of the circuit power supply V _CC . In addition, the circuit of Fig. 3 includes a current mirror circuit section consisting of NPN transistors _Q11 and _Q12 , PNP transistors _Q13 and _Q14 as their active loads, and an NPN transistor coupled to the emitter section of the current mirror circuit section. It has a differential amplifier circuit consisting of Q ₁₅ and Q ₁₆ and a current source circuit consisting of resistors R ₈ and R ₉ , and both input parts of this differential amplifier circuit are connected to the common terminal of each transistor pair. Signals from the emitter section are coupled and input, and the output is taken out through terminal 2 from the collector side of transistor _Q12 . In Fig. 3, the resistor _R10 is an emitter resistor that absorbs the potential between the emitters of the differential pair of transistors _Q11 and _Q12 , and the resistor _R11 is _an output bias resistor. ₅ is each current voltage source (bias supply source).

FIG. 4 is a timing diagram showing the operation of the third illustrated circuit, and the operation of the embodiment circuit will be described in detail below with reference to this timing diagram.

First, when the input signal V _io is applied to the input signal terminal 1, the base potential V _B7 of the transistor Q ₇ fluctuates around the level of the base bias V ₁ , as shown in FIG. At this time, when a switching control signal V ₃ as shown in FIG. 4 is supplied through terminal 3, both transistors Q 7 and Q ₁₀ become conductive during a period of V ₃ <V ₁ , and the transistors Q ₇ and Q 10 become conductive. Both _Q8 and _Q9 become non-conductive. As a result, transistor _Q11 and
The respective base voltages V _B11 and V _B12 of Q ₁₂ are
Ignoring each base current, V _B11 = V ₁ + V _io −V _BE7 V _B12 = V ₁ − V _BE10 , and each emitter voltage V _E11 and V _E12
V _E11 = V ₁ + V _io −V _BE7 − V _BE11 V _E12 = V ₁ − V _BE10 − V _BE12 . Here, V _BE(N) is each transistor (N)
is the base-emitter voltage of . Now, the emitter currents of transistors Q ₁₁ and Q ₁₂ are respectively
Let I _O11 and I _O12 be I _R10 and the current flowing from the emitter of transistor Q ₁₁ to the emitter of transistor Q ₁₂ through resistor R ₁₀ , then transistor Q ₁₁ ,
The respective collector currents I _C11 and I _C12 of _Q12 are expressed as I _C11 = I _E11 = I _O11 + I _R10 I _C12 = I _E12 = I _O12 - I _R10 . Again, each transistor Q ₁₁ ,
Assume that the current amplification factor (h _FE ) of Q ₁₂ is sufficiently large and each base current can be ignored. transistor
Since Q ₁₃ and Q ₁₄ are current mirror-coupled _, the collector currents I _C13 and I C14 of both transistors Q ₁₃ and Q ₁₄ are equal, and I _C13 = I _C14 (that is, current ratio: 1),
This also means that I _C14 = I _C11 . Further, assuming that there is a current flowing through the resistor _R11 , and this is I _R11 , it is expressed as I _R11 = I _C14 - I _C12 = I _C11 - I _C12 = I _O11 - I _O12 +2 I _R10 ...4. As mentioned earlier, the current I _R10 flowing through the resistor R ₁₀ is generated by the difference between the emitter voltage V _E11 of the transistor Q ₁₁ and the emitter voltage V _E12 of the transistor Q ₁₂ , so I _R10 = It can also be expressed as V _E11 −V _E12 /R ₁₀ =V _io −V _BE7 −V _B11 +V _BE10 +V _BE12 /R ₁₀ .

Now, the output voltage V _put appearing at output signal terminal 2
is V _put = V ₅ + I _R11・R ₁₁ . Therefore, I _R11 in the right-hand side expression of V _put above
Substituting equation 4 into , V _put = V ₅ + R ₁₁ (I _O11 − I _O12 ) + 2R ₁₁ /R ₁₀ (V _io − V _BE7 − V _BE11 + V _BE10 + V _BE12 )...5. The DC level of the output voltage V _put is obtained by setting the input signal component V _io to zero from equation 5, and V _put (DC) = V ₅ + R ₁₁ (I _O11 − I _O12 ) +2R ₁₁ /R ₁₀ (V _BE10 +V _BE12 −V _BE7 −V _BE11 ) ...6. In other words, the output signal fluctuates by R ₁₁ /R ₁₀ times the input signal V _io around the DC level of equation 6.

Next, looking at the period when V ₃ /V ₁ , that is, the switching control signal V ₃ is greater than the base bias voltage V ₁ of the input transistors Q ₇ and Q ₁₀ , the transistors Q ₇ and Q ₁₀ become non-conductive. Transistors Q ₈ and Q ₉ become conductive. As a result, the respective base voltages V _B11 and V _B12 of the transistors Q ₁₁ and Q ₁₂ become V _B11 = V ₃ − V _BE8 V _B12 = V ₃ − V _BE9 , and the respective emitter voltages V _E11 and V _E12
V _E11 = V ₃ −V _BE8 −V _BE11 V _E12 = V ₃ −V _BE9 −V _BE12 . Below, according to the circuit operating state, the voltage and current at each point are analyzed in the same manner as in the case of V ₃ < V ₁ described above, and the output voltage V _put in this case is V _put = V ₅ + R ₁₁ ( I _O11 −I _O12 )+2R ₁₁ /R ₁₀ (V _BE9 +V _BE12 −V _BE8 −V _BE11 )...7, and during this time, the transmission of the input signal V _io is cut off. The waveform diagrams in FIG. 4 and the same show the emitter voltage V _E11 of the transistor Q ₁₁ , the emitter voltage V _E12 of the transistor Q ₁₂ , and the operating voltages of the output terminal 2.

Now, the gate offset voltage in the embodiment circuit of FIG. 3 is given by the difference between the above equations 6 and 7, and the difference voltage ΔV _put is ΔV _put = 2R ₁₁ /R ₁₀ (V _BE10 + V _BE8 −V _BE9 −V _BE7 ) ...8. As shown by this result, the cause of the gate offset voltage in the circuit of this example is the four transistors Q ₇ , Q ₈ , Q ₉ , and
More specifically, it can be seen that the variation in V _BE of Q ₁₀ is limited to the range of the difference between the base-emitter voltages of the paired transistors Q ₇ and Q ₈ and the paired transistors Q ₉ and Q ₁₀ . Here, the formula 8
The gain expressed as 2R ₁₁ /R ₁₀ and the three formulas of the conventional example
Assuming that the gains represented by R ₅ /R ₄ are equal and the relative error of the base-emitter voltage V _BE is ±2 mV, the variation in (V _BE10 + V _BE8 − V _BE9 − V _BE7 ) is root averaged. It becomes ±3mV. That is, the gate offset voltage of the circuit of this embodiment is about 1/10 that of the conventional example, and is advantageous in terms of gate offset voltage compared to the conventional example. Generally, in integrated circuits, the variation in V _BE of each transistor within the same chip is within a few mV at most, and in particular, the difference in V _BE between paired transistors formed geometrically adjacent is minute. Therefore, with the circuit configuration of this embodiment, it is possible to suppress the gate offset voltage to a minute range.

In addition, in the example circuit shown in Figure 3, as can be seen from equation 5, the output advancing voltage V _put and the input signal voltage
It is in phase with V _io . Therefore, when it is desired to obtain an input signal and an output signal in phase, the circuit shown in FIG. 3 is convenient. Note that if you want to obtain an input signal and an output signal with opposite phases, you can change the DC output level by moving input signal terminal 1 and coupling capacitor C ₁ to the base electrode side of transistor Q ₁₀ in the circuit shown in Figure 3. Therefore, the gate offset voltage remains the same and only the phase can be reversed.

Effects of the Invention As detailed above, according to the present invention, the operation can be switched while applying a common potential to both ends of the differential input, both when an input signal is applied and when the input signal is cut off. The gate offset voltage when cutting off the signal can be suppressed to the same level as the relative variation in the voltage between the base and emitter of the transistor, and by using an IC, a signal cutting circuit with an even smaller gate offset voltage has been realized. can.

[Brief explanation of the drawing]

FIG. 1 is a diagram of a conventional signal cutoff circuit, FIG. 2 is a timing diagram of its operation, FIG. 3 is a diagram of a signal cutoff circuit according to an embodiment of the present invention, and FIG. 4 is a timing diagram of its operation. 1...Input signal terminal, 2...Output signal terminal, 3
...Switching control terminal, 4...Circuit power supply (V _CC ) terminal, Q ₁ to Q ₁₆ ... Transistor, R ₁ to
_R11 ...Resistor, _C1 ...Coupling capacitor, _V1 , _V2 ,
V ₄ , V ₅ ...Base bias.

Claims (1)

[Scope of Claims] 1: a first transistor pair in which the emitters of the first and second transistors are commonly connected; a second transistor pair in which the emitters of the third and fourth transistors are commonly connected; a fifth transistor whose emitter is connected to the base thereof; and a fifth transistor whose emitter is connected to the emitter of the fifth transistor through the first resistor and whose base is connected to the emitter of the fourth transistor. and a current mirror circuit that mirror-inverts the collector current of the fifth transistor and supplies the mirror-inverted current to the collector of the sixth transistor. a dynamic amplification circuit; and a second resistor connected between the collector of the sixth transistor and a predetermined potential point, applying a switching control signal to the bases of the second and third transistors; 1. Applying the same bias potential to the base of the fourth transistor,
A signal cutoff circuit characterized in that an input signal is applied to the base of the first or fourth transistor.