JPH0580071B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a detection circuit for a synchronization signal of digital data.

[Summary of the invention]

The present invention prevents erroneous detection of a synchronization signal by also utilizing a preamble section in a detection circuit that detects a synchronization signal from channel data.

[Conventional technology]

A video floppy disk for electronic still cameras is being considered as a small floppy disk (Reference: Nihon Keizai Shimbun, morning edition, June 1, 1980).

That is, in FIG. 3, 1 indicates the video floppy as a whole, and 2 indicates the rotating magnetic disk. This disk 2 has a diameter of 47mm and a thickness of
It has a size of 40 μm, and at its center is provided a center core 3 into which a spindle of a drive mechanism (not shown) is fitted, and the core 3 is provided to provide a reference angular position when the disk 2 rotates. A magnetic piece 4 is provided.

And 5 is the storage jacket, which is 60
The size is 54 x 3.6 mm, and there are 2 disks.
is rotatably housed, and the core 3 and magnetic piece 4 are exposed through the central opening 5A of the jacket 5. Furthermore, the jacket 5 has an opening 5B for when the magnetic head comes into contact with the disk 2.
This opening 5B is covered with a sliding dustproof shutter 6 when the disk 1 is not in use. Further, numeral 7 is a counter dial that displays the number of images that have been taken, and numeral 8 is a claw for preventing erroneous recording, and the claw 8 is removed when recording is prohibited.

Fifty magnetic tracks can be formed concentrically on one side of the disk 2, with the outermost track being the first track and the innermost track being the 50th track. Note that the width of the track is 60 μm and the width of the guard band is 40 μm.

During image capture, disk 2 rotates at 3600 rpm.
(field frequency) and rotated at
One field of video signal is still recorded as one magnetic track. In this case, the recorded signal is as shown in FIG.
FM signal in which white peak is converted to 7.5MHz FM signal Sf and FM modulated by red color difference signal
Sr (center frequency 1.2MHz) and blue color difference signal
FM modulated FM signal Sb (center frequency 1.3MHz)
A line sequential signal Sc is formed, and a sum signal Sa of this FM color signal Sc and FM luminance signal Sf is recorded.

Thus, the video floppy 1 has an appropriate size, function, and characteristics as a recording medium for video signals.

Furthermore, it is also contemplated that the video floppy 1 may be used as a storage medium for digital data.

That is, FIG. 5 shows the physical format when recording and reproducing digital data on the video floppy 1. And in the same figure A and B,
TRCK indicates an arbitrary track on the magnetic disk 2, and this track TRCK first has a gap section of 2° in the length direction with the magnetic piece 4 as a reference.
A GAP2 and a 2° index section INDX are provided, and the remaining section is equally divided into four 89° sections, and each of the divided sections is called a sector SECT. Note that the sector SECT immediately after the magnetic piece 4 is the 0th sector, and the sectors are the 1st, 2nd, and 3rd sectors in that order. Furthermore, when accessing the data of the host device to the floppy disk 1, the access is performed in units of one sector SECT. Furthermore, the index section INDX corresponds to approximately 3 frame sections FRAM of data, which will be described later, and Tmax of the digital signal.
The signal "1000" is repeated over the entire section.

Then, as shown in Figure C, the sector SECT
The section of 2 degrees from the starting end is set as a gap section CAP1 for obtaining a margin during read/write, and the rest is divided into 131 equal parts. Each of these equally divided sections contains 44 channel bytes (one channel byte is a unit of signal formed by a predetermined conversion described later, and corresponds to 1 byte of source data, and 10 bits in 8-10 conversion). ) is recorded and played back. The first two equally divided sections are the preamble section PRAM, and this preamble section PRAM contains, for example, the source data.
“0101010101” corresponding to 00H (H indicates hex value)
This signal is repeatedly provided and is used to pull in the PLL during playback.

Furthermore, 128 sections following this section PRAM are sections in which signals called frame FRAM are recorded and reproduced. Also, the last section is a postamble section that is equivalent to the preamble section PRAM.
Considered to be PSAM.

Then, as shown in figure D, one frame
FRAM sequentially receives one channel byte synchronization signal SYNC (“0100010001” or “1100010001”) and frame address signal FADR.
, undefined signal FRSV, and check signal FCRC
and further 32 symbols (1 symbol = 1 channel byte) of data DATA, and 4 symbols each of first and second redundant data PRT1, PRT.
2. In this case, check signal FCRC
is the CRCC for the frame address signal FADR and the signal FRSV. Also, the data DATA is
Although this is original digital data that is accessed by the host device, this data DATA has been interleaved to be completed within the digital data of one sector SECT, and is redundant data PRT.
1, PRT2 is for one sector (32 symbols x
This is parity data generated using the Reed-Solomon encoding method with a minimum distance of 5 for digital data of 128 frames.

Therefore, one sector SECT, track
The capacity of digital data in TRAM and floppy disk 1 is as follows: 1 sector: 4096 bytes (= 16 symbols x 2 x 128 frames) 1 track: 16 KB (= 4096 bytes x 4 blocks) 1 floppy: 800 KB (when one side is used) ( 16K bytes x 50 tracks).

Note that when accessing digital data on floppy disk 1, access is performed in units of one sector SECT, so floppy disk 1
Access to digital data is in units of 4K bytes.

Also, one frame FRAM and sector
The number of SECT bits is as follows: 1 frame: 352 source bits (= 4 x 8 source bits + (32 + 4 symbols) x 8 source bits) 1 sector (excluding gap section GAP1): 46112 source bits (= 352 bits x (128 + 3 frames)) In reality, when recording and reproducing digital signals on floppy disk 1, it is required that DSV is small, Tmin/Tmax is small, and Tw is large, so all the digital signals mentioned above are After the 8-10 conversion is performed, the data is recorded on the floppy disk 1, and during playback, the inverse conversion is performed before the original signal processing is performed.

Therefore, in the case of the above data density, the actual number of bits in floppy 1 is multiplied by 10/8, and becomes 1 frame: 440 channel bits, 1 sector (excluding gap section GAP 1): 57640 channel bits. Also, as a result, the entire section of one sector corresponds to 58,965 channel bits (57,640 channel bits x 89°/87°) (actually, the length of each section is assigned from this number of channel bits as described above. (so the total length of the frame section is slightly less than 87°).

Therefore, a digital signal (8-10
The bit rate when accessing the converted signal is 14.31 Mbit/s (58965 bits x 4 blocks x field frequency x 360°/356°), and 1 bit is 69.9ns (1/14.3 Mbit). corresponds to

Note that it is permitted to mix video signals and digital data on one floppy disk 1 in units of tracks.

Thus, according to this format, one 2-inch video floppy can accommodate one side of the video floppy.
It has a read line for 800K bytes of digital data, which is more than twice the typical capacity of a conventional 5-inch floppy disk (320K bytes), and has a large capacity despite its small size.

In addition, since the rotation speed of the disk 2 is the same as that of the video signal, it is possible to record and reproduce a mixture of the video signal and digital data, in which case,
The frequency spectra of both signals recorded and reproduced on the disk 2 are similar, and recording and reproduction can be performed under conditions suitable for electromagnetic conversion characteristics, head contact, etc. Furthermore, even when recording and reproducing two signals together, there is no need to switch the rotation speed of disk 2, so there is no need to consider the time required to switch the servo, and the two signals can be used immediately. . Furthermore, since the number of revolutions is the same and the mechanism such as the electromagnetic conversion system has the same characteristics or functions, it is also advantageous in terms of cost.

In this manner, the video floppy 1 has new effects as a medium for recording and reproducing video signals, for storing digital data, and further as a medium that can record and reproduce a mixture of video signals and digital data.

[Problem that the invention seeks to solve]

When extracting source data from floppy 1 mentioned above, the channel data is divided into 10 bits based on the position of the synchronization signal SYNC, and the divided channel data is decoded into the original source data by 10-8 conversion. There is. Therefore, if the synchronization signal SYNC is mistakenly detected at an inappropriate position, the delimiter of the subsequent channel data will be shifted, resulting in a bit slip, and it will not be possible until the next correct synchronization signal SYNC is detected. , resulting in errors in the source data. In this case, if the synchronization signal SYNC is far away from the source data, the probability of such an error occurring is small, but when the transmission band is compressed as described above, the distance is as short as 1 bit. , Therefore, the probability of occurrence of that error is high. If many such errors occur, they can no longer be corrected using the parity data PRT1 and PRT2.

In view of these points, the present invention aims to reduce the probability of erroneously detecting the synchronization signal SYNC to a negligible level.

[Means for solving problems]

The present invention detects a synchronization signal by also utilizing a preamble section.

[Effect]

Erroneous detection of synchronization signals is almost eliminated.

〔Example〕

First, let us explain the format corresponding to this invention.

In this format, the format of the track TRCK is the same as the conventional one, as shown in FIGS. 2A and 2B.

Then, as shown in C of the same figure, the sector SECT is
The 2° section from the starting point is defined as the gap section CAP1, and the remaining section is divided into 131 equal parts.
This preamble section is defined as the preamble section PRAM, and this preamble section contains, for example, source data.
A signal "1111111111" corresponding to EBH is repeatedly provided and is used to pull in the PLL during playback.

Furthermore, the section following this preamble section PRAM is defined as a sector synchronization signal section S-SYNC.

As shown in Figure D, the sector synchronization signal section S-SYNC is divided into 11 equal parts, each of which has four channel bytes recorded and reproduced, and the synchronization signal SYNC is repeatedly provided in the first two channel bytes. Furthermore, a frame preview signal FRNT which is incremented by 1 from F5H to FFH of the source data is provided in the next channel byte, and its parity signal PRTY is provided in the last channel byte.

Furthermore, 128 frames FRAM are provided in the section following this sector synchronization section S-SYNC, and the last postamble section PSAM
Similarly to the preamble section PRAM, a signal "1111111111" corresponding to the EBH of the source data is repeatedly provided.

Then, as shown in figure E, one frame
From the beginning, FRAM repeats the synchronization signal SYNC of 2 channel bytes, the frame address signal FADR of 1 channel byte, the check signal FCRC of 1 channel byte, and 32
Symbol data DATA and 4-symbol first and second redundant data PRT1 and PRT2, respectively.
and has. In this case, the frame address signal
FADR is 1 channel byte, and the source data is 1 byte, and as mentioned above, the number of frame FRAMs in 1 sector SECT is 128, so 7 bits are sufficient for the frame address, and the remaining, for example, MSB
is used to record other information. Also, check signal FCRC is CRCC for frame address signal FADR. Further, data DATA and redundant data PRT1 and PRT2 are the same as in the conventional case.

Therefore, in this format, it is possible to perform recording and reproduction with exactly the same storage capacity as in the above-mentioned conventional format.

Next, an example of this invention will be explained.

In FIG. 1, a disk 2 of a floppy disk 1 is rotated at a rate of 60 times per second by a motor (not shown), and a magnetic head 11 of a target track TRCK of the disk 2 is brought into contact with the magnetic head 11 of the target track TRCK. TRCK channel data
CHND is reproduced, and this data CHND is supplied to the first synchronization pattern detection circuit 13 through the reproduction amplifier 12.

This detection circuit 13 compares a 10-bit serial input, serial and parallel output shift register to which data CHND is supplied, and the parallel output of this register with the pattern of the regular synchronization signal SYNC, and when the two match. Therefore, when the synchronization signal SYNC is correctly reproduced, the output of this detection circuit 13 becomes "1".

Then, this detection output is supplied to the AND circuit 15, and the serial output of the shift register of the detection circuit 13 is supplied to the detection circuit 14 of a similar second synchronization pattern, and this detection output is supplied to the AND circuit 1.
5. Therefore, when two synchronizing signals SYNC are reproduced correctly in a row, AND circuit 1
The output _P15 of 5 becomes "1".

Furthermore, the data CHND from amplifier 12 is
A channel clock φ is supplied to the PLL 16 and bit-synchronized with the data CHND, and this clock φ is supplied as a count input to a 10-bit counter 17, and an AND output _P15 is supplied to the counter 17 as a reset input. be done. Then, the carry output and AND output of counter 17
_P15 is taken out through the OR circuit 18.

Therefore, a carry output is obtained from the counter 17 every 10 bits of the channel clock φ, and at this time, the counter 17 receives the synchronization signal.
Every time two SYNCs occur, it is reset by the AND output _P15 and counting starts from that reset point, so the OR output of the OR circuit 18
_P18 is obtained every 10 bits from the synchronization signal SYNC by counting the channel clock φ.
In other words, this OR output P ₁₈ is the channel data
This is a synchronization signal that indicates the division of CHND every 10 bits. Note that 10 bits of channel data CHND corresponds to 8 bits of source data, and therefore, OR output _P18 is also a signal indicating the delimitation of this source data, so from now on, this OR output
_P18 is called the byte synchronization signal.

Furthermore, channel data CHND is taken out in series from a predetermined stage of the shift register of the detection circuit 14, and this data CHND is supplied to a 10-bit serial input parallel output shift register 21, and a clock φ is supplied to the register 21. The data CHND is taken out in parallel from the register 21 in 10 bits at a time, and this data CHND is supplied to the latch 22, and the byte synchronization signal
_P18 is supplied to the latch 22 as a latch enable input, and when the data CHND is correctly divided into 10 bits, it is latched to the latch 22, and this latched data CHND is supplied to the decoder 23 and converted into 8-bit source data SRCD. Decoded (10-8 conversion). And this data
The SRCD is once latched in the latch 24 by the synchronization signal _P18 and then taken out as a read output.

Thus, according to the invention, source data
SRCD is read. In this case, especially according to the present invention, when the synchronization signal SYNC is obtained in the preamble section at the beginning of the sector SECT, the channel data is synchronized with the synchronization signal SYNC.
Since a byte synchronization signal _P18 is obtained for every 10 bits of CHND, the synchronization signal at the beginning of the frame FRAM is
Even if SYNC is not obtained, no error occurs in the byte synchronization signal _P18 . Also, at the beginning of the sector SECT, two synchronization signals SYNC are repeated 11 times, so even if there is an error in a part of this synchronization signal SYNC, the byte synchronization signal P ₁₈ can be obtained. Even if there is an error in all 11 synchronization signals SYNC, the byte synchronization signal _P18 can be obtained by the synchronization signal SYNC at the beginning of the frame FRAM. Furthermore, the synchronization signal of the preamble section
Since SYNC is also used, the original data processing can be performed immediately from the starting position of valid data.

Note that in the above description, the source data SRCD is 8-10 converted and recorded on floppy disk 1, but the run length is limited and the data is m-n converted (m<n). The present invention can be applied to any case where a preamble section at the head of a data packet sequentially includes a bit synchronization signal and an n-bit synchronization signal.

〔Effect of the invention〕

According to this invention, when the synchronization signal SYNC is obtained in the preamble section at the beginning of the sector SECT, the channel data is synchronized with the synchronization signal SYNC.
Since a byte synchronization signal _P18 is obtained for every 10 bits of CHND, the synchronization signal at the beginning of the frame FRAM is
Even if SYNC is not obtained, no error occurs in the byte synchronization signal _P18 . In addition, since the synchronization signal SYNC of two each is repeated 11 times at the beginning of the sector SECT, even if there is an error in a part of this synchronization signal SYNC, the byte synchronization signal P ₁₈ can be obtained. Even if there is an error in all 11 synchronization signals SYNC, the synchronization signal at the beginning of the frame FRAM
Byte synchronization signal _P18 can be obtained by SYNC. Furthermore, the preamble section synchronization signal SYNC
Since the data is also used, the original data processing can be performed immediately from the starting position of valid data.

[Brief explanation of the drawing]

FIG. 1 is a system diagram of an example of the present invention, and FIGS. 2 to 5 are diagrams for explaining the same. 1 is a video floppy, 13 and 14 are detection circuits, 17 is a counter, 21 is a shift register, 2
3 is a decoder.

Claims (1)

[Claims] 1 The run length is limited, and the source data is subjected to m-n conversion (m
The above source data is decoded from a signal that has been converted into n-bit channel data by <n) and has a bit synchronization signal and an n-bit synchronization signal sequentially in the preamble section at the head of this channel data. In this case, the signal for bit synchronization in the preamble part is
This channel clock is supplied to the PLL to form a channel clock, this channel clock is supplied as a count input to an n-bit counter, the pattern of the n-bit synchronization signal in the preamble section is detected, and this detection output is used as described above. A detection circuit for a synchronization signal, which is supplied as a reset input to a counter, and takes out a carry output of the counter as a synchronization signal indicating a division of n bits of the channel data.