JPH0580078B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a still image recording and reproducing apparatus in which one still image is recorded and reproduced on a magnetic tape in units of a plurality of inclined tracks.

[Conventional technology]

Conventional video VTRs (video tape recorders) record a time code corresponding to one frame and are used for editing, etc. However, with this time code alone, editing accuracy cannot be compensated for ±0 frames. First, VITC (Vertical Interval Time Code) is used.

[Problem that the invention seeks to solve]

In a still image recording and reproducing device in which a single still image is recorded and reproduced on a magnetic tape in units of multiple inclined tracks, missing even a single track is not allowed, so the conventional method described above does not provide sufficient editing accuracy. It's difficult. Therefore, in the present invention,
The present invention is intended to enable sufficient editing accuracy to be obtained with such a still image recording and reproducing device.

[Means for solving problems]

In order to solve the above-mentioned problems, the present invention is configured such that recording or playback is delayed by a predetermined time from the end of the synchronization signal recorded on the address track and started in synchronization with the position signal of the rotating magnetic head. be.

For example, in FIG. 1, reference numeral 1 denotes a magnetic tape, which is run diagonally along a tape guide drum 2 over an angular range of, for example, 180°, at a predetermined speed. Furthermore, 3A and 3B are rotating magnetic heads, which are arranged at an angular interval of 180° and rotated at a predetermined speed. In this case, still images are recorded and reproduced on the magnetic tape 1 in units of a plurality of inclined tracks. A fixed magnetic head 4 records and reproduces the synchronizing signal SYNC and address data ADDATA in the longitudinal direction of the magnetic tape 1 in units of the plurality of inclined tracks. This magnetic head 4 receives a synchronizing signal from the system control circuit 5.
SYNC and address data ADDATA are supplied and recorded, and the synchronization signal SYNC and address data ADDATA reproduced by this magnetic head 4
is supplied to the system control circuit 5.

[Effect]

In the above configuration, the synchronization signal SYNC and address data reproduced by the magnetic heads 3A and 3B
By supplying ADDATA to the system control circuit 5, recording and playback can be performed using the synchronization signal
It is delayed by a predetermined time from the end of SYNC and starts in synchronization with the position signals of the magnetic heads 3A and 3B. Therefore, sufficient editing accuracy can be obtained.

〔Example〕

Embodiments of the present invention will be described below with reference to FIG. 2 and subsequent figures.

FIG. 2 is a block diagram showing the entire apparatus of this example. In the figure, red, green and blue signals S _R , S _G and S _B are supplied to the matrix circuit 7 from terminals 6R, 6G and 6B, respectively. A luminance signal Y, a red difference signal R-Y, and a blue difference signal B-Y are obtained from the matrix circuit 7, and these signals are converted into digital signals by an A/D converter 8 and then sent to the first image memory. 9, and one frame worth of data is written into this image memory 9.

Moreover, the signal written to the image memory 9 is
After being encoded, modulated, etc. by the CPU 10, it is supplied to the second image memory 11 and written therein. The 8-bit signal read from the second image memory 11 is converted into a 10-bit signal by an 8/10 conversion circuit 12. This 10-bit signal is parallel/
After being converted into a serial signal by the serial conversion circuit 13, it is supplied to the rotating magnetic heads 3A and 3B via the recording amplifier 14 and the recording side R of the recording/reproducing switch 15.

The magnetic heads 3A and 3B are arranged with an angular spacing of 180° from each other and are rotated at a predetermined speed.

Further, 1 is a magnetic tape, and this magnetic tape 1 is run diagonally along a tape guide drum 2 over an angular range of about 180 degrees at a predetermined speed.

Here, the rotating magnetic head 3 moves over the magnetic tape 1.
A and 3B are scanned alternately, and signals for one frame are recorded on the magnetic tape 1 in units of a plurality of inclined tracks 1A, for example, 60 tracks, as shown in FIG. In this case, a synchronization signal SYNC and address data are provided in advance in the longitudinal direction of the magnetic tape 1.
Address track TA where ADDATA etc. are recorded
is formed, and recording is delayed by a predetermined time from the end of the synchronizing signal SYNC, and recording is started in synchronization with the position signals of the rotating magnetic heads 3A, 3B. In FIG. 3, TC is a control track on which a control signal CTL corresponding to each track of the inclined track 1A is recorded.

Also, during reproduction, the rotating magnetic heads 3A and 3B
The plurality of inclined tracks 1A formed as described above are alternately scanned, and signals for one frame are sequentially obtained. This signal is supplied to the equalizer 17 via the playback side P of the recording/playback switch 15 and the playback amplifier 16, and is waveform-equalized. In this case, reproduction is also delayed by a predetermined time from the end of the synchronizing signal SYNC recorded in the address track TA, and is started in synchronization with the position signals of the rotating magnetic heads 3A, 3B.

The waveform-equalized signal is converted into a parallel signal by the serial/parallel conversion circuit 18, and then
The signal is converted into an 8-bit signal by the conversion circuit 19, and then supplied to the second image memory 11 and written therein. The signal written to this second image memory 11 is
After processing such as demodulation and decoding by 10, it is supplied to the first image memory 9 and written therein.

From this first image memory 9, luminance signals Y,
The red difference signal R-Y and the blue difference signal B-Y are sequentially read out for one frame, and these signals are converted into analog signals by the D/A converter 20 and then supplied to the dematrix circuit 21. And terminal 22
R, 22G and 22B have one frame of red,
Green and blue signals S _R , S _G and S _B are obtained.

In addition, the signal waveform-equalized by the equalizer 17 is
The signal is supplied to a PLL circuit 23, from which a reproduced clock signal CK is obtained.

Further, in FIG. 2, 5 is a system control circuit, and access, recording, reproduction, etc. are controlled by this system control circuit 5. Further, 24 is a servo circuit, and under the control of the system control circuit 5, servo of the drum, capstan, reel, and tracking is performed. Further, 25 is a key device, and control of the system control circuit 5 is performed based on the user's operation on this key device 25.

In addition, 4 is the synchronization signal SYNC, as described above.
Address track the address data ADDATA
This is a fixed magnetic head that records on and plays back from the TA, and this magnetic head 4 is equipped with a system control circuit 5.
More synchronization signal SYNC, address data ADDATA
At the same time, the signal obtained from the magnetic head 4 is supplied to the system control circuit 5.

A fixed magnetic head 26 records and reproduces the control signal CTL on the control track TC, and the magnetic head 26 receives the control signal CTL from the system control circuit 5.
At the same time, the signal obtained from the magnetic head 26 is supplied to the system control circuit 5.

Next, how address tracks TA and control tracks TC are formed in the longitudinal direction of the magnetic tape 1 before recording will be described with reference to FIG.

In the figure, 27 is a CPU that constitutes the system control circuit 5. For example, 14-bit address data ADDATA is sent from this CPU 27.
is supplied to the latch circuit 29 via the input/output port 28 and latched. The latched address data ADDATA is then converted into a serial signal and supplied to the multiplexer 32.

Also, 33 is a 60Hz control signal, for example.
This control signal CTL is supplied to the magnetic head 26 via the recording amplifier 34 to form a control track TC on the magnetic tape 1. The control signal CTL is also supplied to a PLL circuit 35 consisting of a phase comparator 35a, a low-pass filter 35b, a 1/4 frequency divider 35c, and a voltage-controlled variable frequency oscillator 35d, and the output of this PLL circuit 35 is 1/2. As shown in FIG. 5B, a signal having twice the frequency of the control signal CTL is obtained via the frequency divider 36 and is supplied to the latch circuit 29 and multiplexer 32 as an address clock signal. Ru. In addition, the multiplexer 32
Data SDATA, such as tape status, is supplied from the terminal 32a. Then, the multiplexer 32 is connected from the CPU 27 to the input/output port 30.
A trigger signal ST for switching control is supplied to
From this multiplexer 32, a signal as shown in FIG. 6 is obtained. That is, the SYNC part where the synchronization signal SYNC exists, the DATA part where address data ADDATA exists, the USER part where data SDATA such as tape status exists, and the address data.
There is data with the LSB and MSB of ADDATA in reverse order. - It consists of the DATA section. SYNC
The signal is assumed to be high level for 15 consecutive clocks. The reason why the SYNC section is configured this way is that even if address data ADDATA cannot be read accurately during high-speed search, which will be described later, the synchronization signal
This is to enable counting of SYNC. In this case, the length from the end of the synchronizing signal SYNC to the beginning of the next synchronizing signal SYNC is made to correspond to a plurality of slope tracks to be formed later, 60 tracks in this example. In this case, as shown in FIG. 5, the address data ADDATA (shown in C of the same figure) is replaced by the control signal CTL (shown in A of the same figure).
The phase is shifted by 90° from the This is to advantageously reproduce the address data ADDATA using both edges of the reproduction control signal CTL.

The trigger signal S _T is delayed by the delay circuit 31 and then supplied to the latch circuit 29 as a latch pulse.

The signal obtained from the multiplexer 32 is supplied to the magnetic head 4 via the recording amplifier 37, and an address track TA is formed on the magnetic tape 1.

Next, the address track TA and control track TC are placed in the longitudinal direction of the magnetic tape 1 in this way.
How recording and reproduction are performed after the data is formed will be described with reference to FIG.

In the figure, 38 is a demultiplexer, to which a signal reproduced by the magnetic head 4 from the address track TA is supplied via a reproduction amplifier 39, and a control signal CTL reproduced by the magnetic head 26 from the control track TC is supplied. It is supplied as a clock signal via a reproducing amplifier 40. Address data ADDATA obtained from the demultiplexer 38 is demodulated by an address demodulation circuit 41 and then supplied to the CPU 27 via an input/output port 42. Further, the synchronization signal SYNC obtained from the demultiplexer 38 is demodulated by the synchronization demodulation circuit 43 and then supplied to the CPU 27 via the input/output port 44 and is also supplied to the CPU 27 as an interrupt signal.

During recording or reproduction, when a target address TA is given by the key device 25 (see FIG. 2), the tape speed is increased and a high-speed search (access) to the target address TA is performed. At this time, the address output data DATA is determined based on the flowchart shown in FIG.

First, when the synchronization signal SYNC is detected, the counter is incremented or decremented depending on the running direction of the magnetic tape 1. Next, the address data ADDATA is read by the address data ADDATA reading routine and compared with the value of the counter described above. If they match, address data ADDATA becomes output data.
It is considered as DATA.

On the other hand, if they do not match, they are processed by a data processing routine. This data processing routine is the ninth
The address data is configured as shown in the figure.
The causality of ADDATA can be investigated. That is, it is checked whether the magnetic tape 1 is incremented or decremented by 1 in the traveling direction of the magnetic tape 1. If it is done correctly, the address data ADDATA is judged to be correct, and the value is set as the output data DATA and the counter value is set at the same time.
COUNT can also be replaced. In other cases, the counter value COUNT is used as the output data DATA. For example, the relationship between the counter value COUNT, address data ADDATA, and output data DATA is as follows:
The result is as shown in FIG.

The running position is determined based on this output data DATA, and the starting point of recording or reproduction is determined based on this. This starting point is determined based on the flowchart shown in FIG.

First, it is determined whether the output data DATA matches the target address TA. If they match,
A rising edge of the synchronizing signal SYNC is detected, and then a falling edge of the synchronizing signal SYNC is detected. Next, a trigger pulse P _T (shown in FIG. 12D) is generated after a certain period of time has elapsed after the falling edge of the synchronization signal SYNC (shown in FIG. 12A) is detected.

In FIG. 7, a trigger pulse P _T is supplied to a clock terminal CK of a D flip-flop 46 through an input/output port 45. In FIG. A high level signal is supplied to the D terminal of this flip-flop 46, and when a trigger pulse P _T is supplied to the output terminal Q, a high level signal is obtained. The signal obtained at the output terminal Q of this flip-flop 46 is supplied to the D terminal of a D flip-flop 47. Further, a switching pulse _PSW (shown in FIG. 12C) for alternately switching the magnetic heads 3A and 3B is supplied to the terminal 48 via the inverter 49 to the clock terminal CK of the flip-flop 47, and the output terminal Q is supplied with the switching pulse PSW (shown in FIG. 12C). , a signal (shown in FIG. 12E) that goes high at the edge of the second switching pulse P _SW after the fall of the synchronizing signal SYNC is obtained, and this signal is supplied to the CPU 27 via the input/output port 50. Then, the edge of the second switching pulse _PSW after the fall of the synchronizing signal SYNC is taken as the starting point of recording or reproduction. Incidentally, what is shown in FIG. 12B is the reproduction control signal CTL.

In this manner, recording or reproduction is started, and when recording to the plurality of diagonal tracks or reproduction from the plurality of diagonal tracks is completed, the running of the magnetic tape 1 is stopped, and the recording or reproduction is completed. That is, as shown in the flowchart of FIG. 11, after the trigger pulse P _T is generated, the next synchronization signal is
The rising edge of SYNC is detected, then the synchronization signal
The rising edge of SYNC is detected. After the data end is detected, the running of the magnetic tape 1 is stopped. The data end signal is formed as follows. That is, in FIG. 7, the signal obtained at the output terminal Q of the flip-flop 47 is supplied to one input side of an AND circuit 51, and the other input side of this AND circuit 51 is connected to the switching signal obtained at the output terminal Q of the flip-flop 47. A signal obtained by multiplying the pulse P _SW by a multiplier 52 is supplied. In this case, AND circuit 5
From the output side of 61 counter 53, a pulse signal that becomes high level is obtained corresponding to each of a plurality of diagonal tracks, for example 60, from the start point of recording or reproduction, and this pulse signal is applied to the clock terminal of 61 counter 53. Supplied to CK. And this counter 5
The overflow signal S _OF of No. 3 is supplied to the CPU 27 via the inverter 54 and the input/output port 55, and is used as the data end signal.

Also, in Fig. 7, the overflow signal
S _OF is supplied as a reset signal to flip-flops 46 and 47, and flip-flops 46 and 47 are placed in a reset state.

According to this example, the start point of recording or playback is set at the edge of the second switching pulse _PSW after the fall of the synchronization signal SYNC, so that the effects of, for example, jitter on the drum or capstan, etc. are reduced. , the accuracy of recording or reproduction is improved.

In the above-described embodiment, the second edge of the switching pulse _PSW after the fall of the synchronizing signal SYNC is taken as the starting point, but it may be the third or subsequent edge.

〔Effect of the invention〕

As described above, according to the present invention, recording or playback is delayed by a predetermined time from the end of the synchronization signal recorded on the address track and starts in synchronization with the position signal of the rotating magnetic head. The accuracy of editing is improved, and sufficient editing accuracy can be obtained.

[Brief explanation of the drawing]

Fig. 1 is a block diagram for explaining the present invention, Fig. 2 is a block diagram showing an embodiment of the present invention, and Figs.
The figures are for explanation. 1 is a magnetic tape, 3A and 3B are rotating magnetic heads, 4 is a fixed magnetic head, and 5 is a system control circuit.

Claims (1)

[Scope of Claims] 1. A still image recording and reproducing device in which still images are recorded and reproduced on a magnetic tape in units of a plurality of inclined tracks by a rotating magnetic head, wherein still images are recorded in units of the plurality of inclined tracks in the longitudinal direction of the magnetic tape. An address track is formed in which the corresponding synchronization signal and address data are recorded, and during recording and reproduction, first, counting is started when the synchronization signal is detected, and then, as the address data is read, the count is started. Compare it with the count value, and when the count value and the read address data match, output the address data as output data to determine whether it matches the target address. The still image recording and reproducing apparatus is further characterized in that recording and reproducing is started in synchronization with the position signal of the rotating magnetic head after a predetermined delay time has elapsed after detecting the end portion of the synchronization signal. .