JPH0580973A - Normalized rounding device - Google Patents

Abstract

(57) [Summary] (Corrected) [Purpose] Rounding and normalization of operation results are performed at high speed. [Structure] When calculating a quotient, a plurality of partial quotients excluding the finally obtained partial quotient are divided into non-overlapping first intermediate values and second intermediate values, and a partial sum 1 and a first intermediate value are selected. A first selection means 13, a second carry means 14 for selecting a partial carry and a second intermediate value, a rounding position determination means 15 for determining a rounding position by a plurality of partial quotients excluding the partial quotient finally obtained, rounding First and second adding means 16 and 17 with different rounding positions for changing positions and performing addition of two numbers, and third adding means 18 for obtaining the value of the most significant bit of the finally obtained partial quotient, The outputs of the first and second adding means are input with the outputs of the first and second adding means 16 and 17, the output of the third adding means 18 and the plurality of partial quotients 12 excluding the finally obtained partial quotient. Decide which rounding result to select, 16 or 17, and normalize And a normalization rounding means 20 for selecting and normalizing the outputs of the adding means 16 and 17.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a normalization rounding device for rounding and normalizing operation results at high speed.

[0002]

2. Description of the Related Art Recently, a product is calculated by adding a partial sum and a partial carry obtained by a multiplication array, and n partial quotients are sequentially obtained by iterative calculation of multiplication, and finally, these n partial quotients are obtained. There is an arithmetic unit that calculates a quotient by adding quotients. As an arithmetic unit of this kind, Japanese Patent Application No. 1-210
There is a 021 division device. FIG. 3 shows the positional relationship of n partial quotients. In FIG. 3, 51, 52, 53, and 54 are m-bit partial quotients 1, partial quotients 2, partial quotients 3, and partial quotients n, respectively, which are sequentially obtained from partial quotients 1 to n by iterative calculation of multiplication. .. As shown in FIG. 3, the partial quotient i
Has the most significant bit overlapping the least significant bit of the partial quotient i-1.

FIG. 2 is a block diagram showing a conventional normalization rounding device in this type of arithmetic unit.

The operation of the conventional rounding device will be described below with reference to the drawings. In FIG. 2, 3
Reference numerals 1 and 32 denote partial sums and carrys respectively obtained by the multiplication array, 42 denotes a partial quotient storage register for storing n partial quotients, and 43, 44 and 48 select one of two inputs. Selector circuits, 45 and 46 perform rounding by inputting 1 as an initial carry to the rounding position and adder with two different rounding positions for adding two numbers. 47 selects one of the rounded results obtained by different rounding. A normalization rounding determination circuit that determines whether to perform normalization and normalization, 49 is a normalization circuit that performs normalization, and 33 is a calculation result.

The selection circuits 43 and 44 output a partial sum 31 and a partial carry 32, respectively, when calculating a product and when calculating n partial quotients by iterative calculation of multiplication, and calculate n partial quotients. Then, when calculating the quotient, the n partial quotients are divided into a first intermediate value and a second intermediate value that do not overlap, and the first intermediate value and the second intermediate value are output, respectively. Adder 45,
46 receives the outputs of the selection circuits 43 and 44 as input, and when calculating a product, performs rounding in two ways when carry occurs and when carry does not occur, and adds two numbers. Also, when calculating the quotient, rounding is performed in two ways when there is no digit loss and when there is a digit loss.
Add numbers. When calculating n partial quotients by iterative calculation of multiplication, the adder 46 uses the partial sum 31 and the partial carry 32.
Is input, the partial quotient is obtained by adding two numbers without rounding, and the partial quotients are sequentially stored in the partial quotient storage register. The normalization rounding determination circuit 47 receives the upper bits of the outputs of the adders 45 and 46 as an input, whether a carry occurs when calculating a product, whether a carry occurs when calculating a quotient, and Determine whether or not. The selection circuit 48 receives the outputs of the adders 45 and 46 as input, and selects one of the two rounding results by the output of the normalized rounding determination circuit 47. The normalization circuit receives the output of the selection circuit as an input, performs normalization by the output of the normalization rounding determination circuit 47, and outputs a calculation result 33.

[0006]

However, in the normalization rounding device having the above-described structure, when calculating the quotient, rounding and normalization are performed after all n partial quotients have been obtained. There was a problem that it took time.

In view of the above point, the present invention has an object to provide a normalization rounding device for rounding and normalizing an operation result at high speed.

[0008]

The normalization rounding device of the present invention divides a plurality of partial quotients excluding the finally obtained partial quotient into a first intermediate value and a second intermediate value which do not overlap each other and partially sums them. And a first selecting means for selecting a first intermediate value, a second selecting means for selecting a partial carry and a second intermediate value, and a rounding position by a plurality of partial quotients excluding the finally obtained partial quotient. The rounding position determining means for determining, and the output of the first selecting means and the output of the second selecting means are used as inputs, rounding is performed by changing the rounding position, and addition of two numbers is performed at different rounding positions. 2 adding means, 3rd adding means for obtaining the value of the most significant bit of the partial quotient finally obtained by inputting the partial sum and the partial carry, the output of the 1st adding means and the output of the 2nd adding means And an output of the third adding means and a plurality of partial quotients excluding the finally obtained partial quotient The output of the first adding means and the output of the second adding means determines which rounding result is to be selected and which is to be normalized. The output of the adding means of 1 and the second
Is provided with a normalization rounding means for selecting and normalizing the output of the adding means.

[0009]

According to the present invention, when the quotient is calculated, the rounding position determining means for determining the rounding position by a plurality of partial quotients excluding the finally obtained partial quotient is provided.
Since the rounding and normalization can be performed at the same time when the partial quotient finally obtained is obtained, the rounding and normalization of the operation result can be performed at high speed.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT FIG. 1 is a block diagram of a normalization rounding device according to an embodiment of the present invention.

The operation of the normalization rounding device according to the embodiment of the present invention will be described below with reference to the drawings. In FIG. 1, reference numerals 1 and 2 denote partial sums and carrys respectively obtained by the multiplication array, 12 denotes a partial quotient storage register for storing n-1 partial quotients excluding the finally obtained partial quotient,
Reference numerals 13, 14, 20 designate a selection circuit for selecting one of the two inputs, 15 a rounding position determination circuit for determining a rounding position, 1
6 and 17 are adders with different rounding positions that perform rounding while changing the rounding position and add two numbers, 18 are adders that perform two number addition, and 19 is a rounded result that is different. A normalization rounding determination circuit for determining whether or not to perform normalization and a normalization circuit 21 for performing normalization.

FIG. 4 shows a data format handled by an arithmetic unit using the normalized rounding device in this embodiment. Figure 4
In, 61 is a sign, 62 is an exponent, and 63 is a mantissa. As shown in FIG. 4, it is a floating point number consisting of a 1-bit code 61, an 11-bit exponent 62 and a 53-bit mantissa 63. When calculating the product and quotient, the sign is obtained from the multiplier and the multiplicand and the sign bit of the divisor and the dividend, and the exponent is the sum of the exponent of the multiplier and the multiplicand when calculating the product. It is obtained by adding,
When the quotient is calculated, it can be obtained by subtracting the exponent of the divisor from the exponent of the dividend and further subtracting 1 if a precision loss occurs. Therefore, in the present embodiment, the mantissa processing will be described for simplification of description. For rounding, a method of rounding the bit one bit below the least significant bit is used.

The partial quotient storage register 12 stores n-1 m-bit partial quotients. The partial quotient stored in FIG. 5 is shown. In FIG. 5, 71, 72, 73, 74, 75
Are partial quotient 1, partial quotient 2, partial quotient 3, partial quotient 4, respectively
Partial quotient 5. As shown in FIG. 5, here, n = 6,
Since m = 12, five partial quotients from partial quotient 1 to partial quotient 5 are stored by iterative calculation of multiplication. The five partial quotients can be divided into two non-overlapping intermediate values. There are several methods of division, an example of which is shown in FIG.

In FIG. 6, 81 and 82 are intermediate values. As shown in FIG. 6, the intermediate value 81 consists of a bit string of partial quotient 1, partial quotient 3, partial quotient 5 and 0, and the intermediate value 82 consists of a bit string of partial quotient 2 and partial quotient 4 and 0. Selection circuit 1
Reference numerals 3 and 14 respectively output the partial sum and the partial carry obtained by the multiplication array when calculating the product and when calculating the five partial quotients by the iterative calculation of the multiplication, and obtaining the five partial quotients. When the final partial quotient is obtained and the quotient is calculated, the intermediate value 81 and the intermediate value 82 shown in FIG. 6 are output. The rounding position determination circuit 19 determines the rounding position based on the partial quotient 5, and the adders 16 and 17 output the selection circuit 1 based on this output.
With the outputs of 3 and 14 as input, the rounding position is changed and rounding is performed, and addition of two numbers is performed. When five partial quotients are to be obtained by iterative calculation of multiplication, the adder 17 receives the partial sum 1 and the partial carry 2 as input and rounds them to 2 without rounding.
The partial quotient is obtained by adding the numbers and sequentially stored in the partial quotient storage register 12.

FIG. 7 shows a pattern of rounding positions of the adders 16 and 17 determined by the rounding position judging circuit 15. When calculating the product, the adder 16 rounds 2 ^-52 bits as shown in FIG. 7 because the adder 16 performs rounding when a carry occurs, and the adder 17 performs rounding when no carry occurs. ^So round 2 ^-53 bits. Similarly, when calculating a quotient, rounding can be performed in two ways, one with no loss of digits and one with loss of digits. The least significant bit of partial quotient 5 is the maximum of the partial quotient obtained last. Since it overlaps with the upper bits, the most significant bit of the final partial quotient is "1"
In the case of, rounding must be performed at the same time, and four types of rounding are required.

However, by changing the rounding position according to the pattern of the lower bits of the partial quotient 5, four types of rounding can be performed.
It can be done by rounding the street. The least significant bit of the partial quotient 5 corresponds to bits 2 ^-55 , and when this bit is "0", the influence of the most significant bit of the partial quotient obtained last can be ignored, whereby the adder 16 7 rounds the bit of 2 ^-53 as shown in FIG. 7 in order to carry out the case where no digit loss occurs, and the adder 17 rounds the bit of 2 ^-54 as rounding when the digit loss occurs. The lower 2 bits of the partial quotient 5 correspond to 2 ^-54 , 2 ^-55 , these bits are "01", and when the most significant bit of the partial quotient finally obtained is "1", the partial quotient is the highest. Due to the influence of the upper bits, the rounding position does not change from when the least significant bit of the partial quotient 5 is "0".
When the lower 2 bits of the partial quotient 5 is "11" and the most significant bit of the partial quotient obtained last is "1", if the digit is lost, the least significant bit of the partial quotient 5 is "0". 7 does not change the rounding position, but when no digit loss occurs, the adder 16 performs rounding when a digit loss occurs due to the influence of the most significant bit of the final partial quotient. Round 2 ^-52 bits as shown in.

Further, when calculating the quotient, the five partial quotients are added, and at the same time, the adder 17 receives the partial sum 1 and the partial carry 2 as inputs and determines the most significant bit of the final partial quotient. The normalized rounding determination circuit 19 receives the high-order bits of the outputs of the adders 16 and 17, the output of the adder 18 and the partial quotient 5 as input, and selects which of the two rounding results, and
Whether or not to normalize is determined, and accordingly, the selection circuit selects one of two rounding results, and the normalization circuit determines whether a carry occurs when calculating a product and when a quotient is calculated. When digit loss occurs, normalization is performed and the operation result 3 is output.

Two types of rounding result selection patterns of the normalized rounding determination circuit are shown in FIGS. FIG. 8 shows a rounding result selection pattern when calculating a product, and FIG. 9 shows a rounding result selection pattern when calculating a quotient.

[0019] When calculating the product, in the case of two rounding results in 2 ¹ bit are "1" when a carry-up and a carry did not occur when produced, adding determines that carry has occurred When the rounding result of the adder 16 is "0", it is determined that no carry has occurred, and the rounding result of the adder 17 is selected. When the rounding results are "1" and "0", respectively, the rounding is performed. If a carry has occurred, it is determined that no carry has occurred, and the rounding result of the adder 17 is selected. Similarly, when calculating the quotient, to determine whether cancellation at 2 ⁰ bit of the two rounding results when occurred cancellation and if that did not occur cancellation occurs rounding adder 16, 17 The result is selected, but when the lower 2 bits of the partial quotient 5 is “01” and the most significant bit of the partial quotient finally obtained is “1”, one of the rounding results of the adders 16 and 17 is selected. Alternatively, when the lower 2 bits of the partial quotient 5 is “11” and the most significant bit of the partial quotient obtained last is “0”, rounding of the adder 17 is performed regardless of whether or not a digit cancellation has occurred. Select a result.

As described above, according to the normalized rounding device of the embodiment of the present invention, the adder 18 obtains the final partial quotient and the rounding position determining circuit 15 changes the rounding position to perform rounding. Therefore, rounding and normalization of the operation result can be performed at high speed. Further, since the adder 18 only needs to find the most significant bit of the final partial quotient,
When the adder 18 is configured by the look-ahead carry circuit, the circuit scale does not increase because it can be configured by only the 1-bit adder and the carry circuit.

Although one embodiment of the present invention has been described above, one embodiment of the present invention employs a method of rounding the bit one place below the least significant bit of the mantissa of a floating point number as the rounding method. , ANSI / IEEE Std 754
In order to perform floating-point number multiplication and floating-point division that conform to the specifications of the −1985 standard, the least significant bit of the mantissa is set as the guard bit and the round bit in order, and the logical sum of the bits below it is set as the sticky bit, and RN ( Round to nearest value), RP (round toward + ∞), RM
Rounding may be performed with four rounding modes (rounding toward −∞) and RZ (rounding toward 0).

[0022]

As described above, according to the present invention, when a quotient is calculated, the final partial quotient can be obtained and rounding and normalization can be performed at the same time. It is possible to provide a high-speed normalized rounding device, and its practical effect is great.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a normalization rounding device according to an embodiment of the present invention.

FIG. 2 is a block diagram of a conventional normalization rounding device.

FIG. 3 is a diagram showing a positional relationship of n partial quotients.

FIG. 4 is a diagram showing a data format.

FIG. 5 is a diagram showing five partial quotients.

FIG. 6 is a diagram showing a method of dividing five partial quotients into two intermediate values.

FIG. 7 is a diagram showing a rounding position pattern.

FIG. 8 is a diagram showing a rounding result selection pattern when calculating a product.

FIG. 9 is a diagram showing a rounding result selection pattern when calculating a quotient.

[Explanation of symbols]

1,31 Partial sum 2,32 Partial carry 3,33 Operation result 12,42 Partial quotient storage register 13,14,20,43,44,48 Selection circuit 15 Rounding position determination circuit 16,17,45,46 Rounding And adder for adding two numbers 18 Adder for adding two numbers 19,47 Normalization rounding determination circuit 21,49 Normalization circuit

Claims (1)

[Claims] 1. A product is calculated by adding a partial sum 1 and a partial carry 2 obtained by a multiplication array, a plurality of partial quotients is obtained by iterative calculation of multiplication, and the plurality of partial quotients are added. In a computing unit for calculating a quotient, a plurality of partial quotients excluding the finally obtained partial quotient are divided into a first intermediate value and a second intermediate value which do not overlap, and the partial sum 1 and the first intermediate value are divided. First selecting means 13 for selecting, and second selecting means 14 for selecting the partial carry 2 and the second intermediate value.
A rounding position determining means 15 for determining a rounding position based on a plurality of partial quotients excluding the finally obtained partial quotient, an output of the first selecting means and an output of the second selecting means,
The first and second adding means 16 and 1 having different rounding positions for changing the rounding position to perform rounding and adding the two input numbers
7, a third adder 18 for obtaining the value of the most significant bit of the partial quotient finally obtained by inputting the partial sum 1 and the partial carry 2; the output of the first adder and the second The output of the adder, the output of the adder 3 and a plurality of partial quotients excluding the final partial quotient are input, and the first
Of the output of the adding means and the output of the second adding means, the normalization rounding determination means 19 for determining which rounding result to select and normalize, and the output of the normalization rounding determination means. A normalization rounding means 20 for selecting and normalizing the output of the first adding means and the output of the second adding means,
21. A normalization rounding device comprising: