JPH0581118A - Information processor - Google Patents

Abstract

PURPOSE:To realize an information processor where a specified processing (for example: data inversion) having few advantages in leaving the processing to a hardware part by an ordinary method is executed at high speed. CONSTITUTION:When data is inverted, CPU 11 defines the hardware part 13 to be validity and also reads data from a memory 12 with the control circuit 20. Read data is inverted in an inverter circuit 22 after being latched in a latching circuit 21 and the inverted data is given to CPU 11 with a buffer circuit 23 and a data bus 14. Thus, the inversion processing of data is realized by the hardware part 13 as one of continuous access operations.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing apparatus such as a document creating / editing apparatus (word processor), and more particularly to a speeding up of processing of a specific function.

[0002]

2. Description of the Related Art Information processing devices such as document creation / editing devices
As shown in FIG. 2, the CPU (microprocessor) 1 mainly performs software processing while accessing the memory 2.

For example, conventionally, the inversion process performed to reverse display the display data stored in the display memory is performed as follows. That is, the CPU 1 specifies the address of the memory 2 via the address bus 3 and sends the read signal to the memory 2 via the control bus 4.
Data to be supplied to the memory 2 for inversion processing is read from the memory 2, the data is fetched via the data bus 5, software is inverted, and then the address of the memory 2 is designated via the address bus 3 and the control bus 4 is set. A write signal is given to the memory 2 via the memory and the inverted data output to the data bus 5 is written to the memory 2.

When inverting one data in this way,
The procedure of reading from the memory 2, inversion processing (data processing), and writing to the memory 2 is performed.

[0005]

By the way, in practice, 1
When trying to reverse display for more than one character, the number of data to be subjected to the reverse processing is large, and in many cases,
The data is often continuous.

When inverting such a large amount of data,
If software processing is performed each time, the total processing time cannot be avoided.

Therefore, it is possible to entrust such specific processing, which was processed by software, to hardware. A general method of entrusting specific processing to hardware is that the CPU 1 reads data from the memory 2 and gives the data to the hardware section, and the CPU 1 fetches the data after being processed by the hardware section and then the memory 2
Is a way to write. However, with this method, CP
Data transfer between U1 and the hardware part is required twice, and in the case of a simple process such as data inversion, the amount of data to be processed is reduced even if the hardware part is entrusted with the process due to the data transfer time increased twice. Depending on the situation, the processing time cannot be shortened and the processing time may be lengthened.

Therefore, it is possible to block-transfer from the memory 2 to the hardware unit and execute the processing by the hardware unit by using the DMA method so that the CPU 1 does not transfer the data to the hardware unit. Even if there is a small amount of data to be processed by the hardware unit, even if the processing is entrusted to the hardware unit, there is little advantage in terms of processing time.

The present invention has been made in consideration of the above points, and in a conventional general method, it is possible to process a specific function process, which has little advantage of entrusting the process to a hardware unit, at high speed. The present invention intends to provide an information processing device that can be used.

[0010]

In order to solve such a problem, an information processing apparatus according to the present invention has a branch data path provided in parallel on a data bus between a CPU and a memory, which is effective when a specific function process is instructed. , A data processing circuit which is inserted on this branch data path to execute the specific function processing by hardware, and at the time of an access operation after the CPU instructs the specific function processing, the data on the data bus is transferred to the branch data path. And a control circuit having a hardware configuration for giving a CP.
It is assumed that the data processing circuit processes the data to be transferred during the access operation of the U memory.

[0011]

In the present invention, when the CPU executes the specific function processing, the branch data path provided in parallel with the data bus is made effective. Thus, the data output from the CPU and directed to the memory is given to the memory after being subjected to the specific function processing by the data processing circuit, or the data output from the memory and directed to the CPU is subjected to the specific function processing. And then given to the CPU.

As a result, such a special function process is performed by C
This can be realized as a part of the access operation of the PU and by the hardware configuration, so that the speedup can be realized.

[0013]

An embodiment of the present invention will be described in detail below with reference to FIG. Note that FIG. 1 is a block diagram showing the configuration of this embodiment.

In this embodiment also, the processing is speeded up by entrusting specific processing to the hardware section. Moreover, in the conventional delegation method, even if the processing is entrusted to the hardware section, the effect is small. It relates to data inversion processing.

In FIG. 1, an information processing apparatus 10 of this embodiment includes a CPU 11, a memory 12 and a hardware section 1.
It is composed of 3.

The hardware section 13 comprises a control circuit 20, a data latch circuit 21, an inverter circuit 22 and a data buffer circuit 23.

The control circuit 20 includes a CPU 11 and a memory 1.
It is inserted on the control bus 16 that connects the two. The control circuit 20 is provided with a control signal from the CPU 11 for instructing the valid / invalid state of the hardware unit 13.

The control circuit 20 includes the hardware unit 13
When the invalid state is instructed, the read signal and the write signal from the CPU 11 and other control signals are given to the memory 12 as they are. On the other hand, the control circuit 20
Generates a timing signal for the data latch circuit 23 and the data buffer circuit 23 based on a read signal, a write signal from the CPU 12 and other control signals when the valid state of the hardware unit 13 is instructed. The read signal, the write signal, and other control signals synchronized with these timing signals are given to the memory 12.

The data latch circuit 21 is connected to the data bus 14 connecting the CPU 11 and the memory 12, and latches the data read from the memory 12 based on the timing signal from the control circuit 20. To do.

The data latched by the data latch circuit 21 is applied to the inverter circuit 22. The inverter circuit 22 inverts this data and supplies it to the data buffer circuit 23. The data buffer circuit 23 is the data bus 1
4 and buffers the inverted data on the basis of the timing signal from the control circuit 20 and supplies it to the data bus 13.

The data latch circuit 21 and the data buffer circuit 23 form a data path branched from the data bus 14 connecting the memory 12 and the CPU 11.

Data bus 14 and control bus 16
Is connected to the hardware unit 13 as described above, but the address bus 15 is connected to the CPU 11 and the memory 12 without being connected to the hardware unit 13.

In the information processing apparatus 10 having the above configuration, when inverting the display data stored in the memory 12 for reverse display, each unit operates as follows.

The CPU 11 gives a valid / invalid signal to the control circuit 20 to bring the hardware section 13 into a valid state. After that, the address of the memory area in which the original data is stored is output to the address bus 15 and the read signal is output. The valid / invalid signal indicates the valid state until the inversion processing of all the data to be inverted is completed.

The control circuit 20 transfers the read signal to the memory 12
And output the data to the data bus 14,
A timing signal is given to the data latch circuit 21 to latch the data, and the read signal given to the memory 12 is made invalid. Such data is inverted via the inverter circuit 22, buffered by the data buffer circuit 23 to which the timing signal is given from the control circuit 20, and given to the data bus 14. Such inverted data is given to the CPU 11.

At this time, the CPU 11 outputs a write signal, and outputs the given inverted data as it is to the data bus 14. At this time, the address remains unchanged. As a result, the inverted data is stored in the original memory area of the memory 12.

If there is data to be inverted,
The CPU 11 repeats the above operation. When the processing for all the data to be inverted is completed, the CPU 11 activates /
The invalid signal shall indicate an invalid state.

When the hardware section 13 is in the invalid state, the control signals such as the read signal and the write signal are directly applied to the memory 12, so that the CPU 11 can perform the normal access.

Therefore, according to the above-described embodiment, the data inversion process is processed by the hardware unit 13, so that the high-speed process can be executed. In doing so, since the data read by the CPU 11 is guided to a data path different from the original data path and given to the inverter circuit 22 on the path to be processed and taken in by the CPU 11, the access operation of the CPU 11 (read operation) The hardware part 13 can be used as a part of the above, and there is no need to separately perform data transfer between the CPU 11 and the hardware part, and a higher speed can be realized than the use of the hardware part 13 by the conventional method. You can

If the processing executed by the hardware section is complicated, the processing time will extend the read time. However, since the above-described inversion processing is simple, the above-mentioned processing is performed. There is no need to realize high speed.

Further, speeding up can be realized regardless of the number of data to be subjected to the inversion processing. That is, when the data is transferred to the hardware unit by using the DMA method and the hardware unit is used, the effect is great only when there is a large amount of data, but in this embodiment, the processing is performed even when the data is small. The effect of speeding up is obtained.

In the above embodiment, the case where the data is read from the memory 12 via the hardware unit 13 is shown, but the data may be written to the memory 12 via the hardware unit 13. good.

In the above embodiment, the CPU 11 to which the inverted data is given immediately writes the inverted data in the memory 12, but the software processing may be performed on the inverted data.

Further, in the above embodiment, the processing performed by the hardware unit 13 is the inversion processing, but it may be the data rearrangement processing. In practice, image data handled by a document creation / editing apparatus, a personal computer, or the like has the least significant bit (LSB) written on the left side and the right side of the memory area.
A process for rearranging these may be executed so that these can be appropriately used.

[0035]

As described above, according to the present invention, the CPU
The data bus between the memory and the memory is provided with a branch data path that is effective at the time of the instruction of the specific function processing, and a data processing circuit that executes the specific function processing is provided on the branch data path. Since the specific function processing is executed via the branch data path, the specific function processing can be executed at a higher speed than before.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of an information processing device according to the present invention.

FIG. 2 is a block diagram showing a conventional device.

[Explanation of symbols]

10 ... Information processing device, 11 ... CPU, 12 ... Memory, 1
3 ... Hardware section, 14 ... Data bus, 20 ... Control circuit, 21 ... Data latch circuit, 22 ... Inverter circuit,
23 ... Data buffer circuit.

Claims (5)

[Claims] 1. A C which becomes effective when a specific function process is instructed.
A branch data path provided in parallel on the data bus between the PU and the memory, a data processing circuit which is inserted on this branch data path to execute the specific function processing by hardware, and the CPU instructs the specific function processing. And a control circuit having a hardware configuration for giving the data on the data bus to the branch data path in the subsequent access operation, and the data processing circuit processes the data in the access operation to the memory of the CPU. Information processing device. 2. The information processing apparatus according to claim 1, wherein the data processing circuit is an inverter circuit that inverts data. 3. The information processing apparatus according to claim 1, wherein the data processing circuit is a rearrangement circuit that reverses the order of data. 4. The data processing circuit processes the data read from the memory and supplies the data to the CPU when the CPU makes an access to read the data from the memory. 1. The information processing device according to 1. 5. The data processing circuit processes the data output from the CPU when the CPU accesses the memory to write data to the memory, and supplies the processed data to the memory. The information processing device described.