JPH0584680B2 - - Google Patents
Info
- Publication number
- JPH0584680B2 JPH0584680B2 JP60255846A JP25584685A JPH0584680B2 JP H0584680 B2 JPH0584680 B2 JP H0584680B2 JP 60255846 A JP60255846 A JP 60255846A JP 25584685 A JP25584685 A JP 25584685A JP H0584680 B2 JPH0584680 B2 JP H0584680B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- resistor
- low
- fired ceramic
- circuit board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Landscapes
- Parts Printed On Printed Circuit Boards (AREA)
- Glass Compositions (AREA)
- Apparatuses And Processes For Manufacturing Resistors (AREA)
- Non-Adjustable Resistors (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Description
(産業上の利用分野)
本発明は低温焼成セラミツク回路基板、殊に抵
抗の設計が容易な低温焼成セラミツク回路基板に
関するものである。
(従来技術とその問題点)
一般的に抵抗の長さと幅によつて比抵抗が変動
する所謂ターミナル効果は、これが大きいと回路
設計が難かしくなるために厚膜ハイブリツドセラ
ミツク基板の分野ではターミナル効果を如何に少
く、かつ安定させるかが重要な課題となつてい
る。
このターミナル効果を少く、かつ安定させる方
法として高温焼成セラミツク基板では従来抵抗ペ
ーストの組成を変更することにより対処している
が、この方法は、抵抗ペーストの組成を自由に変
更することが難かしい低温焼成セラミツク基板に
は応用できない。
このため、低温焼成セラミツク基板では、従
来、一つのシート抵抗のペーストで異なつた抵抗
値を持つ抵抗体を設計するためには抵抗体の長さ
及び幅を変えて調整していた。
しかし、銀(Ag)系導体を電極とする場合、
電極の影響を受けるので、長さ1mm以下の抵抗体
は安定しない。
ところが、パターンの高密度化のためには抵抗
体をあまり大きくすることはできず小さければ小
さい程望ましい。
従つて、抵抗体の設計上、この相反する2つの
条件を満足させるために従来の抵抗体の設計範囲
はシート抵抗の30〜50%程度に留まつているのが
実情である。
(発明の目的)
本発明は上記の問題点を解消したターミナル効
果が小さくかつ安定した抵抗体の設計が容易な低
温焼成セラミツク回路基板を提供することを目的
とするものである。
(問題点を解決するための手段)
本発明は、銀又は銀−パラジウムを主体とする
金属を導体とし、RuO2−ガラス系を抵抗体とし
て使用した低融点ガラスとアルミナとからなる低
温焼成セラミツク回路基板において、抵抗体層の
下層に絶縁層を介して、抵抗体層の位置に対応さ
せて下層導体層を配置すると共に、その下層導体
層の長さLと抵抗体層の有効長さl、及び下層導
体層の幅Wと抵抗体層の幅wは下記の関係式を
夫々満足し、
L≧l,W≧w
かつ、抵抗体層とその下層導体層との間隔を
100μm以下にしたことにより、ターミナル効果が
小さくかつ安定した低温焼成セラミツク回路基板
を得るものである。
(実施例)
以下、本発明を比較例としての従来例と併せて
説明する。
第1図aは本発明の低温焼成セラミツク回路基
板の縦断面図で、第1図bは第1図aの拡大平面
図である。1は基板(テープ)、2,2′は基板1
上に積層された絶縁層、3は基板1と絶縁層2と
の間に設けられた(印刷された)第2導体層、
4,4′は絶縁層2,2′間に設けられた(印刷さ
れた)第1導体層、5は第1導体層4,4′間に
印刷により設けられた抵抗体層で、該抵抗体層5
は前記第2導体層3の上層に位置するように配設
されている。ここで、下層の第2導体層3の幅及
び長さをそれぞれW及びLとし、他方、抵抗体層
5の幅及び有効長さをそれぞれw及びlとする
と、L≧l、及びW≧wの関係を満足する。
図示した例においては、抵抗体層5と第2導体
層3との間隔は40μmであつた。
第1図a及びbに示す本発明の低温セラミツク
回路基板は、一般に知られている一体焼成、即ち
同時焼成の技法あるいは個別焼成の技法を用いて
焼成されれば良い。同時焼成の場合、通常使用さ
れている印刷法によつて、基板1上に、第2導体
層3を印刷し、次に絶縁層2を印刷し、更に第1
導体4,4′を印刷し、次にこの導体4,4′間を
覆うように、抵抗体層5を印刷し、その上に絶縁
層2′を印刷して、一体焼成することによつて形
成される。
一方、個別焼成の場合、焼成された基板1に第
2導体3を印刷して、焼成後、更に絶縁層を印刷
して焼成し、次に同様に印刷と焼成を繰り返せば
良い。
第1図に示す低温焼成セラミツク回路基板のテ
ープ(基板)、絶縁層及び抵抗の組成は第1表に
示す組成のものを使用した。
(Industrial Application Field) The present invention relates to a low-temperature fired ceramic circuit board, and particularly to a low-temperature fired ceramic circuit board whose resistance can be easily designed. (Prior art and its problems) In general, the so-called terminal effect, in which specific resistance varies depending on the length and width of the resistor, is difficult to design if it is large, so the terminal effect is used in the field of thick-film hybrid ceramic substrates. An important issue is how to reduce and stabilize this amount. Conventionally, this terminal effect is reduced and stabilized by changing the composition of the resistor paste in high-temperature fired ceramic substrates, but this method is difficult to change at low temperatures where it is difficult to freely change the composition of the resistor paste. It cannot be applied to fired ceramic substrates. For this reason, in the case of low-temperature fired ceramic substrates, conventionally, in order to design resistors having different resistance values using one sheet resistor paste, the length and width of the resistor were adjusted. However, when using a silver (Ag)-based conductor as an electrode,
Resistors with a length of 1 mm or less are not stable because they are affected by the electrodes. However, in order to increase the density of the pattern, the resistor cannot be made too large, and the smaller it is, the more desirable it is. Therefore, in order to satisfy these two contradictory conditions when designing a resistor, the design range of conventional resistors is actually limited to about 30 to 50% of the sheet resistance. (Object of the Invention) An object of the present invention is to provide a low-temperature fired ceramic circuit board which eliminates the above-mentioned problems, has a small terminal effect, and allows easy design of a stable resistor. (Means for Solving the Problems) The present invention is a low-temperature-sintered ceramic made of alumina and a low-melting glass that uses a metal mainly composed of silver or silver-palladium as a conductor and RuO 2 -glass as a resistor. In the circuit board, a lower conductor layer is arranged below the resistor layer via an insulating layer, corresponding to the position of the resistor layer, and the length L of the lower conductor layer and the effective length l of the resistor layer are arranged. , and the width W of the lower conductor layer and the width w of the resistor layer satisfy the following relational expressions, L≧l, W≧w, and the distance between the resistor layer and the lower conductor layer is
By setting the thickness to 100 μm or less, a low-temperature fired ceramic circuit board with small terminal effect and stability can be obtained. (Example) The present invention will be described below along with a conventional example as a comparative example. FIG. 1a is a longitudinal sectional view of a low-temperature fired ceramic circuit board of the present invention, and FIG. 1b is an enlarged plan view of FIG. 1a. 1 is the substrate (tape), 2, 2' is the substrate 1
an insulating layer laminated thereon, 3 a second conductor layer provided (printed) between the substrate 1 and the insulating layer 2;
4 and 4' are first conductor layers provided (printed) between the insulating layers 2 and 2'; 5 is a resistor layer provided by printing between the first conductor layers 4 and 4'; body layer 5
is arranged so as to be located above the second conductor layer 3. Here, if the width and length of the lower second conductor layer 3 are W and L, respectively, and the width and effective length of the resistor layer 5 are w and l, respectively, then L≧l and W≧w satisfy the relationship. In the illustrated example, the distance between the resistor layer 5 and the second conductor layer 3 was 40 μm. The low temperature ceramic circuit board of the present invention shown in FIGS. 1a and 1b may be fired using commonly known integral firing techniques or separate firing techniques. In the case of simultaneous firing, the second conductive layer 3 is printed on the substrate 1, then the insulating layer 2 is printed, and then the first
By printing the conductors 4, 4', then printing the resistor layer 5 so as to cover between the conductors 4, 4', and printing the insulating layer 2' on top of it, and then integrally firing it. It is formed. On the other hand, in the case of individual firing, the second conductor 3 is printed on the fired substrate 1, and after firing, an insulating layer is further printed and fired, and then printing and firing are repeated in the same manner. The compositions of the tape (substrate), insulating layer, and resistor of the low-temperature fired ceramic circuit board shown in FIG. 1 were as shown in Table 1.
【表】
また、導体材料としては、第1導体層にAg:
80、Pd:20(wt%)、第2導体層にAg:100%の
導体を使用した。
第2表は第1図a及びbに示す本発明の低温焼
成セラミツク回路基板及び第2図に示す従来の低
温焼成セラミツク回路基板900℃で20分間ホール
ドして焼成したものの抵抗値の測定結果を示すも
のである。
また、第2表の右側の2つの欄は、長さ4mmの
抵抗体層のシート抵抗を基準にしたときのシート
抵抗の変化率を示している。
尚、従来の低温焼成セラミツク基としては、第
2図に示すように、抵抗体層5の下部に第2導体
層3を配置しないものを使用した。
本発明者等の実験によれば、抵抗体層5と第2
導体層3との間隔が100μm程度になるまで、タ
ーミナル効果の改善が見られた。[Table] Also, as a conductor material, Ag for the first conductor layer:
80, Pd: 20 (wt%), and Ag: 100% conductor was used for the second conductor layer. Table 2 shows the resistance value measurement results of the low-temperature fired ceramic circuit boards of the present invention shown in Figures 1a and b and the conventional low-temperature fired ceramic circuit boards shown in Figure 2 held and fired at 900°C for 20 minutes. It shows. Furthermore, the two columns on the right side of Table 2 show the rate of change in sheet resistance when the sheet resistance of a resistor layer with a length of 4 mm is used as a reference. The conventional low-temperature fired ceramic base used was one in which the second conductor layer 3 was not disposed below the resistor layer 5, as shown in FIG. According to experiments conducted by the present inventors, the resistor layer 5 and the second
Improvement in the terminal effect was observed until the distance from the conductor layer 3 was approximately 100 μm.
【表】
所定長さにおけるシー
シート抵抗 ト抵抗
※ =[Table] Seat resistance at specified length * =
Claims (1)
体3,4とし、RuO2−がラス系を抵抗体5とし
て使用した低融点ガラスとアルミナとからなる低
温焼成セラミツク回路基板において、抵抗体層5
の下層に絶縁層2を介して、抵抗体層5の位置に
対応させて下層導体層3を配置すると共に、その
下層導体層3の長さLと抵抗体層5の有効長さ
l、及び下層導体層3の幅Wと抵抗体層5の幅w
は下記の関係式を夫々満足し、 L≧l,W≧w かつ、抵抗体層5とその下層導体層3との間隔
を100μm以下にしたことを特徴とする低温焼成セ
ラミツク回路基板。 2 低融点ガラスをCaO又はMgO−Al2O3−
SiO2−B2O3系としたことを特徴とする特許請求
の範囲第1項に記載の低温焼成セラミツク回路基
板。[Scope of Claims] 1. A low-temperature fired ceramic circuit board made of low melting point glass and alumina, in which conductors 3 and 4 are made of a metal mainly composed of silver or silver-palladium, and a RuO 2 - lath is used as a resistor 5. In, the resistor layer 5
A lower conductor layer 3 is arranged below the insulating layer 2 so as to correspond to the position of the resistor layer 5, and the length L of the lower conductor layer 3, the effective length l of the resistor layer 5, and Width W of lower conductor layer 3 and width W of resistor layer 5
A low-temperature fired ceramic circuit board, which satisfies the following relational expressions, L≧l, W≧w, and the distance between the resistor layer 5 and the lower conductor layer 3 is 100 μm or less. 2 Low melting point glass with CaO or MgO−Al 2 O 3 −
The low-temperature fired ceramic circuit board according to claim 1, characterized in that it is made of SiO 2 -B 2 O 3 system.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60255846A JPS62117386A (en) | 1985-11-16 | 1985-11-16 | Low temperature sintered ceramic substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60255846A JPS62117386A (en) | 1985-11-16 | 1985-11-16 | Low temperature sintered ceramic substrate |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62117386A JPS62117386A (en) | 1987-05-28 |
| JPH0584680B2 true JPH0584680B2 (en) | 1993-12-02 |
Family
ID=17284402
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60255846A Granted JPS62117386A (en) | 1985-11-16 | 1985-11-16 | Low temperature sintered ceramic substrate |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62117386A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02265206A (en) * | 1989-04-05 | 1990-10-30 | Matsushita Electric Ind Co Ltd | Square-sheet type chip resistor and manufacture thereof |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5570056A (en) * | 1978-11-22 | 1980-05-27 | Hitachi Ltd | Preparation of thick film hybrid integrated circuit |
| JPS60160687A (en) * | 1984-01-31 | 1985-08-22 | ソニー株式会社 | Thick film laminated board |
-
1985
- 1985-11-16 JP JP60255846A patent/JPS62117386A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS62117386A (en) | 1987-05-28 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term |