JPH0584687B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a technology that is particularly effective when applied to flip-flop technology and even edge-trigger flip-flops.
This invention relates to a technology that is effective for use in ECL (emitter coupled logic) type edge-triggered flip-flops.

[Background technology]

FIG. 5 schematically shows a conventional edge trigger type flip-flop.

As shown in the figure, this type of edge-triggered flip-flop includes a slave section 10 and a master section 20.

As shown in Figure 6, this edge-triggered flip-flop operates when the input data is input when the clock signal CK rises (or falls).
Din is read and held until the next rise (or fall) of the clock signal CK. Dout indicates the held output data.

Regarding this type of edge-triggered flip-flop, for example, see "Detailed explanation of digital IC circuits (Part 1)" published by Radio Gijutsusha, written by Kimio Goto, Showa era.
Published on July 10, 1956, pages 125 and 126.

However, in this type of conventional edge-triggered flip-flop, the master section 10 and the slave section 20 each have a holding circuit, and the input data once read and held in the master section 10 is transferred to the slave section 20. Because of the heat, the circuitry of the master section 10 in particular became complicated.
For this reason, the overall circuit configuration becomes complicated and the number of elements becomes extremely large. There was a problem.

[Purpose of the invention]

An object of the present invention is to provide a flip-flop technology that enables the operation of the edge-triggered flip-flop described above to be realized with a simple circuit having a small number of elements.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Summary of the invention]

A brief overview of typical inventions disclosed in this application is as follows.

That is, the holding operation of the holding circuit and the data input operation to the holding circuit are controlled in a complementary manner by a differential circuit, and the differential circuit is controlled by two transistors, first and second transistors connected in parallel with each other. Q
1, Q2 and these two transistors Q1, Q2
A third transistor Q3 forming a differential pair with the first, second, and third transistors Q1, Q2, and Q
a constant current circuit interposed between the common emitter of No. 3 and the negative power supply potential;
The purpose is to make it possible to realize the operation of an edge-triggered flip-flop with a simple circuit with a small number of elements by applying a reference potential that determines the input threshold of the differential circuit to the base of the transistor Q3. The goal is to achieve the following.

〔Example〕

Hereinafter, typical embodiments of the present invention will be described with reference to the drawings.

In the drawings, the same reference numerals indicate the same or corresponding parts.

FIG. 1 shows a first embodiment of a flip-flop according to the invention.

The flip-flop shown in the figure is connected to a clock signal.
It is an edge-triggered flip-flop that reads and holds input data Din at the rising edge of CK, and is particularly constructed using ECL (emitter coupled logic). This edge-triggered flip-flop includes a holding circuit 21, an input control circuit 22, a differential circuit 11, and a timing generation circuit 3. Below, each part 21, 22,
11 and 3 will be explained in detail. Note that Vcc indicates a positive power supply potential, and Vee indicates a negative power supply potential.

The holding circuit 21 is a kind of set-reset type flip-flop, and its main parts are npn bipolar transistors Q4, Q5, Q6, Q7,
It is composed of resistors R1, R2, R3, and R4, and constant current circuits 12 and 13. This holding circuit 2
1 holds the input data Din and outputs it. Dout indicates its holding output.

The input control circuit 22 is a circuit attached to the holding circuit 21, and is composed of only two npn bipolar transistors Q8 and Q9. These two transistors Q8 and Q9 form a differential pair, and the input data Din is applied to the base of one Q8, and the reference potential Vbb1 is applied to the base of the other Q9. This input control circuit 22 controls the input operation of the holding circuit 21.

The differential circuit 11 is composed of npn bipolar transistors Q1, Q2, Q3 and a constant current circuit 14. Transistors Q1 and Q2 are connected in parallel to each other. These Q1, Q2 and the other Q3 form a differential pair. The emitters of Q1, Q2, and Q3 are commonly connected, and this common emitter is connected to the negative power supply potential Vee via a constant current circuit 14. Further, the common collectors of Q1 and Q2 are connected to the common ground point D of the holding circuit 21, that is, the common emitter of Q3 and Q4. The collector of Q3 is connected to the common ground point C of the input control circuit 22, that is, the common emitter of Q8 and Q9. Furthermore, signals A and B, which will be described later, are input to the bases of Q1 and Q2, and a reference potential is input to the base of Q3.
Vbb2 is now given. Reference potential
Vbb2 determines the input threshold of the differential circuit 11.
Thereby, the differential circuit 11 controls the respective operations of the holding circuit 21 and the input control circuit 22 in a complementary manner.

The timing generation circuit 3 receives an input clock signal.
Phase dividing means for distributing CK into positive logic and negative logic;
and delay means for delaying one of the two signals distributed by the phase dividing means. In this case, the phase dividing means and delay means are constituted by logic gates (NOR and OR) 31 and 32, respectively. This timing generation circuit 3
A negative logic non-delayed clock signal A which is relatively undelayed and a delayed clock signal B which is relatively delayed by the logic gate 32 are outputted from the gate 32. These two signals A and B are distributed and input to the bases of one of the transistors Q1 and Q2 of the differential circuit 11. As a result, the differential circuit 1
1 is driven when the input clock signal CK rises or falls.

Next, the operation will be explained.

FIG. 2 shows an example of the operation of the flip-flop shown in FIG. 1 using a timing chart.

In Figures 1 and 2, the clock signal
When CK is in the inactive state of “L” (low potential), signal A is “H” and signal B is “L” (high potential).
Therefore, the transistor Q1 of the differential circuit 11 becomes
Becomes ON (conducting) state. In this state, point C becomes a low potential and the holding circuit 21 becomes active, while point D becomes a high potential and the input control circuit 22 becomes inactive. Therefore, at this time, input of the input data Din is prohibited, while the holding circuit 21
In other words, the respective collector potentials of Q4 and Q5 continue to be output as held output data Dout and Dout, respectively.

Next, when the input clock signal CK rises from the inactive state "L" to the active state "H", first the signal A switches to "L". For signal B, depending on the transmission delay time τ of the logic gate 32,
It remains at “L”. In this state, both transistors Q1 and Q2 of the differential circuit 11 are
Becomes OFF (non-conducting) state. Then, point C becomes a high potential and the holding circuit 21 becomes inactive, while point D becomes a low potential and the input control circuit 22 becomes active. As a result, the input data Din is input to the holding circuit 21 by the input control circuit 22.

After that, after a predetermined transmission delay time τ, the signal B
When the voltage changes from "L" to "H", point C becomes a low potential again and the holding circuit 21 becomes active, while point D becomes a high potential and the input control circuit 22 becomes inactive. Become. As a result, the holding circuit 21
Input data Din just before signal B switches to “H”
is updated to a holding state according to the current holding state, and this updated holding state is maintained. Then, this new held state, that is, the state of each collector potential of Q4 and Q5, continues to be output as held output data Dout.

After this, the clock signal CK returns to "L", and first the states of A="H" and B="H" appear, and then the original state of A="H" and B="L" appears. but,
During this time, the holding state of the holding circuit 21 is maintained as it is.

As described above, even with a simple configuration including only one holding circuit 21, an edge-trigger flip-flop operation in which input data Din is read and held at the rising edge of the clock signal CK can be obtained.
In addition, since the input data Din is input directly to the holding circuit 21 without relying on the method of transferring input data from the master section to the slave section,
It is also possible to obtain the advantage that the delay in reading the input data Din can be reduced.

In Figure 1, if the common collectors of Q1 and Q2 are connected to point D and the collector of Q3 is connected to point C, the input data Din is read and held at the rising edge of the clock signal CK, contrary to the above. You can get the action.

〔effect〕

(1) The holding operation of the holding circuit and the data input operation to this holding circuit are controlled in a complementary manner by the differential circuit, and the differential circuit is controlled by the first and second Two transistors Q1 and Q2, a third transistor that forms a differential pair with these two transistors, and a constant voltage that is interposed between the common emitter of each of the first, second, and third transistors and the negative power supply potential. By providing a reference potential that determines the input threshold of the differential circuit to the base of the third transistor, the operation of an edge-triggered flip-flop can be performed using a simple circuit with a small number of elements. The effect is that it can be realized by

(2) Furthermore, since the input data is directly read into the holding circuit, it is possible to reduce the delay in the read operation.

Although the invention made by the present inventor has been specifically explained above based on examples, this invention is not limited to the above-mentioned examples, and it is understood that various changes can be made without departing from the gist of the invention. Needless to say. For example, a configuration using a MOS field effect transistor instead of a bipolar transistor may be used.

[Application field]

The above explanation mainly describes the invention made by the present inventor and the field of application that is its background.
Although the case where the present invention is applied to the ECL type edge-triggered flip-flop technology has been described, the present invention is not limited thereto, and can also be applied to, for example, MOS type or C-MOS type flip-flop technology.

[Brief explanation of the drawing]

1 is a circuit diagram showing a first embodiment of an edge-triggered flip-flop according to the present invention; FIG.
The figure is a timing chart showing the operation of the circuit shown in Fig. 1, Fig. 3 is a block diagram showing the general configuration of an edge-triggered flip-flop according to the prior art, and Fig. 4 is a timing chart showing the operation of the circuit shown in Fig. 3. This is a timing chart. 1...Control unit, 2...Data holding unit, 11...
Differential circuit, 21...Holding circuit, 22...Input control circuit, 3...Timing generation circuit, Din...Input data, Dout...Output data, CK...Clock signal, 31...As phase dividing means Logic gate, 32...Logic gate as delay means.

Claims (1)

[Claims] 1. An edge-triggered flip-flop that reads and holds input data at the rise or fall of a clock signal, including a holding circuit that holds and outputs input data, and an input control circuit that controls the input operation of this holding circuit. , a differential circuit that complementarily controls each operation of the holding circuit and the input control circuit, and a timing circuit that generates a signal for driving this differential circuit at the rise or fall of a clock signal. In this case, when the differential circuit is driven, the holding circuit is deactivated and the input control circuit is activated, and the differential circuit is connected to the first , the second two transistors, and the second two transistors.
a third transistor forming a differential pair with one transistor, and a constant current circuit interposed between the common emitter of each of the first, second, and third transistors and the negative power supply potential; The timing circuit includes a phase dividing means for distributing the input clock signal into positive logic and negative logic, and a delay means for delaying one of the two signals distributed by the phase dividing means, and The delayed signal and non-delayed signal output from the circuit are distributed and inputted to the base of the first transistor and the base of the second transistor, while the input threshold of the differential circuit is input to the base of the third transistor. A flip-flop characterized in that a reference potential for determining the flip-flop is applied.