JPH0584689B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to an unlock detection circuit, for example.
The present invention relates to a circuit that detects the synchronous or asynchronous state of a PLL circuit in a synchronous detection circuit incorporated in an integrated circuit device for an AM stereo decoder or the like.

(Prior Art) In order to receive AM stereo broadcasting adopted in the United States and other countries, it is necessary to perform synchronous detection of the received signal. For this reason, a PLL circuit is used to create a clock synchronized with the input signal, and this clock is used to perform synchronous detection. In this case, when the PLL circuit becomes asynchronous, a beat sound is generated due to the frequency difference between the input signal and the clock signal output from the PLL circuit, so it is necessary to perform normal envelope detection instead of synchronous detection. For this reason,
AM stereo receivers and the like require an unlock detection circuit to detect that the PLL circuit is in an asynchronous state.

Conventionally, determining whether a PLL circuit is synchronous or asynchronous is
This is done by detecting whether the control voltage applied to the voltage controlled oscillator, ie, VCO, used in the PLL circuit is within a predetermined range.

However, in such a conventional type, the control voltage may transiently fall within a predetermined range even when the control voltage is in an asynchronous state, and the control voltage may be in a synchronous state even when the control voltage is outside the predetermined range. There is a disadvantage that the relationship between the control voltage and synchronization or asynchronous state is low, and the reliability of detecting a synchronous or asynchronous state is low. Furthermore, since the control voltage varies depending on the temperature characteristics of each part of the PLL circuit, there is also the problem that the detection state of synchronous or asynchronous varies depending on the environmental conditions.

(Problems to be Solved by the Invention) In view of the above-mentioned problems with the conventional type, the present invention enables accurate discrimination between synchronous and asynchronous states in an unlock detection circuit, and responds to changes in environmental conditions. This is intended to prevent the reliability of unlock detection from decreasing.

(Means for Solving the Problems) In order to solve the above-mentioned problems, according to the present invention, angles of approximately 0° and approximately 90° with respect to the input signal are provided.
a phase-locked circuit that outputs first and second clock signals having a phase difference of a second synchronous detection circuit that integrates the outputs of the first and second synchronous detection circuits, an integration circuit that integrates the outputs of the first and second synchronous detection circuits, and a comparison circuit that compares the respective integral outputs, and synchronizes the phase locked circuit based on the output of the comparison circuit. An unlock detection circuit is provided which is characterized by determining a state.

(Operation) According to the above-mentioned means, in the synchronous state, 0°
The synchronous detection circuit outputs a DC voltage according to the level of the input signal, and the 90° synchronous detection circuit outputs no DC voltage, whereas in the asynchronous state, neither synchronous detection circuit outputs a DC voltage. Therefore, by integrating the outputs of each synchronous detection circuit and comparing them with each other, it is possible to determine whether the outputs are synchronized or not.

(Example) Hereinafter, an example of the present invention will be described with reference to the drawings.
FIG. 1 schematically shows an unlock detection circuit according to a first embodiment of the present invention. The unlock detection circuit shown in the figure is built into an AM stereo receiver, and includes a phase comparator 1 and a low-pass filter 2.
and a voltage controlled oscillator 3, an envelope detection circuit 4, a 0° synchronous detection circuit 5, and a 90°
It has a synchronous detection circuit 6, an unlock detection section 7, a switch circuit 8, and a matrix circuit 9.

In the circuit shown in FIG. 1, an intermediate frequency signal (hereinafter simply referred to as an IF signal) from a tuner section (not shown) is applied to a phase comparator 1 of the PLL circuit.

In the PLL circuit, clock signals c and d are generated in synchronization with this IF signal and having a phase difference of 0° and 90° with respect to the IF signal, respectively. These clock signals c and d are applied to a 0° synchronous detection circuit 5 and a 90° synchronous detection circuit 6, respectively, to synchronously detect the IF signal at each phase. The signal a outputted by the 0° synchronous detection circuit 5 includes the sum signal L+R of the left and right channels, and the output signal b of the 90° synchronous detection circuit 6 contains the difference signal LR of the left and right channels. When the PLL circuit is synchronized with the IF signal, the output e of the unlock detection section 7 causes the switch section 8 to be activated.
Each switch is connected to the position B side, and therefore, each of these sum signals L+R and difference signal L-R is input to the matrix circuit 9, respectively, and the left channel output L _OUT and the right channel output R _OUT
is generated.

On the other hand, when the PLL circuit is in an asynchronous state with the IF signal, the unlock detector 7 detects the asynchronous state from the states of the outputs a and b of each synchronous detection circuit 5 and 6, and the signal e Switch section 8 is switched to position A side by . As a result, the IF signal is subjected to AM detection by the envelope detection circuit 4, inputted to the matrix 9, and outputted from both channels as a monaural output.

FIG. 2 shows detailed configurations of the 0° synchronous detection circuit 5 and the 90° synchronous detection circuit 6 in the circuit shown in FIG. The 0° synchronous detection circuit 5 includes transistors Q ₁ , Q ₂ ,
..., Q ₇ , resistors R ₁ , R ₂ , and capacitor C ₁ . The 90° synchronous detection circuit 6 also has the same configuration as the 0° synchronous detection circuit 5, and the transistor
Q ₈ , Q ₉ , ..., Q ₁₄ , resistors R ₁ , R ₂ , and capacitor C ₁ are provided.

In the 0° synchronous detection circuit 5 having such a configuration, the transistor Q ₁ or Q ₂ and the transistor Q ₄ or Q ₃ are alternately turned on and off by the clock signal c from the PLL circuit, and the transistors Q ₅ and Q gates the IF signal applied between the bases of transistors Q ₂ and _{Q 4}
The synchronous detection output a is output to the commonly connected collectors of the synchronous detection output a. Note that the capacitor _C1 is provided to remove high frequency components. The operation of the 90° synchronous detection circuit 6 is also the same as that of the 0° synchronous detection circuit 5, so a detailed explanation will be omitted. In addition, the transistor
For example, a voltage of 2V _BE is applied to the bases of Q ₇ and Q ₁₄ , which causes each transistor Q ₇
And Q ₁₄ and the resistor R ₂ connected between each emitter and ground operate as a constant current circuit.
Note that V _BE is the base-emitter voltage of each transistor.

In the circuit shown in FIG. 2, the DC bias voltages at output points a and b of each synchronous detection circuit 5 and 6 are the same unless there are variations in the circuit constants, and V _cc −R ₁ /R ₂ V _BE ……( 1) becomes. In the synchronous state, as is well known, the output a of the 0° synchronous detection circuit 5 becomes V _cc −R ₁ /R ₂ V _BE +Kυ _i (2). Here K is a constant. That is, in the synchronous state, a signal corresponding to the input signal υ _i is output as the output a. Furthermore, the output b of the 90° synchronous detection circuit 6 is not output in the synchronous state. Also,
In the asynchronous state, the input signal υ _i and each of the clock signals c and d are unrelated, and when observed over a long period of time, the mutual phase difference uniformly changes from 0° to 360°. Therefore, in this case each output a and b
As such, no DC component is output.

Now, for simplicity, if we assume that the IF signal υ _i is unmodulated, υ _i = Asinω _O t ...(3), and the clock signal e _k output from the PLL circuit.
becomes e _k = B sin (ω _c ^t −) ……(4). ^Since the _synchronous detection circuit is a multiplier _, if _its ^output _is X, _{then c} ^t −) −cos(ω _O ^t −ω _c ^t +)} ...(5) However, the first term in equation (5) is the capacitor C _1
Since ^{it is} removed _by As is clear from equation (6), (a) ω _O ^t ≠ ω _c ^t in the asynchronous state, so
The output X is a beat signal with an amplitude AB/2 and a period (ω _O ^t −ω _c ^t ), and does not include a DC component.

(b) On the other hand, in the synchronous state, ω _O ^t =ω _c ^t .
Therefore, the 0° synchronous detection circuit (=0°) is X _O =
A DC output of AB/2 is generated, and the 90° synchronous detection circuit (=90°) becomes X ₉₀ =0 and does not output a DC component.

Figure 3 shows the PLL using the above properties.
The configuration of the unlock detection section 7 that determines whether the circuit is synchronized or asynchronous is shown. The unlock detection section 7 in the same figure is
A comparator 10, a low pass filter 11 having resistors _R3 , _R4 and a capacitor _C2 , and a resistor
_R5 and a low pass filter 12 having a capacitor _C3 . Low pass filter 11 is 0°
The low-pass filter 12 is connected between the output of the synchronous detection circuit 5 and, for example, a positive input terminal of the comparator 10, and the low-pass filter 12 is connected between the output of the 90° synchronous detection circuit 6 and the negative input terminal of the comparator 10. .

In the circuit shown in Fig. 3, when the PLL circuit is asynchronous, the outputs a and b of each synchronous detection circuit 5 and 6 are both input signals, as shown in Fig. 4.
It becomes a beat component with the clock signal of the PLL circuit and does not include a DC component. Therefore, comparator 1
The voltage b' at the negative polarity input terminal of 0 becomes the DC voltage expressed by the above-mentioned equation (1). On the other hand, the signal a' at the positive input terminal is divided by the resistors R ₃ and R ₄ and becomes a voltage slightly lower than the signal b'. Therefore,
The output e of comparator 10 becomes low level.
Indicates that the PLL circuit is in an asynchronous state.

On the other hand, when the PLL circuit is synchronized with the input signal, as shown in Figure 5, the signal b' corresponding to the output b of the 90° synchronous detection circuit is the same as in Figure 4. However, the output a of the 0° synchronous detection circuit becomes a signal corresponding to the input signal υ _i . A voltage a' obtained by integrating this signal a by the low-pass filter 11 becomes a DC signal having a higher level than the signal b'. Therefore, the output e of the comparator 10 is at a high level.
Indicates that the PLL circuit is in synchronization.

(Effects of the Invention) As described above, according to the present invention, synchronization or non-synchronization of the PLL circuit is detected by comparing the output DC components of each of the 0° synchronous detection circuit and the 90° synchronous detection circuit. It becomes possible to detect the synchronization state extremely accurately, and the occurrence of detection errors due to variations in constants of each component due to temperature characteristics etc. is extremely reduced, greatly improving the reliability of the unlock detection circuit. It becomes possible.

[Brief explanation of the drawing]

FIG. 1 is a block circuit diagram showing an outline of an unlock detection circuit according to an embodiment of the present invention, FIG. 2 is an electric circuit diagram showing details of each synchronous detection circuit used in the circuit of FIG. 1, and FIG. 3 is an electric circuit diagram showing the configuration of the unlock detection section used in the unlock detection circuit of FIG. 1, and FIGS. 4 and 5 are waveform diagrams for explaining the operation of the circuit of FIG. 3. be. 1... Phase comparator, 2... Low pass filter,
3... Voltage controlled oscillator, 4... Envelope detection circuit, 5... 0° synchronous detection circuit, 6... 90° synchronous detection circuit, 7... Unlock detection section, 8... Switch section, 9... Matrix circuit , 10...Comparator, _R1 , _R2 ,..., _R5 ...Resistor, _C1 , _C2 , _C3 ...
...Capacitor, Q ₁ , Q ₂ , ..., Q ₁₄ ...Transistor.

Claims (1)

[Claims] 1 Approximately 0° and approximately 90° relative to the input signal, respectively.
a phase-locked circuit that outputs first and second clock signals having a phase difference of , a first synchronous detection circuit that synchronously detects an input signal using the first clock signal, and a circuit similar to the first synchronous detection circuit a second synchronous detection circuit configured to synchronously detect an input signal using a second clock signal; first and second integrating circuits that respectively integrate outputs of the first and second synchronous detection circuits; and a comparison circuit that compares the integral outputs of the second integration circuit, and determines the synchronization state of the phase locked circuit based on the output of the comparison circuit.