JPH0585042B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a sampling frequency conversion device for sampling data, and particularly to a downsampling circuit that performs thinning through a digital filter.

[Conventional technology]

FIG. 3 shows a block diagram of a general digital filter.

FIG. 4 shows a configuration diagram of a conventional down-sampling circuit using a digital filter.

As shown in Figure 3, a typical digital filter uses a sum-of-products format that calculates the output by multiplying the current sampling data to several samples of past sampling data by each filter coefficient and accumulating the results. are doing. In order to downsample it, the output data is thinned out.

The conventional downsampling circuit shown in FIG. 4 will be explained. First is the filter processing part. At the same time as the input signal 41 is input, each data of the delay circuit 45 is transferred to the next delay circuit 45.
will be forwarded to. Next, the filter coefficients sequentially output by the coefficient generation circuit 46 and each sampling data held by the delay circuit 45 are sent to the selection circuit 4.
7 and multiplied by multiplier 43. The initial value of the delay circuit 45 is 0. The sequentially multiplied data is accumulated by the adder 44, passes through the initialization circuit 50, and is stored in the data holding circuit 48.
is maintained. The output of the initialization circuit 51 is usually
The input is output as is, but 0 is output at the same time as it is repeated for the order of the filter, and the filter processing of 1 input data is completed. By passing the data obtained through filter processing through a gate that opens at the desired sampling timing,
Downsample to any frequency.

[Problem to be solved by the invention]

The problem with the above-mentioned conventional down-sampling circuit using a digital filter is that as the order of the filter increases, a delay circuit is required to hold past sampling data corresponding to the increase in the order of the filter, resulting in an increase in the scale of the hardware. There is. Furthermore, due to the structure, calculations are also performed on data to be thinned out that is not related to the output, so the operation of the circuit must be made faster, resulting in the problem of increased calculation power.

[Differences between the invention and the prior art]

In contrast to the conventional downsampling circuit described above, there is a means to perform calculations that affect the output when one input data is input before the next input data is input, and a means to hold the accumulated data necessary for output. The difference is that the provision of the circuit eliminates the need for a delay circuit required for filter processing.

[Means to solve problems]

The downsampling circuit according to the present invention includes a filter coefficient generation circuit, a multiplier that multiplies sampling data, an adder that accumulates the results, and a data holding circuit that holds the accumulated data.

〔Example〕

FIG. 1 is a block diagram showing one embodiment of a downsampling circuit according to the present invention. 64KHz
This is an example of a circuit that downsamples the sampled data to 1/8 of 8KHz while passing it through a 16th order filter.

FIG. 2 is a diagram showing input/output timing. X is the input, Y is the output, and α is the filter coefficient. The subscripts of X and Y indicate the passage of time, α
The subscript indicates the order of the filter.

As shown in FIG. 2, input data X0 affects two outputs, output data Y-1 and Y0.

An embodiment of the downsampling circuit according to the present invention will be described with reference to FIGS. 1 and 2. First of all, regarding the input signal X0, the next output is the output Y
Perform the necessary processing to obtain -1. Input data X0 is the 16th input data output from the coefficient generation circuit 13.
Multiplyed by the next filter coefficient α16 and the multiplier 14. The multiplication result and data holding circuit 17
The values of are added by the adder 15. The initial values of the data holding circuit 16 and the data holding circuit 17 are 0. At the same time, the value of the data holding circuit 16 is transferred to the data holding circuit 17, and the addition result is transferred to the initialization circuit 1.
9 and is transferred to the data holding circuit 16. The initialization circuit 19 normally outputs the input as it is, but 0 is output at the cycle in which the output signal Y is calculated.

Next, necessary processing is performed to obtain the output Y0 for the input signal X0. This process is the same as the first process except for the filter coefficients. The filter coefficient output from the filter coefficient generation circuit 13 is an 8th-order filter coefficient α8 shifted by 8 orders.
It is. Multiplier 14 multiplies the input signal. The multiplication result and the value of data holding circuit 17 are added by adder 15. At the same time, the value of the data holding circuit 16 is transferred to the data holding circuit 17,
The addition result passes through the initialization circuit 19 and is transferred to the data holding circuit 16.

Similarly, while updating the filter coefficient α from α15 to α7 for input signals X1 to X8,
By processing, the output result Y-1 is obtained. At this time, the data in the data holding circuit 16 is initialized to 0 by the initialization circuit 19, and the data holding circuit 17 holds intermediate results of cumulative data necessary to obtain the output Y0. Furthermore, by repeating input signals X8 to X15, output Y0 is obtained. At this time, the data in the data holding circuit 16 is initialized to 0 by the initialization circuit 19, and the data holding circuit 17 holds intermediate results of cumulative data necessary to obtain the output Y1. By repeating this process, it is possible to perform 1/8 downsampling through a digital filter.

〔Effect of the invention〕

As described above, the present invention can eliminate the delay circuits conventionally required in a downsampling circuit using a digital filter, and can reduce the scale of hardware.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram of a downsampling circuit showing one embodiment of the present invention. FIG. 2 is an input/output timing diagram showing an embodiment of the present invention. Figure 3 shows
Block diagram of a general filter. FIG. 4 is a block diagram of a conventional downsampling circuit. 11... Input signal, 12... Output signal, 13... Filter coefficient generation circuit, 14... Multiplier, 15... Adder, 16... Gate, 17... Data holding circuit, 18
...data holding circuit, 19...initialization circuit, 31...input signal, 32...output signal, 33...multiplier, 34...
Adder, 35...Delay circuit, 41...Input signal, 42
...output signal, 43...multiplier, 44...adder, 45
...Delay circuit, 46...Filter coefficient generation circuit, 4
7... Selection circuit, 48... Data holding circuit, 49... Gate, 50... Initialization circuit.

Claims (1)

[Claims] 1 Pass the input data through a digital filter,
In a downsampling circuit that converts frequencies by thinning out, the frequency conversion ratio (sampling frequency before processing/sampling frequency after processing) is smaller than the order of the filter,
A downsampling circuit comprising a filter coefficient generation circuit, a multiplier that multiplies sampling data and a filter coefficient, an adder that accumulates the multiplication results, and a data holding circuit that holds the accumulated data.