JPH02189620A - Down sampling circuit - Google Patents

Abstract

PURPOSE:To reduce the number of delay circuits by providing the sampling circuit with a filter factor generating circuit, a multiplexer for multiplexing the output of the factor generating circuit by sampling data, an adder for accumulating the multiplexed result, and a data holding circuit for holding the accumulated data. CONSTITUTION:Input data X0 are multiplexed by the 16th-order filter factor alpha16 through the multiplexer 14 and the multiplexed result is added to the value of the data holding circuit 17 by the adder 15. The initial values of both circuits 16, 17 are zero. Simultaneously, the value of the circuit 16 is transferred to the circuit 17 and the added result is transferred to the circuit 16 through an initializing circuit 19. Although the input of the circuit 19 is usually outputted as it is, zero is outputted in a period calculating an output signal Y. Consequently, the delay circuit for holding the past sampling data can be eliminated.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a sampling frequency conversion device for sampling data, and particularly to a downsampling circuit that thins out sampling data through a digital filter.

[Conventional technology]

FIG. 3 shows a block diagram of a general digital filter.

FIG. 4 shows a configuration diagram of a conventional down-sampling circuit using a digital filter.

As shown in Figure 3, the digital filter is a product-sum type that calculates the output by multiplying the current sampling data to several samples of past sampling data by each filter coefficient and accumulating the results. doing. In order to downsample it, the output data is thinned out.

The conventional downsampling circuit shown in FIG. 4 will be explained. First is the filter processing part.

At the same time that the input signal 41 is input, each data in the delay circuit 45 is transferred to the next delay circuit 45. Next, the filter coefficients sequentially output by the coefficient generation circuit 46 and each sampling data held by the delay circuit 45 are selected by the selection circuit 47 and multiplied by the multiplier 43.

The initial value of the delay circuit 45 is 0. Each sequentially multiplied data is accumulated by an adder 44 and then sent to an initialization circuit 50.
and is held in the data holding circuit 48. The initialization circuit 51 normally outputs the input as it is, but 0 is output at the same time as it is repeated for the number of orders of the filter, and the filter processing of one input data is completed. The data obtained through filter processing is down-sampled to an arbitrary frequency by passing it through a gate that opens at the desired sampling timing.

[Problem to be solved by the invention]

In the conventional downsampling circuit using a digital filter, as the order of the filter increases,
As the order of the filter increases, a delay circuit for retaining past sampling data is required, resulting in an increase in the scale of the hardware. Furthermore, due to the structure, calculations are also performed on data to be thinned out that is not related to the output, so the circuit must operate quickly, resulting in the problem of increased calculation power.

[Differences between the invention and the prior art]

In contrast to the conventional downsampling circuit described above, means for performing calculations that affect the output when one input data is input before the next input data is input;
The difference is that by providing a holding circuit for the accumulated data required for output, a delay circuit required for filter processing is not required.

[Means to solve problems]

The downsampling circuit according to the present invention includes a filter coefficient generation circuit, a multiplier that multiplies sampling data, an adder that accumulates the results, and a data holding circuit that holds the accumulated data.

〔Example〕

FIG. 1 is a block diagram showing an embodiment of a downsampling circuit according to the present invention. This is an example of a circuit that downsamples 64 KHz sampling data to 1/8 of 8 KHz while passing it through a 16th order filter.

FIG. 2 is a diagram showing input/output timing. X is the input, Y is the output, and α is the filter coefficient. The subscripts of X and Y indicate the passage of time, and the subscript of α indicates the order of the filter.

As shown in FIG. 2, input data Xo is output data Y-1
It affects two outputs, YO and YO.

An embodiment of the downsampling circuit according to the present invention will be described with reference to FIGS. 1 and 2. First of all, input signal
For O, necessary processing is performed to obtain the next output, output Y-1. Input data XO is the coefficient generation circuit 13
The multiplier 14 multiplies the 16th-order filter coefficient α16 output from the multiplier 14. The multiplication result and the value of the data holding circuit 17 are added by an adder 15.

The initial values of the data holding circuit 16 and data holding circuit 17 are 0.
It is. At the same time, the value of the data holding circuit 16 is transferred to the data holding circuit 17, and the addition result passes through the initialization circuit 19.
The data is transferred to the data holding circuit 16. The initialization circuit 19 normally outputs the input as it is, but 0 is output at the cycle in which the output signal Y is calculated.

Next, necessary processing is performed to obtain the output YO for the input signal XO. The process is the same as the first one except for the filter coefficients. The filter coefficient output from the filter coefficient generation circuit 13 is an eighth-order filter coefficient α8 shifted by eight orders. Multiplier 14 multiplies the input signal.

The multiplication result and the value of the data holding circuit 17 are added by an adder 15. At the same time, the value of the data holding circuit 16 is transferred to the data holding circuit 17, and the addition result is transferred to the initialization circuit 1.
9 and is transferred to the data holding circuit 16.

Similarly, from input signals X1 to X8, filter coefficient α
The output result Y-1 is obtained by processing while updating from α15 to α7. At this time, the data in the data holding circuit 16 is initialized to 0 by the initialization circuit 19, and the data holding circuit 17 holds intermediate results of cumulative data necessary to obtain the output YO. Furthermore, by repeating input signals X8 to X15, the output YO is obtained. At this time, the data in the data holding circuit 16 is initialized to O by the initialization circuit 19, and the data in the data holding circuit 17 is initialized to O by the initialization circuit 19.
holds intermediate results of accumulated data necessary to obtain the output Y1. By repeating this process, 1/8 downsampling through a digital filter can be performed.

〔Effect of the invention〕

As described above, the present invention can eliminate the delay circuits conventionally required in a downsampling circuit using a digital filter, and can reduce the scale of hardware.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram of a downsampling circuit showing one embodiment of the present invention, and FIG. 2 is an input/output timing diagram showing one embodiment of the present invention. FIG. 3 is a block diagram of a boat fishing filter. FIG. 4 is a block diagram of a conventional downsampling circuit. 11...Input signal, 12...Output signal, 13...Filter coefficient generation circuit, 14...
... Multiplier, 15 ... Adder, 16 ...
...gate, 17...data holding circuit, 18
......data holding circuit, 19...initialization circuit, 31...input signal, 32...output signal, 33...multiplier , 34... Adder, 35... Delay circuit, 41... Input signal, 42... Output signal, 43...
Multiplier, 44... Adder, 45... Delay circuit, 46... Filter coefficient generation circuit, 4
7... Selection circuit, 48... Data holding circuit, 49... Gate, 50... Initialization circuit. Agent Patent Attorney Uchihara Back 1 diagram xott2213r (Xjx&xqtlIt111xt
/mxt3ulx/! xi xrr7Zδρma x5rixr
tmxt Tsuro δa7ala! ata3ara/ Specific force Y-f Input X Figure 21

Claims (1)

[Claims] In a downsampling circuit that passes input data through a digital filter and converts the frequency by thinning out,
Frequency conversion ratio (sampling frequency before processing/
A circuit whose sampling frequency (after processing) is smaller than the filter order, which includes a filter coefficient generation circuit, a multiplier that multiplies the sampling data and filter coefficients, an adder that accumulates the multiplication results, and holds the accumulated data. A downsampling circuit characterized by having a data holding circuit.