JPH058646U - Memory device - Google Patents

Abstract

(57) [Summary] [Purpose] The sequencer performs the saving operation of the previous value, which was performed by the software of the CPU, instead of the sequencer.
Improve CPU performance. [Structure] Holding means for holding an address signal from a CPU, an address counter for generating an address signal, and a CP
A first multiplexer for selecting either the U address signal or the address from the address counter, a holding unit for holding the write data from the CPU, a read data holding unit for holding the data read from the memory unit, and C
A second multiplexer that selects one of PU address, write data, and read data, and an evacuation operation command from the CPU, and an access signal from the CPU, to the first and second multiplexers in a predetermined sequence. And a sequencer that outputs an access signal to the memory controller.

Description

[Detailed description of the device]

[0001]

[Industrial applications]

 The present invention relates to a memory device accessed by a microprocessor (CPU), and more particularly, to a memory device capable of efficiently storing the previous value of the memory contents in order to facilitate error retry of the CPU. ..

[0002]

[Prior Art]

 FIG. 5 is an operation conceptual diagram of the conventional apparatus when the CPU accesses the memory. When the CPU attempts to work using the data stored in the shaded area 11, the CPU first uses a unit with good memory content division (a unit that can be retried). The contents (previous value data) are saved / saved in the buffer area 12 provided for saving the previous value. Next, the CPU performs the work while writing or reading the current data in the hatched area 11. After that, the steps of and are repeated. When an error occurs during such work, the contents saved in the buffer area 12 are restored and the retry is performed.

[0003]

[Problems to be solved by the device]

 However, in such a conventional device, the CPU needs to perform the operation of writing the current value after saving the previous value in the buffer area in units that are well separated by software, and such data saving operation takes time. Therefore, there is a problem that the performance of the CPU is deteriorated. The present invention has been made in view of the above circumstances, and an object thereof is to provide a memory device that can easily perform a retry operation when an error occurs in the CPU and improve the performance of the CPU.

[0004]

[Means for Solving the Problems]

 The present invention that achieves such an object is to hold an address signal from a CPU in a memory device including a memory unit accessed from a CPU and a memory controller that controls writing and reading of data to and from the memory unit. CPU address holding means, an address counter for generating an address signal, a first multiplexer for selecting either the address signal from the CPU address holding means or the address from the address counter, and the write data from the CPU Write data holding means, read data holding means for holding data read from the memory section, address signal held by the CPU address holding means, write data held by the write data holding means, read data holding Select one of the read data held by the method. And a second multiplexer for receiving an evacuation operation command from the CPU and an access signal from the CPU, and a selection signal to the first and second multiplexers and an access signal to the memory controller in a predetermined sequence. Is a memory device characterized by being provided with a sequencer for outputting.

[0005]

[Action]

 Upon receiving the save operation command from the CPU, the sequencer reads the previous value from the memory unit and writes the previous value in the buffer area together with the address of the memory unit to be saved. It also outputs a timing signal for sequentially performing operations such as incrementing the address counter (buffer address) and writing the current value. As a result, the saving operation of the previous value of the memory is executed without depending on the software of the CPU.

[0006]

【Example】

 Embodiments of the present invention will be described in detail below with reference to the drawings. FIG. 1 is a configuration block diagram showing an embodiment of the present invention. In the figure, 1 is a memory unit accessed from a CPU (not shown), 2 is a memory controller that controls writing and reading of data to the memory unit 1, and is an address signal, data, and chip select signal C / S. , Read / write commands, etc. are applied. 3 is a CPU address holding means for holding an address signal from the CPU, 4 is an address counter (buffer address) for generating a signal for designating a memory address to the buffer area, and 5 is an address signal from the CPU address holding means 3. The first multiplexer selects any one of the buffer addresses from the address counter 4 and the address signal selected here is passed through the memory controller 2 to specify the address of the memory section 1. Reference numeral 6 is a write data holding means for holding the write data from the CPU, and 7 is a read data holding means for holding the data read from the memory section 1. The read data held here is also output to the CPU side. It A second multiplexer 8 selects one of the address signal held by the CPU address holding means 3, the write data held by the write data holding means 6 and the read data held by the read data holding means 7. The signal selected here is given to the memory controller 2. Reference numeral 9 is a control register for instructing a save operation which is set based on a command from the CPU, and 10 is an enable signal from the control register 9 and an access signal from the CPU. This is a sequencer that outputs selection signals to the second multiplexers 5 and 8 and access signals to the memory controller 2.

The control register 9 is set in response to a save operation command from the CPU, and outputs an enable signal to the sequencer 10. The sequencer 10 receives the enable signal from the control register 9, the address strobe signal AS from the CPU, the read / write command R / W, etc., and reads and saves the previous value from the memory unit 1. , Various timing signals for sequentially performing the operation of writing the previous value together with the address of the memory unit 1 in the buffer area, the increment operation of the address counter (buffer address) 4, and the writing of the current value. It is configured to output to the part.

The operation of the apparatus thus configured will be described next. (Normal Read / Write Operation) During a normal read / write operation, the CPU sets the control register 9 to be disabled. In this state, the sequencer 10 outputs to the memory controller 2 an address strobe AS and, for example, a write command in the case of write access. The first and second multiplexers 3 and 8 are instructed to select the address from the CPU address holding unit 3 and the write data from the CPU and output them to the memory controller 2. ing. As a result, the memory controller 2 performs an operation of writing the data to the designated address of the memory unit 1. In the case of read access, the data read from the memory unit 1 is held in the holding unit 7 and transferred to the CPU side. When some kind of error occurs during such a normal read / write operation, the CPU writes the contents of the control register 9 so as to perform a save operation for saving the previous value from the memory unit 1 to the buffer area. Set to enable.

(Saving Operation) FIG. 2 is a flowchart showing a saving operation for saving the previous value from the memory unit 1. Here, the operation indicated by the sequencer 10 in the case of write access from the CPU is shown as an example. When the contents of the control register 9 are set to enable, the holding means 3 holds the CPU address and the holding means 6 holds the write data (step 1). Next, the first multiplexer 5 is caused to select the CPU address, the read command is output, these are given to the memory unit 1 via the memory controller 2, and the previous value is read (step 2). Then, the read previous value is held in the holding means 7 (step 3). Then, the first multiplexer 3 selects the address of the address counter (buffer address) 4, the second multiplexer selects the CPU address, outputs the write command, and saves the address in the memory unit 1. Write (Step 4). Then, the address of the address counter (buffer address) 4 is incremented (step 5), and the first multiplexer 5 selects this buffer address. The second multiplexer 8 selects the previous value held in the holding means 7, outputs a write command, and writes this previous value in the memory section 1 (step 6). As a result, the previous value and its address are written in the buffer area, and the save operation is completed. Next, the address of the address counter (buffer address) 4 is incremented (step 7), and the first multiplexer 5 selects the CPU address held in the holding means 3 this time, and the second The multiplexer 8 selects the write data from the CPU held in the holding means 6. Then, the write command is output and the current value is written in the memory unit 1 (step 8).

FIG. 3 is a conceptual diagram showing a state of data written in the buffer area of the memory unit 1 by the above saving operation. The address where the data (previous value) was stored before the evacuation and the previous value are paired and written sequentially. FIG. 4 is a time chart during the saving operation for saving the previous value from the memory unit 1. (A)-(d) is a waveform diagram of each signal output from CPU, (e)-(h) is a waveform diagram of each signal given to the memory controller 2. As shown in this timing chart, the sequencer 10 reads the previous value, writes the CPU address and the previous value to the buffer area in the CPU write or read access cycle, and then writes to the address specified by the CPU. Write the value this time. Such a series of evacuation operation is performed by each constituent element receiving the timing signal from the sequencer 10, and during this time, the CPU can concentrate on other work.

[0011]

[Effect of the device]

 As described in detail above, according to the present invention, the sequencer performs the saving operation of the previous value, which was previously performed by the software of the CPU, instead of the previous value, so that the performance of the CPU can be improved.

[0012]

[Brief description of drawings]

FIG. 1 is a configuration block diagram showing an embodiment of the present invention.

FIG. 2 is a flowchart showing a previous value saving operation.

FIG. 3 is a conceptual diagram showing a state of data written in a buffer area.

FIG. 4 is a time chart during a save operation for saving the previous value from the memory unit.

FIG. 5 is an operation conceptual diagram of a conventional device when a CPU accesses a memory.

[Explanation of symbols]

 1 Memory Unit 2 Memory Controller 3 CPU Address Holding Means 4 Address Counter (Buffer Address) 5 First Multiplexer 6 Write Data Holding Means 7 Read Data Holding Means 8 Second Multiplexer 9 Control Register 10 Sequencer

Claims (1)

Claims for utility model registration: 1. A memory device comprising a memory unit accessed by a CPU and a memory controller for controlling writing and reading of data to and from the memory unit. CPU address holding means for holding, an address counter for generating an address signal, a first multiplexer for selecting either the address signal from the CPU address holding means or the address from the address counter, and the write data from the CPU Write data holding means, read data holding means for holding the data read from the memory section, and an address signal held by the CPU address holding means,
A second multiplexer for selecting one of the write data held by the write data holding means and the read data held by the read data holding means, and a save operation command from the CPU, and an access signal from the CPU. In response to the predetermined sequence,
A memory device provided with a sequencer for outputting a selection signal to a second multiplexer and an access signal to the memory controller.