JPH0587148B2 - - Google Patents
Info
- Publication number
- JPH0587148B2 JPH0587148B2 JP23055686A JP23055686A JPH0587148B2 JP H0587148 B2 JPH0587148 B2 JP H0587148B2 JP 23055686 A JP23055686 A JP 23055686A JP 23055686 A JP23055686 A JP 23055686A JP H0587148 B2 JPH0587148 B2 JP H0587148B2
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- differential amplifier
- transistor
- wiring
- amplifier circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004020 conductor Substances 0.000 claims description 20
- 238000010586 diagram Methods 0.000 description 12
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 230000003071 parasitic effect Effects 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 239000000470 constituent Substances 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Landscapes
- Amplifiers (AREA)
- Semiconductor Integrated Circuits (AREA)
- Bipolar Integrated Circuits (AREA)
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体集積回路で実現する差動増幅回
路に関する。特に差動対の構成素子を対称に配列
するときのレイアウトの改良に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a differential amplifier circuit realized by a semiconductor integrated circuit. In particular, it relates to improvements in layout when symmetrically arranging constituent elements of a differential pair.
回路のほぼ中央に電源電位の導体領域を設け、
この領域に対して対称な位置に正相側および逆相
側の回路素子が配置した差動増幅回路において、
上記導体領域をくり抜いて、ここに共通の電流
源となる素子の少なくとも一部を配置することに
より、
さらにバランス特性を改善するものである。
A conductor area for the power supply potential is provided approximately in the center of the circuit,
In a differential amplifier circuit in which circuit elements on the positive phase side and negative phase side are arranged symmetrically with respect to this area, the above conductor area is hollowed out and at least part of the elements serving as a common current source is placed here. This further improves the balance characteristics.
差動増幅回路はリニア集積回路の増幅回路や電
流切替スイツチング回路として非常に多く用いら
れている。集積回路では同一のシリコンチツプ上
に作られたトランジスタ、抵抗値などはそれぞれ
本質的に等しい。従つて差動増幅回路のようにト
ランジスタ、抵抗のバランス回路設計を必要とす
る回路は集積回路で実現するのに適している。さ
らに、差動増幅回路は直流から高周波までの増幅
ができ、最近は数百メガヘルツ帯からギガヘルツ
帯にかけての超高周波数領域でも使われるように
なつてきている。
Differential amplifier circuits are widely used as amplifier circuits and current switching circuits in linear integrated circuits. In integrated circuits, transistors and resistance values made on the same silicon chip are essentially the same. Therefore, circuits that require a balanced circuit design of transistors and resistors, such as differential amplifier circuits, are suitable for implementation with integrated circuits. Furthermore, differential amplifier circuits can amplify from direct current to high frequencies, and have recently come to be used in the ultra-high frequency range from hundreds of megahertz to gigahertz.
第4図は差動増幅回路の基本的回路を示し、ト
ランジスタQ1,Q2、抵抗R1,R2,R3の素子で構
成され、トランジスタQ1のベースが入力端子1、
トランジスタQ2のベースが入力端子2、トラン
ジスタQ1のコレクタが出力端子3、トランジス
タQ2のコレクタが出力端子4に接続され、抵抗
R1の一端はトランジスタQ1のコレクタに、他端
は高電位側電源線5に接続され、抵抗R2の一端
はトランジスタQ2のコレクタに、他端は前記高
電位側電源線5に接続され、抵抗R3の一端はQ1
およびQ2のエミツタに他端は低電位側電源線6
に接続されている。 Figure 4 shows the basic circuit of a differential amplifier circuit, which is composed of transistors Q 1 , Q 2 and resistors R 1 , R 2 , R 3 , with the base of transistor Q 1 connected to input terminal 1,
The base of transistor Q 2 is connected to input terminal 2, the collector of transistor Q 1 is connected to output terminal 3, the collector of transistor Q 2 is connected to output terminal 4, and the resistor
One end of R 1 is connected to the collector of transistor Q 1 and the other end is connected to the high potential side power line 5. One end of resistor R 2 is connected to the collector of transistor Q 2 and the other end is connected to the high potential side power line 5. and one end of resistor R 3 is Q 1
and the other end is the low potential side power supply line 6 to the emitter of Q2 .
It is connected to the.
従来、差動増幅回路のバランス設計としてはト
トランジスタおよび抵抗のバランス、および差動
の正相よび逆相の信号伝播遅延時間のバランスを
考慮して集積回路設計を行つていた。第5図は、
差動増幅回路の基本的回路である第4図の回路図
をシリコンチツプ上に実現する場合のレイアウト
配置図の従来例を示す。第5図においてバランス
設計として考慮してある点は、トランジスタQ1,
Q2、抵抗R1,R2の各素子を上下対称に配置する
こと、入力信号線11と入力信号線12の長さを
等しく、さらに出力信号線13と出力信号線14
の長さを等しくすることである。なお第5図のト
ランジスタQ1,Q2におけるCはコレクタ、Bは
ベース、Eはエミツタを示し、以下各図のC,
B,Eも同様である。 Conventionally, when designing the balance of a differential amplifier circuit, an integrated circuit has been designed by taking into consideration the balance of transistors and resistors, and the balance of differential positive-phase and negative-phase signal propagation delay times. Figure 5 shows
A conventional example of a layout diagram for realizing the circuit diagram of FIG. 4, which is a basic circuit of a differential amplifier circuit, on a silicon chip is shown. The points considered in the balance design in Fig. 5 are the transistors Q 1 ,
Q 2 , resistors R 1 and R 2 are arranged vertically symmetrically, the input signal line 11 and the input signal line 12 have the same length, and the output signal line 13 and the output signal line 14 have the same length.
The purpose is to make the lengths of the two equal. In the transistors Q 1 and Q 2 in Fig. 5, C indicates the collector, B indicates the base, and E indicates the emitter.
The same applies to B and E.
従来例第5図をさらに詳細に説明すると、中央
に低電位側電源線6が走り、その上部および下部
にそれぞれ高電位側電源線5,7が走つており、
低電位側電源線6と上部の高電位側電源線5の間
にトランジスタQ1と抵抗R1が配置され、低電位
側電源線6と下部の高電位側電源線7の間にトラ
ンジスタQ2と抵抗R2が配置され、抵抗R3はトラ
ンジスタQ1側に配置されている。このように、
抵抗R3がトランジスタQ1側に配置されているた
めに、トランジスタQ1のエミツタと抵抗R3の接
続配線15と、トランジスタQ2のエミツタと抵
抗R3の接続配線16の配線長を比較すると、後
者の接続配線16が長くなつている。接続配線1
5と接続配線16の配線長が異なることによつて
それぞれの布線インピーダンス(特に配線寄生容
量)が異なる。 To explain the conventional example in FIG. 5 in more detail, a low potential side power line 6 runs in the center, and high potential side power lines 5 and 7 run above and below it, respectively.
A transistor Q 1 and a resistor R 1 are arranged between the low potential side power line 6 and the upper high potential side power line 5, and a transistor Q 2 is arranged between the low potential side power line 6 and the lower high potential side power line 7. and a resistor R 2 are arranged, and a resistor R 3 is arranged on the transistor Q 1 side. in this way,
Since the resistor R 3 is placed on the transistor Q 1 side, comparing the wiring lengths of the connecting wire 15 between the emitter of the transistor Q 1 and the resistor R 3 and the connecting wire 16 between the emitter of the transistor Q 2 and the resistor R 3 , , the latter connection wiring 16 is longer. Connection wiring 1
The wiring impedance (particularly the wiring parasitic capacitance) differs due to the difference in wiring length between the wiring 5 and the connection wiring 16.
上述した従来のレイアウト配置図第5図は入力
端子から出力端子までの信号線の長さが等しく、
しかも信号線の長さが比較的短くなつているが、
接続配線15と接続配線16の長さが異なること
でそれぞれの配線インピーダンスのバランス設計
が実現できない欠点がある。特に、この接続配線
15と接続配線16の配線インピーダンスに関し
ては、配線部とシリコン基板間に存在する寄生容
量が差動増幅回路のバランスを妨げ、使用周波数
が数百メガヘルツ以上になると致命的な欠点とな
る。従つて差動増幅回路のバランス設計において
は、トランジスタ、抵抗値、信号線の配線長のバ
ランスのみでなく、他の配線の寄生容量のバラン
スを充分に考慮する必要がある。
In the conventional layout diagram shown in FIG. 5 mentioned above, the length of the signal lines from the input terminal to the output terminal is equal;
Moreover, the length of the signal line has become relatively short,
Since the lengths of the connection wiring 15 and the connection wiring 16 are different, there is a drawback that a balanced design of the respective wiring impedances cannot be realized. In particular, regarding the wiring impedance of the connection wiring 15 and the connection wiring 16, the parasitic capacitance that exists between the wiring part and the silicon substrate disturbs the balance of the differential amplifier circuit, which becomes a fatal drawback when the operating frequency exceeds several hundred megahertz. becomes. Therefore, in the balanced design of a differential amplifier circuit, it is necessary to fully consider not only the balance of transistors, resistance values, and wiring lengths of signal lines, but also the balance of parasitic capacitance of other wirings.
本発明はこれを改良するもので、回路バランス
状態をさらに改善する差動増幅回路を提供するこ
とを目的とする。 The present invention improves on this, and aims to provide a differential amplifier circuit that further improves the circuit balance state.
本発明は、回路のほぼ中央に電源の片側の電位
に接続される細長い導体領域が設けられ、この導
体領域を境にしてほぼ対称な位置に、正相側およ
び逆相側の回路素子が配置された差動増幅回路に
おいて、上記正相側および逆相側の回路素子に共
通に与える電流の電流源となる素子の少なくとも
一部が、上記導体領域をくり抜いて設けたエリア
内に配置されたことを特徴とする。
In the present invention, an elongated conductor region connected to the potential on one side of the power supply is provided approximately in the center of the circuit, and circuit elements on the positive phase side and negative phase side are arranged at approximately symmetrical positions with this conductor region as a border. In the differential amplifier circuit, at least a part of an element that serves as a current source for a current commonly applied to the circuit elements on the positive phase side and the negative phase side is arranged in an area provided by hollowing out the conductor region. It is characterized by
正相側および逆相側に共通に電流源となる回路
素子の一部または全部を、導体領域内にくり抜い
て設けたエリア内に配置することにより、回路配
置が対称になるとともにこの回路素子は導体によ
り遮蔽され、一方の側に片寄つて影響を与えるこ
とがなくなる。
By arranging part or all of the circuit element that serves as a common current source for the positive phase side and the negative phase side in an area cut out within the conductor region, the circuit layout becomes symmetrical and the circuit element It is shielded by the conductor, so it will not be biased to one side.
次に、本発明について図面を用いて説明する。 Next, the present invention will be explained using the drawings.
第1図は本発明の実施例の配置図である。中央
に低電位側の電源電位となる導体領域6が配置さ
れ、この導体領域6の一部がくり抜かれ非配線部
のエリア10が設けられる。このエリア10内に
正相側および逆相側に共通に電流を供給する抵抗
R3を配置してある。導体領域6と高電位側の導
体5の間に差動増幅回路の正相側トランジスタ
Q1および抵抗R1が配置され、導体領域6と下部
高電位側電源線7の間に差動増幅回路の逆相側ト
ランジスタQ2および抵抗R2が配置される。 FIG. 1 is a layout diagram of an embodiment of the present invention. A conductor region 6 having a power supply potential on the low potential side is arranged in the center, and a part of the conductor region 6 is hollowed out to provide a non-wiring area 10. A resistor that commonly supplies current to the positive phase side and negative phase side within this area 10
R 3 is placed. A positive phase side transistor of the differential amplifier circuit is connected between the conductor region 6 and the high potential side conductor 5.
Q 1 and a resistor R 1 are arranged, and a negative phase side transistor Q 2 and a resistor R 2 of the differential amplifier circuit are arranged between the conductor region 6 and the lower high potential side power supply line 7.
このように導体領域6の一部をくり抜いてエリ
ア10を設け、このエリア10の中に抵抗R3を
配置することにより、トランジスタQ1,Q2よび
抵抗R1,R2,R3が対称に配置され、トランジス
タおよび抵抗のバランス設計、入力端子から出力
端子までの信号線の長さに関する正相および逆相
のバランス設計、さらには入出力信号配線以外の
配線8,9のバランス設計が実現される。 In this way, by hollowing out a part of the conductor region 6 to provide the area 10 and arranging the resistor R 3 in this area 10, the transistors Q 1 and Q 2 and the resistors R 1 , R 2 , and R 3 are made symmetrical. This realizes a balanced design for transistors and resistors, a balanced design for positive phase and negative phase regarding the length of the signal line from the input terminal to the output terminal, and a balanced design for the wiring 8 and 9 other than the input/output signal wiring. be done.
第2図および第3図は、本発明の他の実施例回
路図および配置図である。トランジスタQ102,
Q103,Q104、抵抗R103,R104,R105の各素子によ
つて差動増幅回路を構成してある。 2 and 3 are circuit diagrams and layout diagrams of other embodiments of the present invention. Transistor Q 102 ,
A differential amplifier circuit is configured by each element Q 103 , Q 104 and resistors R 103 , R 104 , and R 105 .
第3図に示すように、低電位側の電源導体領域
6の一部をくり抜いて設けられたエリア104
に、正相側および逆相側に共通なトランジスタ
Q101,Q104、抵抗R102,R105を配置する。図中2
×R101および2×R108は抵抗値がR101およびR108
のそれぞれ2倍の値であることを示す。 As shown in FIG. 3, an area 104 is provided by hollowing out a part of the power supply conductor region 6 on the low potential side.
, a transistor common to the positive and negative phase sides
Q 101 , Q 104 and resistors R 102 and R 105 are arranged. 2 in the diagram
×R 101 and 2 × R 108 have resistance values of R 101 and R 108
It shows that each value is twice the value of .
以上説明したように、本発明によれば、回路の
配置対称性がきわめてよくなるとともに、共通の
部分は電源導体で遮蔽されるから、一方に片寄つ
て影響を与えることがなくなり、きわめてよいバ
ランス特性が得られる。
As explained above, according to the present invention, the symmetry of the circuit arrangement is extremely good, and the common parts are shielded by the power supply conductor, so there is no biased influence on one side, and extremely good balance characteristics are achieved. can get.
第1図は本発明の実施例差動増幅回路の配置
図。第2図は本発明第2実施例回路図。第3図は
本発明第2実施例の配置図。第4図は差動増幅回
路の基本回路図。第5図は従来の差動増幅回路の
レイアウト図。
1,2,101,102……入力端子、3,
4,103……出力端子、5,7……高電位側電
源の導体、6……低電位側電源の導体領域、8,
9……配線、10,104……繰り抜いて設けた
エリア、11〜16……配線、Q1,Q2,Q101〜
Q108……トランジスタ、R1,R2,R3,R101〜
R108……抵抗。
FIG. 1 is a layout diagram of a differential amplifier circuit according to an embodiment of the present invention. FIG. 2 is a circuit diagram of a second embodiment of the present invention. FIG. 3 is a layout diagram of a second embodiment of the present invention. Figure 4 is a basic circuit diagram of a differential amplifier circuit. FIG. 5 is a layout diagram of a conventional differential amplifier circuit. 1, 2, 101, 102...input terminal, 3,
4,103...Output terminal, 5,7...Conductor of high potential side power supply, 6...Conductor region of low potential side power supply, 8,
9... Wiring, 10, 104... Area cut out, 11 to 16... Wiring, Q 1 , Q 2 , Q 101 ~
Q 108 ...Transistor, R 1 , R 2 , R 3 , R 101 ~
R 108 ...Resistance.
Claims (1)
れる細長い導体領域が設けられ、この導体領域を
境にしてほぼ対称な位置に、正相側および逆相側
の回路素子が配置された差動増幅回路において、 上記正相側および逆相側の回路素子に共通に与
える電流の電流源となる素子の少なくとも一部
が、上記導体領域をくり抜いて設けたエリア内に
配置された ことを特徴とする差動増幅回路。[Claims] 1. An elongated conductor region connected to the potential of one side of the power supply is provided approximately in the center of the circuit, and circuits on the positive phase side and negative phase side are located at approximately symmetrical positions with this conductor region as a border. In the differential amplifier circuit in which the elements are arranged, at least a part of the element that serves as a current source for the current commonly applied to the circuit elements on the positive phase side and the negative phase side is located in an area provided by hollowing out the conductor region. A differential amplifier circuit characterized in that:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23055686A JPS6384307A (en) | 1986-09-29 | 1986-09-29 | Differential amplifier circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23055686A JPS6384307A (en) | 1986-09-29 | 1986-09-29 | Differential amplifier circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6384307A JPS6384307A (en) | 1988-04-14 |
| JPH0587148B2 true JPH0587148B2 (en) | 1993-12-15 |
Family
ID=16909606
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP23055686A Granted JPS6384307A (en) | 1986-09-29 | 1986-09-29 | Differential amplifier circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6384307A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW579576B (en) * | 2001-10-24 | 2004-03-11 | Sanyo Electric Co | Semiconductor circuit |
| TWI221656B (en) * | 2001-10-24 | 2004-10-01 | Sanyo Electric Co | Semiconductor integrated circuit device |
-
1986
- 1986-09-29 JP JP23055686A patent/JPS6384307A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6384307A (en) | 1988-04-14 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP4206589B2 (en) | Distributed amplifier | |
| JP2964975B2 (en) | High frequency switch circuit | |
| US4926066A (en) | Clock distribution circuit having minimal skew | |
| JPH05251963A (en) | High gain monolithic microwave integrated circuit amplifier | |
| US6064253A (en) | Multiple stage self-biasing RF transistor circuit | |
| US6380644B1 (en) | Switching circuitry providing improved signal performance at high frequencies and method of operation thereof | |
| JPH0587148B2 (en) | ||
| US5627495A (en) | Topography for integrated circuit operational amplifier | |
| EP0407778B1 (en) | Hybrid amplifier | |
| US5475327A (en) | Variable impedance circuit | |
| US4786881A (en) | Amplifier with integrated feedback network | |
| US3500262A (en) | Nonreciprocal gyrator network | |
| JP4031032B2 (en) | Electronic integrated circuit device having means to compensate for undesired capacitance | |
| US4578629A (en) | Monolithic microwave "split load" phase inverter for push-pull monolithic FET amplifier circuits | |
| JP2762850B2 (en) | Semiconductor integrated circuit | |
| US6351015B1 (en) | Transistor device of MOS structure in which variation of output impedance resulting from manufacturing error is reduced | |
| JPS62208704A (en) | Constant current circuit | |
| GB2078038A (en) | Superheterodyne receivers | |
| JP2570050B2 (en) | Digital circuit | |
| JPH11204728A (en) | High frequency semiconductor device | |
| JPS5991713A (en) | Switching amplifier | |
| GB1585079A (en) | Microwave circuits incorporating transistors | |
| JPH02260561A (en) | Semiconductor device | |
| JPS624343A (en) | Master-slice-type semiconductor integrated circuit device | |
| JP2000124741A (en) | Amplifier circuit |