JPH05876B2 - - Google Patents
Info
- Publication number
- JPH05876B2 JPH05876B2 JP63320648A JP32064888A JPH05876B2 JP H05876 B2 JPH05876 B2 JP H05876B2 JP 63320648 A JP63320648 A JP 63320648A JP 32064888 A JP32064888 A JP 32064888A JP H05876 B2 JPH05876 B2 JP H05876B2
- Authority
- JP
- Japan
- Prior art keywords
- copper plating
- hole
- plating film
- forming
- solder resist
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/42—Plated through-holes or plated via connections
- H05K3/425—Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern
- H05K3/427—Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern initial plating of through-holes in metal-clad substrates
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、高密度化に最適なプリント回路板の
製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a printed circuit board that is optimal for high density.
プリント回路板を製造するには、従来、18〜
35μmの銅箔上に30μm前後の電気銅めつきを析出
させ、ドライフイルムを用いたテンテイング法ま
たは孔埋めによる印刷法により回路形成後エツチ
ングにて回路を独立させていた。
Traditionally, manufacturing printed circuit boards requires 18 to
Electrolytic copper plating of around 30 μm was deposited on a 35 μm copper foil, and circuits were formed using a tenting method using a dry film or a printing method by filling holes, and then etched to make the circuits independent.
しかし、高密度のプリント回路板に上記従来技
術を適用した場合、次のような問題が生じる。プ
リント回路板を高密度化すると必然的にスルーホ
ール孔径が小さくなるが、この場合、エツチング
レジストを形成する際の位置ずれが問題となる。
エツチングレジストを形成する前にスルーホール
にめつきをした場合、位置ずれを起こすとスルー
ホール内にエツチング液が入り込み、スルーホー
ル内のめつき及び銅箔層が侵食されるのである。
この状況を第１１図に示す。第１１図においてａ
は、エツチング中のスルーホール部断面図、ｂ
は、エツチング後の同断面図であり、ドライフイ
ルム５の左方向のずれにより、スルーホール内に
エツチング液１２が浸入し、スルーホール内のめ
つき層４及び銅箔層１が侵食されている。 However, when the above-mentioned conventional technology is applied to a high-density printed circuit board, the following problems occur. When the density of a printed circuit board is increased, the diameter of the through hole inevitably becomes smaller, but in this case, positional deviation when forming an etching resist becomes a problem.
If the through holes are plated before forming the etching resist, if misalignment occurs, the etching solution will enter the through holes, corroding the plating and copper foil layer inside the through holes.
This situation is shown in FIG. In Figure 11, a
is a sectional view of the through-hole part during etching, b
is the same cross-sectional view after etching. Due to the leftward shift of the dry film 5, the etching liquid 12 has penetrated into the through hole, corroding the plating layer 4 and the copper foil layer 1 inside the through hole. .
しかし、だからといつてめつきをエツチング後
に行なうと、回路部分は、第１２図のようにな
り、ライン幅の増大につながる。第１２図におい
ては、エツチングにより独立した銅張り層板の銅
箔１の側面にもめつき層１３が付着し、ライン幅
が増加している。 However, if plating is performed after etching for this reason, the circuit portion will become as shown in FIG. 12, leading to an increase in line width. In FIG. 12, the plating layer 13 is attached to the side surface of the copper foil 1 of the independent copper-clad laminate by etching, and the line width is increased.
一方、第８図にＡで示すように電気めつきで
は、めつき厚バラツキが大きく（第８図中、Ａ
は、電気めつきによる銅めつき厚と厚さのバラツ
キの関係、Ｂは、化学めつきによる銅めつき厚と
厚さのバラツキの関係を示す）、それが第１０図
に示す銅厚と最小ライン幅の関係図中の、最小ラ
イン幅のバラツキの増加となつてしまう。（第１
０図は、エツチングレジストにドライフイルムを
用い、アルカリ型のエツチング液を使用したとき
の銅厚と最小ライン幅の関係を示す）。さらに、
高密度化が要求されてくると必然的にスルーホー
ル孔径も小さくなり、相対的な板厚が増加するこ
ととなる。電気めつきを用いる場合、均一電着性
が悪く、孔径が小さくなるにつれスルーホール内
のめつきが薄くなり、スルーホール強度の劣化と
なる。そのため、従来の電気めつきによるプリン
ト回路板の製造方法では、スルーホールの孔径
は、0.6mmが限度であつた。その関係を第９図に
示す。第９図において、Ａ及びＢは、第８図にお
けると同様に、それぞれ電気めつき及び化学めつ
きについての銅めつき厚と厚さのバラツキの関係
を示す。従つて、必然的に高密度のプリント回路
板では、化学銅めつきを用いることとなるのであ
るが、化学銅めつきは、めつき膜の形成に時間を
要するので、効率的に行なうことが必要である。 On the other hand, in electroplating, as shown by A in Fig. 8, there is a large variation in plating thickness (A in Fig. 8).
(B shows the relationship between the copper plating thickness and thickness variation due to electroplating, and B indicates the relationship between the copper plating thickness and thickness variation due to chemical plating), which is the relationship between the copper thickness and the thickness shown in Figure 10. This results in an increase in the variation in the minimum line width in the minimum line width relationship diagram. (1st
Figure 0 shows the relationship between the copper thickness and the minimum line width when a dry film is used as the etching resist and an alkaline etching solution is used. moreover,
When higher density is required, the diameter of the through-hole inevitably becomes smaller, and the relative thickness of the plate increases. When electroplating is used, uniform electrodeposition is poor, and as the hole diameter becomes smaller, the plating inside the through hole becomes thinner, resulting in deterioration of the through hole strength. Therefore, in the conventional method of manufacturing printed circuit boards by electroplating, the diameter of the through hole is limited to 0.6 mm. The relationship is shown in FIG. In FIG. 9, A and B indicate the relationship between copper plating thickness and thickness variation for electroplating and chemical plating, respectively, as in FIG. 8. Therefore, chemical copper plating is inevitably used for high-density printed circuit boards, but chemical copper plating takes time to form a plating film, so it is difficult to perform it efficiently. is necessary.
しかし、上記従来技術に化学銅めつきを適用し
た場合、スルーホール部の銅層を必要な厚さまで
形成しようとすると、銅箔上には必要以上の化学
銅めつきが形成され、効率的でないばかりか、エ
ツチング時における、銅箔上の化学銅めつきの厚
さが厚すぎ、良好な回路ラインを形成することが
できない。 However, when chemical copper plating is applied to the above conventional technology, when trying to form the copper layer in the through-hole part to the required thickness, more chemical copper plating than necessary is formed on the copper foil, which is not efficient. Moreover, the thickness of the chemical copper plating on the copper foil during etching is too thick, making it impossible to form good circuit lines.
そこで、これらの問題を解決する方法として、
めつきをスルーホール部及びランド部ののみに限
ることが考えられる。 Therefore, as a way to solve these problems,
It is conceivable to limit plating to only through-hole portions and land portions.
しかし、露光法によりソルダーレジスト層を形
成することによりスルーホール及びランド部のみ
にめつきする場合に新たな問題が生ずる。以下こ
のことについて説明する。
However, a new problem arises when forming a solder resist layer using an exposure method and plating only through holes and land portions. This will be explained below.
露光法によりソルダーレジスト層を形成するに
は、まず未硬化のソルダーレジストを基板全面に
塗布し、ソルダーレジストの不要な部分に露光マ
スクを施し、次に紫外光照射し、露光マスクのな
い部分を硬化させる方法が取られる。 To form a solder resist layer using the exposure method, first apply uncured solder resist to the entire surface of the substrate, apply an exposure mask to the unnecessary parts of the solder resist, and then irradiate the solder resist with ultraviolet light to remove the parts without the exposure mask. A method of hardening is used.
そこで問題となるのが、第１３図に示すような
露光マスク１５のない部分からスルーホール内へ
の紫外光１４の漏れである。この漏れにより、ス
ルーホール内に付着したソルダーレジスト１６を
も硬化させてしまうのである。これは、高密度の
プリント回路板特有の問題である。 The problem here is that ultraviolet light 14 leaks into the through-hole from the portion where the exposure mask 15 is not provided, as shown in FIG. This leakage also hardens the solder resist 16 adhering to the inside of the through hole. This is a problem unique to high density printed circuit boards.
上記問題を解決するため、本発明では、露光法
によりソルダーレジスト層を形成する前に、薄い
銅層を予め形成したのである。
In order to solve the above problem, in the present invention, a thin copper layer is previously formed before forming a solder resist layer by an exposure method.
露光マスクのない部分からの紫外光の漏れは、
予め形成した薄い銅層によつて遮断され、スルー
ホール内に付着したソルダーレジストを硬化させ
ることはない。
Leakage of ultraviolet light from areas without an exposure mask is
The pre-formed thin copper layer blocks the solder resist deposited inside the through-holes from hardening.
以下に、実施例を用いて本発明を一層詳しく説
明するが、それは例示にすぎず、本発明の枠を超
えることなく、いろいろな変形や改良があり得る
ことは、勿論である。
The present invention will be described in more detail below using examples, but these are merely illustrative, and it goes without saying that various modifications and improvements can be made without going beyond the scope of the present invention.
第１図に示す樹脂板２の両面に18μmまたは
35μmの銅箔を有する積層板にドリルまたはパン
チングにてスルーホール孔３をあけ、第２図のよ
うにする。孔あけ後処理としてバリ除去を行なつ
た後、表面及び孔内を含め全面を脱脂、清浄化、
触媒付与を施し、硫酸銅、錯化剤ベースの還元性
化学銅めつき浴に浸漬し、第３図のごとく銅めつ
き膜４を２〜10μmも析出させる。この銅めつき
が、後に紫外光遮断の役割をする。エツチング液
のスルーホール内への浸入を防ぐためスルーホー
ル孔３内にアルカリ可溶型インク１１を挿入した
後、そのものにドライフイルム５を用いた露光法
にてテンテイングを行ない、第４図のように回路
形成する。アンモニウム水、塩化アンモニウムよ
りなるアルカリエツチング液にて回路以外の銅を
溶解除去し、ドライフイルム５を塩化メチレン等
を用いて剥離し、独立ライン６及びランド部７を
形成し、アルカリ可溶型インク１１を溶解除去
し、第５図に示すように回路を独立させる。エポ
キシ樹脂をベースにした高耐薬品性のソルダーレ
ジストめつきレジスト９をランド部７及びスルー
ホール部８を除く全面に露光法により形成する。
この際、先に形成したスルーホール内の銅めつき
層４が第１３図における紫外光１４の遮断の役割
をする。露光マスク１５のない部分からの紫外光
１４の漏れは、先に形成した薄い銅めつき層４に
よつて遮断され、スルーホール３内に付着したソ
ルダーレジストを硬化させることはない。こうし
て、第６図のようにした後、露出しているランド
部７及びスルーホール部８に再度硫酸銅、錯化剤
ベースの化学銅めつき浴に浸漬する方法で、銅め
つき膜１０を厚さ15〜30μmt2析出させ、第７図
のごとくなる。スルーホール部の銅めつき膜４，
１０の膜圧t3はt1＋t2となる。 18μm or
A through hole 3 is made by drilling or punching in a laminate having a 35 μm copper foil, as shown in FIG. 2. After removing burrs as a post-drilling process, the entire surface, including the surface and inside of the hole, is degreased, cleaned,
A catalyst is applied thereto and immersed in a reducing chemical copper plating bath based on copper sulfate and a complexing agent to deposit a copper plating film 4 with a thickness of 2 to 10 μm as shown in FIG. This copper plating will later serve as a shield against ultraviolet light. After inserting the alkali-soluble ink 11 into the through-hole hole 3 to prevent the etching liquid from entering the through-hole, tenting is carried out using an exposure method using a dry film 5, as shown in FIG. form a circuit. Copper other than the circuit is dissolved and removed using an alkaline etching solution consisting of ammonium water and ammonium chloride, and the dry film 5 is peeled off using methylene chloride or the like to form independent lines 6 and land portions 7, and alkali-soluble ink is removed. 11 is dissolved and removed to make the circuit independent as shown in FIG. A highly chemically resistant solder resist plating resist 9 based on epoxy resin is formed on the entire surface except for the land portions 7 and through-hole portions 8 by an exposure method.
At this time, the copper plating layer 4 in the previously formed through hole serves to block the ultraviolet light 14 in FIG. 13. Leakage of the ultraviolet light 14 from the areas where the exposure mask 15 is not present is blocked by the previously formed thin copper plating layer 4, and the solder resist deposited inside the through holes 3 will not be hardened. After completing the process as shown in FIG. 6, the exposed land portions 7 and through-hole portions 8 are again dipped in a chemical copper plating bath based on copper sulfate and a complexing agent to coat the copper plating film 10. It was deposited to a thickness of 15 to 30 μm, and the result was as shown in Fig. 7. Copper plating film 4 in through-hole area,
The membrane pressure t 3 of 10 becomes t 1 +t 2 .
本発明によれば、ソルダレジスト（めつきレジ
スト）の前後に化学銅めつきを形成、つまりスル
ーホール部に第１、第２の化学銅めつきをまた、
回路部に第１の化学銅めつきを形成し、かつ該回
路部を含む部分に上記スルーホール部及び上記ラ
ンド部を除いてソルダレジストを形成すること
で、例えば、2.54mm間に0.1mm幅ラインを４本描
画という回路精度（良好な回路ライン）を有し、
0.3mm孔径のスルーホールをもつという従来にな
し得なかつた非常に高密度の高いプリント回路板
を製造することができ、また、スルーホール部に
おける化学銅めつきの二層化による半田付け性の
向上等が図れ、安定した状態で高品質な高密度プ
リント回路板が得られると共に、銅めつきの面積
が小さいため、めつき材料費等からみて効率的な
めつきが可能となり、製造コストとして銅めつき
を溶解する量の低減、銅めつき析出量の低減等に
よる低コストが図れる。また更には、上記ソルダ
レジスト形成前に、第１の銅めつき層を形成する
工程に基づけば、ソルダレジストの硬化に起因す
る第２の銅めつき層の形成不良及びスルーホール
導通性の高信頼化を図ることができる等の効果が
ある。
According to the present invention, chemical copper plating is formed before and after the solder resist (plating resist), that is, first and second chemical copper plating is also applied to the through-hole portion.
By forming the first chemical copper plating on the circuit part and forming a solder resist on the part including the circuit part except for the through-hole part and the land part, for example, a width of 0.1 mm is formed between 2.54 mm. It has circuit accuracy of drawing 4 lines (good circuit line),
It is possible to manufacture extremely high-density printed circuit boards that have through-holes with a diameter of 0.3 mm, which was previously impossible, and also improves solderability by using two layers of chemical copper plating in the through-hole areas. etc., it is possible to obtain a high-quality, high-density printed circuit board in a stable state, and since the copper plating area is small, efficient plating is possible in terms of plating material costs, etc., and copper plating is reduced in manufacturing costs. Costs can be reduced by reducing the amount of copper to be dissolved and the amount of copper plating deposited. Furthermore, based on the step of forming the first copper plating layer before forming the solder resist, formation defects of the second copper plating layer due to hardening of the solder resist and high through-hole conductivity may occur. This has the effect of increasing trust.
第１図から第７図までは本発明によるプリント
回路板の製造方法を示す断面図、第８図は、平均
銅めつき厚と銅めつき厚バラツキの間の関係を示
すダイヤグラム、第９図は、孔径／板厚比と均一
電着性の間の関係を示すダイヤグラム、第１０図
は、銅厚とエツチング後最小ライン幅の間の関係
を示すダイヤグラム、第１１図は、エツチングレ
ジストの位置ずれしたときの状態を示す図、第１
２図は、エツチング後に回路部分にめつきを行な
つたときの状態を示す図、第１３図は、光マスク
のない部分からスルーホール内への紫外光の漏れ
の様子を示す図である。
符号の説明、１……銅張り積層板の銅箔、２…
…銅張り積層板の樹脂板、３……スルーホール
孔、４……パネル化学銅めつき層、５……ドライ
フイルム、６……独立ライン、７……ランド部、
８……スルーホール部、９……ソルダーレジス
ト、１０……化学銅めつき膜、１１……アルカリ
可溶型インク、１２……エツチング液、１３……
めつき層、１４……紫外光、１６……未硬化のソ
ルダーレジスト、１７……露光マスク。
1 to 7 are cross-sectional views showing the method for manufacturing a printed circuit board according to the present invention, FIG. 8 is a diagram showing the relationship between average copper plating thickness and copper plating thickness variation, and FIG. 9 is a diagram showing the relationship between average copper plating thickness and copper plating thickness variation. 10 is a diagram showing the relationship between the hole diameter/thickness ratio and uniform electrodeposition. FIG. 10 is a diagram showing the relationship between copper thickness and minimum line width after etching. FIG. 11 is a diagram showing the relationship between the etching resist position. Diagram showing the state when misaligned, 1st
FIG. 2 is a diagram showing the state when the circuit portion is plated after etching, and FIG. 13 is a diagram showing the leakage of ultraviolet light from the portion without the optical mask into the through hole. Explanation of symbols, 1... Copper foil of copper-clad laminate, 2...
...Resin plate of copper-clad laminate, 3...Through hole, 4...Panel chemical copper plating layer, 5...Dry film, 6...Independent line, 7...Land part,
8...Through hole part, 9...Solder resist, 10...Chemical copper plating film, 11...Alkali-soluble ink, 12...Etching liquid, 13...
Plating layer, 14... Ultraviolet light, 16... Uncured solder resist, 17... Exposure mask.
Claims (1)
工程と、 回路となる部分及びランド部にエツチングレジ
ストを形成する工程と、 エツチングにより、回路となる部分及びランド
部の銅層を独立させる工程と、 上記回路部分を含む部分に、上記ランド部及び
上記スルーホール部を除いて、ソルダーレジスト
層を形成する工程と、 上記スルーホール部のスルーホール内および上
記回路部分に、第１の化学銅めつき膜を施す工程
と、 上記ランド部及び上記スルーホール部のスルー
ホール内の第１の化学銅めつき膜上に、スルーホ
ール導通のための第２の化学銅めつき膜を形成す
る工程と、 からなり、 上記ソルダーレジスト層を形成する前に、上記
第１の化学銅めつき膜を施し、上記ソルダーレジ
スト層を形成した後に、上記第２の化学銅めつき
膜を施し、上記第１の化学銅めつき膜t1は、上記
第２の化学銅めつき膜t2よりも薄く形成し、上記
スルーホール部のスルーホール内の化学銅めつき
膜厚t3を厚く、上記回路部の化学銅めつき膜厚t1
を薄く形成したことを特徴とするプリント回路板
の製造方法。[Claims] 1. A step of forming through holes in a double-sided copper-clad laminate, a step of forming an etching resist on the portions that will become the circuit and the land portions, and a step of etching the copper layer of the portions that will become the circuit and the land portions. a step of forming a solder resist layer in a portion including the circuit portion, excluding the land portion and the through hole portion; and a step of forming a solder resist layer in the through hole of the through hole portion and in the circuit portion. a second chemical copper plating film for through-hole conduction on the first chemical copper plating film in the through holes of the land portion and the through hole portion; forming the first chemical copper plating film before forming the solder resist layer, and applying the second chemical copper plating film after forming the solder resist layer. The first chemical copper plating film t 1 is formed thinner than the second chemical copper plating film t 2 , and the chemical copper plating film thickness t 3 inside the through hole of the through hole portion is Thick, chemical copper plating film thickness of the above circuit part t 1
A method for manufacturing a printed circuit board, characterized in that the printed circuit board is formed thinly.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP32064888A JPH01302795A (en) | 1988-12-21 | 1988-12-21 | Printed circuit board manufacturing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP32064888A JPH01302795A (en) | 1988-12-21 | 1988-12-21 | Printed circuit board manufacturing method |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8484682A Division JPS58202589A (en) | 1982-05-21 | 1982-05-21 | Printed circuit board manufacturing method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH01302795A JPH01302795A (en) | 1989-12-06 |
| JPH05876B2 true JPH05876B2 (en) | 1993-01-06 |
Family
ID=18123758
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP32064888A Granted JPH01302795A (en) | 1988-12-21 | 1988-12-21 | Printed circuit board manufacturing method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01302795A (en) |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS554956A (en) * | 1978-06-28 | 1980-01-14 | Oki Electric Ind Co Ltd | Method of manufacturing printed circuit board |
| JPS5518072A (en) * | 1978-07-26 | 1980-02-07 | Chiyou Lsi Gijutsu Kenkyu Kumiai | Mos semiconductor device |
| JPS5752196A (en) * | 1980-09-16 | 1982-03-27 | Hitachi Ltd | Method of producing printed board |
| JPS58202589A (en) * | 1982-05-21 | 1983-11-25 | 株式会社日立製作所 | Printed circuit board manufacturing method |
-
1988
- 1988-12-21 JP JP32064888A patent/JPH01302795A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPH01302795A (en) | 1989-12-06 |
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