JPH05884B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a booster circuit for an operational amplifier that can drive a large current without losing the original functions of a CMOS operational amplifier.

Conventional CMOS operational amplifiers lose their gain when the drive current is increased, making it impossible to maintain the functionality of conventional CMOS operational amplifiers.

As a conventional example, FIG. 1 shows a CMOS operational amplifier circuit. Since the output of this operational amplifier is of a type composed of a Pch transistor 10 and an Nch transistor 13, the transistors in this output stage cannot operate in the saturated region, but operate in the non-saturated region.

Therefore, the gain at this output stage is reduced, and the gain of the entire operational amplifier is reduced by Pch transistors 4, 5,
The main gain is the gain of the differential stage composed of Nch transistors 6, 7, and 8. Therefore, even if a sufficiently stable voltage level is applied to the input, the gain of the operational amplifier itself decreases, and the error in the output voltage level with respect to the input voltage level increases. In this way, in a single conventional operational amplifier, the output stage is of a complementary type, so when the drive current increases, the gain decreases, which is undesirable.

The present invention relates to a booster circuit that compensates for the drawbacks of such CMOS operational amplifiers.

An object of the present invention is to enable large current drive while maintaining the output at a highly accurate voltage level, and also to not impair the dynamic range.

The present invention connects the output of a CMOS operational amplifier to the gate of a MOS transistor and uses only the gate capacitance as the load, thereby enabling large current drive without reducing the gain of the CMOS operational amplifier.

FIG. 2 shows an embodiment of the present invention.

The booster circuit for the CMOS operational amplifier of the present invention is
Operate one channel transistor of the Pch transistor 26 or the Nch transistor 21,
Resistors 24 and 22 are used to increase drive capability. This resistor is used for the purpose of normal operation of the MOS transistor, current limit, and stable operation of the entire device when used as a buffer configuration.

Furthermore, in the case of only one MOS transistor and one resistor, the dynamic range of the operational amplifier is narrowed, so in the present invention, an Nch transistor 27 and a Pch transistor 20 are used, and a Pch transistor 26 and a resistor 24 are used, respectively. Current drive circuit, Nch transistor 21 and resistor 22
The output level of the operational amplifier is changed to inverter 1.
9 is detected and turned ON. This makes it possible to drive large currents without impairing the operational amplifier's dynamic range. Furthermore, if a normal inverter configuration is adopted, the Pch and Nch transistors become conductive at the same time when the input signal is inverted, causing short current to flow between the power supplies and causing noise.
In order to control the Nch transistor 27 with a signal obtained by delaying the input signal by the inverter 19, the Nch transistor 21 is
Even if the Pch transistor 26 becomes conductive at the same time, no short current can flow. Therefore, current consumption is low and no noise is generated due to short current.

Furthermore, since the resistors 24 and 22 used in this circuit do not need to be highly accurate, they can be integrated into the same circuit using a CMOS process.

In the embodiment of the present invention, one of the current drive circuits is controlled by the switches 20 and 27, but a similar effect can be achieved by controlling the gates of the MOS transistors 21 and 26.

Next, the effects of actually configuring such a circuit are listed below.

1. As a constant voltage source, it can flow a large current while maintaining a highly accurate voltage level.

2. If you want to use an OPAMP that is easy to integrate into an integrated circuit, requires a large current to flow in the circuit, and has even higher accuracy, you can use an external bipolar operational amplifier, or use an internal Even if you use a CMOS op amp,
Although it was necessary to use a bipolar transistor as an external booster, by using this circuit, external components and current consumption can be reduced.

3 As an OPAMP, it is capable of driving large currents without losing its functionality as a normal CMOS operational amplifier.

4 The booster circuit of the present invention has a small gain and a corner frequency that is much higher than that of a CMOS operational amplifier.
If the CMOS operational amplifier has enough phase margin to prevent oscillation on its own, it will not oscillate.

5. The dynamic range of the booster circuit is extremely wide, so various input voltage levels can be selected arbitrarily without narrowing the range of the CMOS operational amplifier.

As described above, according to the present invention, since there is no conductive path between the power supplies using transistors, short current is not generated at the time of input signal transition, and it is possible to prevent the generation of noise due to short current.

[Brief explanation of the drawing]

Figure 1 shows a conventional example of a CMOS operational amplifier.
FIG. 2 shows an embodiment of the invention. In Figure 1, 1... operational amplifier minus input terminal, 2... operational amplifier positive input terminal, 3... operational amplifier gate drive terminal, 4, 5, 10... Pch transistor, 6, 7, 8, 13... Nch transistor, 9
...Power supply _VDD , 11...Phase compensation capacitor,
12... operational amplifier output terminal, 14... power supply V _SS , in Figure 2, 15... operational amplifier minus input terminal, 16... operational amplifier positive input terminal,
17... CMOS operational amplifier, 18... operational amplifier output terminal, 19... inverter, 20, 26...
...Pch transistor, 21, 27...Nch transistor, 22, 24...Resistor, 23...Power supply
V _DD , 25... booster circuit output terminal of the present invention,
28...Power supply V _SS .

Claims (1)

[Claims] 1. A first resistor connected between a first power source and a first terminal that is an output terminal;
a first MOS transistor connected in a column between the power supplies, a second MOS transistor connected between the first terminal and the second power supply, and a second MOS transistor connected between the first terminal and the second power supply. a second resistor connected to the booster circuit, and an input signal is applied to the gate electrodes of the first and second MOS transistors, the first
A third MOS transistor connected in series with
a MOS transistor; a fourth MOS transistor connected in series with the second MOS transistor between the first terminal and the second power supply; and a third and fourth MOS transistor that delays the input signal.
A booster circuit comprising: a delay circuit that applies voltage to a gate electrode of a transistor.