JPH0588577B2 - - Google Patents

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a clock-controlled data transfer system.
In particular, by installing simple hardware on the receiving side, economical NRZ has the same functionality as the CMI encoding method.
The present invention relates to an automatic clock phase adjustment circuit suitable for encoding data transfer.

[Background of the invention]

Conventional clock-controlled data transfer methods include, for example, the NRZ encoding method and the CMI encoding method. Figure 1 shows NRZ (Non-Return to Zero)
FIG. 2 is a block diagram illustrating a code transfer method. 1st
In the figure, a sender S with a sender SEND
DATA input and CLK are each data line L1 and clock line
It passes through L2 (indicating each transmission data and clock waveform) separately and is sent to the receiving side R having a receiving device REC, and a DATA output is obtained. In this system, unless the data phase and the clock phase are always the same, the receiving side R cannot receive the data correctly. Therefore, if the distance between the transmitting side S and the receiving side R becomes long and a shift occurs between the data phase and the clock phase, the receiving side R will not be able to correctly receive data. Figure 2 was designed to compensate for this shortcoming.
FIG. 2 is a block diagram illustrating a CMI encoding transfer method. In Figure 2, there is a DATA input on the sending side S.
A code section CODE is provided to mix CLK, and a CMI code (indicating the transmission waveform) is sent from the transmitting device SEND via transmission path L in the form of a mixture of data and clock.
The receiving side R sends this information to the receiving device.
The clock is received by the REC, only the clock is extracted by the timing extraction unit TIMING, and the data is extracted using this extracted clock by the decoding unit DECODE to obtain the DATA output. In this method, data and clock can always maintain the same phase condition regardless of the transmission path length, but a code section is required on the transmitting side, and a timing extraction section and a decoding section are required on the receiving side. It becomes a large-scale device.

[Purpose of the invention]

The purpose of the present invention is to provide a clock that can provide functions equivalent to those of the CMI encoding system by providing simple hardware on the receiving side by transmitting only data using the NRZ encoding system, without sending the clock over a separate line, even if the transmission path is long. To provide an automatic phase adjustment circuit.

[Summary of the invention]

The present invention provides a circuit for determining the mark signal and space signal of the NRZ code on the receiving side, and a clock phase corresponding to the intermediate value of the determined mark signal and space signal is provided on the receiving side. This is an automatic clock phase adjustment circuit that makes it possible to receive NRZ code data with an extremely simple circuit by extracting the clock phase from the clock and using the extracted clock phase as a data identification clock on the receiving side. .

[Embodiments of the invention]

An embodiment of the present invention is shown below in Figures 3a, b and 4.
This will be explained using figures.

FIGS. 3a and 3b are explanatory views of the relationship between the received data waveform and the prepared clock phase, and a clock phase punching table, respectively, which explain the clock phase punching principle of the automatic clock phase adjustment circuit according to the present invention. In Figure 3a, regarding the waveform of received (test) data D of the NRZ code, T is the data period, L1 and L2 correspond to the space signal time (section) and mark signal time (section), respectively, and approximately T /
Equal to 2. x _s is a threshold value for determining a space signal, and x _n is a threshold value for determining a mark signal. Signals whose signal level is smaller than x _s are considered space signals, and signals whose signal level is larger than x _n are defined as space signals. is regarded as a mark signal. One prepared clock T1~
For T6, 1/m of the data half period T/2
M types of clocks with a phase difference of (m is an integer) are prepared on the receiving side, and for example, in this example, m =
Six types of clocks are available: clocks T ₂ , T ₃ ,
T ₄ , T ₅ , T ₆ , and T ₁ have phases that are sequentially delayed by T/2m=T/12 hours. Next, regarding the clock phase punching table in Figure 3b, the received data (waveform) D is punched out at the rising edge of the clocks T ₂ , T ₃ , T ₄ , T ₅ , T ₆ , and T ₁ in Figure 3a. The table shows the output obtained by comparing the received data (waveform) D and the threshold values _xs · _xn . For example, clock T ₁
If received data D is punched at the rising edge of
In the space signal time (section) L1, the data value is smaller than both thresholds x _s and x _n , so the output of the comparison judgment result with each threshold value x _s and x _n is 0, 0, and the mark signal At time (section) L2, the data value is larger than both thresholds x _s and x _n , so the comparison determination result with each threshold value x _s and x _n is 1,1. Even when data is punched out at the rising edge of clocks T ₃ , T ₄ , T ₅ , and T ₆ , the output is the same as above.
Furthermore, when data is punched out at the rising edge of clock _T2 , the output is 1 for the threshold x _s in section L ₁ and 0 for the threshold x _n , and the output is 0 for the threshold x _s in section L 2. On the other hand, when the output is 1, the output becomes 0 for the threshold value x _n .

However, the received data (waveform) D in FIG.
It can be. For this reason, for example, clock T1
At the rising time (phase) t ₁₁ and t ₁₂ of the received data D
When _considering the extraction _of
For example, even if the value is close to 0, it will be determined as 1 if it is larger than the threshold value _xs , so there is a certain probability that a 0 of a space signal will be mistakenly received as a 1 or a 1 of a mark signal will be mistakenly received as a 0. Therefore, in order to prevent such erroneous reception, the received data may be extracted using a clock whose phase falls at the center position of the space signal and mark signal of the received data D. That is, in FIG. 3a, the clock T2 corresponds to this, and at the falling time (phase) t ₂₁ and t ₂₂ , the space signal of the received data D becomes 0.
Since it is sufficient to extract and receive the mark signal 1, it is sufficient to select the clock T2 from among the m=6 types of clocks _T0 to _T6 having different phases prepared for this purpose. Therefore, regarding how to select this clock T2, in the clock phase punching table shown in Figure 3b, the results of comparison with threshold values x _s and x _n in sections L1 and L2 of received data D at the rising edge of clock T2 are used. Focusing on it, in interval L1 the threshold value x _s ,
It becomes 1,0 for x _n , and the threshold value x _s ,
x _n becomes 1, 0, and as a result, both intervals L1,
Only the comparison results between the data value at L2 and the thresholds x _s and x _n are contradictory values, so that it is possible to select the relevant clock T ₂ .

FIG. 4 is a block diagram showing an embodiment of an automatic clock phase adjustment circuit according to the present invention using the clock phase punching principle of FIG. In Figure 4, the clock is sent from the transmitting device SEND on the transmitting side S.
NRZ code (test) data is transmitted by CLK. The flip-flop F/F on the receiving side R takes in the received data using a clock selected from among the clocks _T1 to _T6 for outputting the received data D. The next stage CMPA is a mark signal threshold judgment circuit (comparator) that compares the signal level of the received received data with the space signal judgment threshold x _s and the space signal threshold x _n . This is a threshold value judgment circuit (comparator) for determining data mark signals. EXOR is a circuit that takes the exclusive OR of the outputs of both threshold judgment circuits (comparators) CMPA and CMPB, and its output is connected to the counter CNT via the NOT circuit, flip-flop F1, and AND gate. Also, CLK is received data D
For a clock having a frequency 2 (period T/2, which is 1/2 of the period T of received data), DL changes the phase of clock CLK by T/2m=T/
This is a delay circuit that delays by 12 hours. SEL is the T/T of the delay circuit DL output by the Q output of the counter CNT.
This circuit sequentially selects one of the clocks _T1 to _T6 whose phase is delayed by 12 hours, and its output is connected to the CK terminal of the flip-flop F/F and one input of the AND gate. Receiving device on receiving side R
REC extracts received data D based on the inverted output of the selection circuit SEL.

With this configuration, if the selection circuit SEL is used to clock
If T ₁ is chosen, flip-flop F/
Since F outputs the result of punching the received data D at the rising phase of clock _T1 from the Q output, the third
As shown in Figures a and b, the outputs of the next-stage threshold value judgment circuits (comparators) CMPA and CMPB have the same value. Therefore, both threshold judgment circuits CMPA,
The value obtained by exclusive ORing the output of CMPB by the exclusive OR circuit EXOR is "0", so that the next stage flip-flop F1 is not set. Therefore, the output of flip-flop F1 is "1", and this output and clock T ₁
The counter CNT is updated according to the AND condition.
As a result, the next clock _T2 is selected by the selection circuit SEL, and the clock CK of the flip-flop F/F is selected.
is switched from clock _T1 to clock _T2 .
Then, the flip-flop F/F causes the clock to start.
As a result of punching out the received data D at the rising phase of T ₂ ,
From that Q output, the next stage threshold judgment circuit CMPA,
Since the outputs of CMPB have contradictory values as shown in Figure 3a and b, the output of the exclusive OR circuit EXOR becomes "1" from both outputs, which causes the flip-flop F/1 in the next stage to be activated. It will be set. Therefore, the output of the flip-flop F1 becomes "0" and the counter CNT is no longer updated. As a result, the clock _T2 is selected continuously from the selection circuit SEL and becomes the clock CK of the flip-flop F/F. As a result of the above, by using the inverted output of clock _T2 as the clock for extracting the received data of the receiving device REC,
As shown in FIGS. 3a and 3b, it is possible to receive correct space signals and mark signals of NRZ code data.

In the above operation, in order to determine one type of clock phase from m types of clocks with different phases prepared on the receiving side from the NRZ code data, m/2 0 data (space signal) and m/2 0 data (space signal) from the transmitting side are required. 2
It is necessary to alternately transmit one piece of data (mark signal). When one type of clock is determined by preparing these m types of clocks, it is preferable to select the value of m as small as possible to reduce the amount of hardware. The value of m can be selected from the rise time τ of the received data waveform through the transmission path and the received data period T under the condition m=T/τ.

As described above, according to this embodiment, by providing an automatic clock phase adjustment circuit with a simple hardware configuration on the receiving side, it is possible to correctly transmit and receive NRZ code data without sending the clock from the transmitting side over a separate line. can.

〔Effect of the invention〕

As described above, the automatic clock phase adjustment device of the present invention does not require large-scale hardware like the CMI code, and also does not send the clock over a separate line, allowing NRZ code data to be transmitted and received correctly. Therefore, it can be economically effective if used for optical networks or data transmission between a terminal device and a host computer, which were generally available for data transfer.

[Brief explanation of the drawing]

FIG. 1 is a block diagram illustrating a conventional NRZ code transfer method, FIG. 2 is a block diagram illustrating a conventional CMI code transfer method, and FIGS. 3a and 3b explain the principle of clock phase punching according to the present invention. FIG. 4 is a block diagram showing an embodiment of an automatic clock phase adjustment circuit according to the present invention. S...Sending side, SEND...Sending device, R...Receiving side,
F/F...flip-flop, CMPA...space signal threshold judgment circuit (comparator), CMPB...mark signal threshold judgment circuit (comparator), EXOR...exclusive OR circuit, CNT...counter, CLK...clock, DL...delay circuit, SEL...selection circuit, REC...
Receiving device, x _s ... Space signal judgment threshold, x _n
…Mark signal judgment threshold, L1…Space signal time (section), L2…Mark signal time (section), T ₁
~T ₆ …Clock.

Claims (1)

[Claims] 1. While the receiving side receives an NRZ code test data pattern of a predetermined bit length, in which patterns of “1” and “0” appear alternately, the pattern is sent before the NRZ code data from the transmitting side. from the sending side
This is an automatic clock phase adjustment circuit that automatically selects a reception clock with a desired phase from among multiple reception clocks with different phases in order to reliably receive NRZ code data. A receive clock generator that generates a plurality of receive clocks with a period equal to 1/2 of the data period and whose phases are shifted by 2π/N (N: generally an integer of 2 or more); Any one of the multiple reception clocks of
The signal level of the NRZ code test data pattern from the transmitting side is determined at the rising edge or falling edge of the clock using a clock selecting section that selects and outputs one of the clocks, and a receiving clock that is selectively outputted from the clock selecting section. After comparing the signal level held as a digital value with the signal level from the signal level holding unit and the threshold value for mark signal level determination and the threshold value for space signal level determination, a signal level comparison and determination unit that determines whether or not the signal level of the mark exists between the mark signal level determination threshold and the space signal level determination threshold; Based on the comparison judgment result that the threshold exists between the signal level judgment threshold and the space signal level judgment threshold, the flip-flop for counting stop control which is placed in the counting stop state and the flip-flop for counting stop control Until the flip-flop is placed in the counting stop state, the flip-flop is placed in the counting state by the reception clock selectively outputted from the clock selection section, and the count value is generated as a clock selection signal to the clock selection section. An N-adic counter,
Automatic clock phase adjustment circuit consisting of: