JPH05886B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a signal amplitude limiting device or limiter. Amplitude limiting devices are used in a variety of applications and their range of application is extremely wide. For example, when transmitting a frequency modulated signal or when demodulating a frequency modulated signal, it is necessary to use an amplitude limiting device. The amplitude limiting device of the present invention is suitable for application to a frequency demodulator for a relatively high modulation frequency, such as in a magnetic recording/reproducing device, and is also suitable for integration into an integrated circuit.

Conventional configurations and their problems In recent years, amplitude limiting devices suitable for integrated circuits use capacitors or coils to improve limiter balance, that is, generate even-order harmonic components due to amplitude limiting. Generally, it is designed to reduce the amount of

An amplitude limiting device used in a conventional integrated circuit will be described below.

FIG. 1 shows a circuit diagram of an amplitude limiting device used in a conventional integrated circuit, in which 1 is an input terminal for a minute signal whose amplitude should be limited, 2 and 3 are transistors, and 4 and 5 are resistors. , respectively the first and second
The bases of the transistors 2 and 3 are biased by a voltage source 8 through resistors 6 and 7, respectively, and the base of the transistor 2 is also connected to the input terminal 1. 9,
10 is a transistor, 11 and 12 are emitter resistors, 13 is a current source, and 14 and 15 are collector resistors, each of which constitutes a first amplifier, and the bases of transistors 9 and 10 are connected to the emitters of transistors 2 and 3, respectively. connected, transistor 9,
The 10 emitters have emitter resistances 11 and 1, respectively.
2 to a current source 13, and the collectors of transistors 9 and 10 each have a collector resistor 1.
4 and 15. 16 and 17 are transistors, and 18 and 19 are resistors, which constitute third and fourth emitter follower circuits, respectively, and the bases of transistors 16 and 17 are connected to transistors 9 and 1.
0 collector. 20 and 21 are transistors, 22 and 23 are current sources, and 24 and 25 are collector resistors, each of which constitutes a second amplifier, and the bases of transistors 20 and 21 are connected to the emitters of transistors 16 and 17; The emitters 20 and 21 are connected to current sources 22 and 23, respectively, and the transistors 20 and 21 are connected to current sources 22 and 23, respectively.
The collectors of are connected to collector resistors 24 and 25. 26 and 27 are terminals provided in the integrated circuit for connecting the inside of the integrated circuit and an external circuit, 28 is a capacitor, 29 and 30 are output terminals, and the emitters of the transistors 20 and 21 are connected through the terminals 26 and 27. The transistors 20 and 2 are connected by a capacitor 28.
The collector of No. 1 is connected to output terminals 29 and 30.

The operation of the conventional amplitude limiting device configured as described above will be described below.

In FIG. 1, a signal inputted from an input terminal 1 is inputted via a first emitter follower circuit to the base of a transistor 9 constituting a first amplifier with low impedance. transistor 9,1
0 constitutes a differential amplifier, each base is biased by the bias circuit and the first and second emitter follower circuits, and when the input signal is minute, the current value is inversely proportional to the emitter resistors 11 and 12 and the current value of the current source 13. AC emitter resistance of transistors 9 and 10,
The signal is amplified with an amplification degree approximately determined by the collector resistors 14 and 15, and is output at low impedance via the third and fourth emitter follower circuits. Here, the output signals of the first amplifier outputted by the third and fourth emitter follower circuits are in the opposite phase and in-phase relationship with the signal inputted to the input terminal 1, respectively. These are input to the bases of transistors 20 and 21 constituting the second amplifier, and the current source 2
Transistor 2 which is inversely proportional to the current value of 2 and 23
The signal is amplified with an amplification degree approximately determined by the AC emitter resistance of 0.0 and 21, the capacitor 28, and the collector resistances 24 and 25, and is output from the output terminals 29 and 30. Now, the AC component of the input signal input to input terminal 1 is V _i ,
Assuming that the first amplifier operates linearly and its amplification degree is G ₁ , the output signal of the first amplifier, that is, the input signal of the second amplifier, are −G ₁ V _i and G ₁ V _i , respectively. Become. Assuming that the degree of amplification during linear operation of the second amplifier is G ₂ and the output signals output to the output terminals 29 and 30 are V _p and -V _p , when V _i is sufficiently small, V _p = G ₁ G ₂ V _i ...(1). Here, G ₂ = R _c / r _e +1/2・¹ / _SC ...(2) However, r _e is the AC emitter resistance of the transistors 20 and 21, and the current value of the current sources 22 and 23 is
I ₂ , where k is the Boltzmann constant, q is the electron charge, and T is the absolute temperature, r _e =kT/q・1/I ₂ , S is the complex angular frequency, and S=j・2π is the input signal Frequency, C is the capacitance value of capacitor 28, R _c
is the resistance value of the collector resistors 24 and 25, and the current amplification factor hFE of the transistors 20 and 21 is assumed to be sufficiently large. Next, the voltage drop across the resistors 24 and 25 is determined by the current values of the current sources 22 and 23, respectively.
Since I ₂ , when there is no input signal, R _c and
I ₂ , and when an AC signal is input, the maximum value of the voltage drop is 2R _c I ₂ and the minimum value is zero. Therefore,
When G ₁ G ₂ V _i exceeds R _c I ₂ or −R _c I ₂ in the positive or negative direction, the amplitude is limited and the AC signal level R ₂ I ₂ −
Or −R ₂ I ₂ is output as constant. Here, the frequency characteristics of the output signal for a small input signal |V _i |<R _c I ₂ /G ₁ G ₂ are given by _{equations (} 1 ₎ and ( ₂ ): _e ×j4πf・r _e C/1+j4πj・r _e
C...(3) becomes. Since G ₁ is a constant, equation (3) becomes a high-pass filtering characteristic, and its cutoff frequency f _c becomes f _c =1/2π×1/2 r _e C . Here, as a specific numerical example, I ₂ =
If it is 0.1mA, r _e ≒260Ω, so at this time _c =
To obtain 500KHz, C≒612pF is required.

On the other hand, considering the DC potential of the above circuit, transistors 2 and 3, resistors 4 and 5, resistor 6,
7, transistors 9, 10, resistors 11, 12, resistors 14, 15, transistors 16, 17, resistor 1
When transistors 8 and 19 have exactly the same characteristics, when input terminal 1 has no input, transistors 16 and 17
The emitter potentials of will be equal. However, in an integrated circuit, these characteristics have a certain distribution variation and a DC potential difference.

Limiter balance (the ratio of even-order harmonic components generated to input signal frequency components in an amplitude limiting device) is generally used to evaluate the performance of an amplitude limiting circuit. Now, as an example of this limiter balance, let us assume that the amplitude V _a and frequency of the input signal V _i of the amplitude limiter are V _i =V _a cos2πt, and that the amplification degree of the amplitude limiter is sufficiently large, and its output Assume that the signal V _p is a rectangular wave with an amplitude of 1. Here, if the DC bias of the amplitude limiter is amplified so that the timing of V _i = ΔV is the timing of the rise and fall of the rectangular wave with a deviation of ΔV, the rectangular wave is a harmonic component of an odd-numbered frequency. It has even-order harmonic components outside.
Therefore, the amplitude of the frequency component is V _p1 and the frequency 2
Letting the component amplitude of be V _p2 , V _p1 and V _p2 are the Fourier series theorem V _p = V _pp /2 + V _p1 cosφ + V _p2 cos2φ +... V _po =2/π∫〓 _p U _p (φ) cosnφdφ However, φ= From 2πt, is found. After all, V _p1 /V _p2 =V _a /ΔV, and the limiter balance can be evaluated by the ratio of the input signal amplitude at the input of the amplifier that performs the amplitude limiting operation to the deviation of the DC voltage when no input is applied.

In the conventional example shown in FIG. 1, the first amplifier amplifies the minute input signal to increase the above-mentioned V _a . The capacitor 28 blocks the DC potential difference generated in the first amplifier, and has the effect of amplifying and amplitude limiting only the AC signal at the output of the third and fourth emitter follower circuits in the second amplifier, so the above ΔV is Since it is generated only in the second amplifier, it becomes very small, and the limiter balance is improved.

By the way, the capacitance that can be integrated on an integrated circuit is about 10 pF at most, and with the above configuration, several
It is impossible to realize an amplifier with a passband of 100KHz or more using integrated circuits alone. Therefore, the above configuration has the problem that two terminals must be provided on the integrated circuit and the capacitance must be externally connected.

On the other hand, there is an example of using a coil as another configuration, but in this case, a coil is inserted between the collectors of transistors 9 and 10 that make up the first amplifier, and the emitters of transistors 20 and 21 that make up the second amplifier are inserted. In this case, the coil cannot be provided on the integrated circuit, and two terminals must be provided on the integrated circuit to connect the coil from the outside.

Purpose of the invention The present invention solves the above-mentioned conventional problems.
An amplitude limiting device suitable for integrated circuits that can be configured with transistors, diodes, resistors, and small capacitances, and that generates few even-order harmonic components even with small input signals in terms of performance. The purpose is to provide.

Structure of the Invention The present invention includes first and second amplifying means, and first and second amplifying means.
This is an amplitude limiting device equipped with a clamping means, in which a first amplifying means linearly amplifies a minute input signal to obtain two output signals having equal amplitudes and opposite phases to each other,
The first and second clamping means clamp to the same DC voltage, and the second amplification means amplifies and limits the amplitude of the difference signal, thereby removing DC level fluctuations generated by the first amplification means, It is possible to amplify and limit the amplitude of only the AC signal component in the input signal.

DESCRIPTION OF EMBODIMENTS FIG. 2 shows a block diagram of an amplitude limiting device according to an embodiment of the present invention, in which 1 is an input terminal of a minute signal whose amplitude is to be limited, 31 is a first amplifier, 32, 33 are the first of the first amplifier,
a second output terminal, 34 is a second amplifier, 35,3
6 are the first and second input terminals of the second amplifier, 37 and 38 are the first and second clamp circuits, 2
9 and 30 are first and second output terminals for amplitude-limited signals. Here, the first amplifier 31 linearly amplifies the signal input to the input terminal 1, and the first clamp circuit 37 connects the first output terminal 32 of the first amplifier 31 and the first output terminal of the second amplifier 34. Input terminal 3 of
5, the second clamp circuit 38 connects the second output terminal 33 of the first amplifier 31 and the second output terminal 34 of the second amplifier 34.
The second amplifier 34 nonlinearly amplifies the voltage difference between the signals input to the input terminals 35 and 36, that is, limits the voltage when the voltage difference exceeds a certain level. Output terminal 29, 3
Outputs a signal whose amplitude is limited from 0.

The operation of the amplitude limiting device of this embodiment configured as described above will be explained below.

A small signal to be amplified and limited is input from the input terminal 1 and is amplified to an appropriate amplitude by the first amplifier 31, and then outputted from the first and second output terminals 32 and 33 with equal amplitude and in opposite phases. be done. Now, if there is a difference in the DC voltage between the first and second output terminals 32 and 33 of the first amplifier 31 due to variations in the elements, bias circuit, etc. that make up the first amplifier 31, this difference will be applied to the first amplifier 31 as it is. When the second amplifier 34 amplifies and limits the amplitude, as described above, the first amplifier 34 amplifies and limits the amplitude.
1 and the ratio of the amplitude of the AC signal at the first and second output terminals 32 and 33 to 1/2 of the DC potential difference because signals of opposite phase are output to each output terminal, the amplitude is almost limited. The fundamental frequency component of the signal and the second
The lower the amplitude of the input signal and the higher the degree of amplification of the first amplifier 31, the worse the limiter balance becomes. The first and second clamp circuits cut off the DC voltage at the first and second output terminals 32 and 33 of the first amplifier 31, and pass an equal DC current to the first and second output terminals of the second amplifier 34. is applied to the input terminals 35 and 36 of
The second amplifier 34 can amplify and limit the amplitude of only the output AC signal component of the first amplifier 31.

Here, the first and second clamp circuits and the second amplifier themselves also generate a DC voltage difference, but when the AC signal amplitude of the input signal is amplified to an appropriate value by the first amplifier, in practice Even-numbered harmonic components can be reduced to a level that causes no problems.

In addition, in the present invention, the first amplifier is not only necessary to amplify a minute input signal, but also clamps the two input terminals of the second amplifier by outputting signals with opposite phases to each other. This is also essential in order to equalize the amount of DC voltage change due to operation so that it can be removed by the second amplifier.

The amplitude limiting device of this embodiment whose operation has been explained above will be explained in more detail using the specific circuit example shown in FIG.

In FIG. 3, 1 is an input terminal for a minute signal whose amplitude should be limited, 2 and 3 are transistors, 4 and 5 are resistors, which constitute the first and second emitter follower circuits, respectively, and 6 and 7 are resistors. , 8 are voltage sources, each forming a bias circuit, 9, 10
is a transistor, 11 and 12 are emitter resistors, 1
3 is a voltage source, 14 and 15 are collector resistors, each of which constitutes a first amplifier, and 16 and 17 are collector resistors.
20 and 21 are transistors, 22 and 23 are current sources, and 24 and 25 are collector resistors, respectively, which constitute the third and fourth emitter follower circuits. 29 and 30 are output terminals for amplitude-limited signals, and the above structure is similar to that of FIG. 1. What is different from the configuration shown in FIG. 1 is the capacitors 39 and 40, the diodes 41 and
The first and second clamp circuits constituted by the voltage source 43 are connected between the emitters of the transistors 16 and 17 constituting the third and fourth emitter follower circuits and the bases of the transistors 20 and 21 constituting the second amplifier. The second point is that the terminals 26, 27 and the capacitor 28 are removed from the first conventional example, and the emitters of the transistors 20, 21 are directly connected.

Regarding the specific circuit example configured as above,
The operation will be explained below.

In FIG. 3, a signal input from the input terminal 1 is input to the first amplifier via the first emitter follower circuit, and includes emitter resistors 11 and 12, an AC emitter resistor that is inversely proportional to the current value of the current source 13,
It is amplified with an amplification degree approximately determined by the collector resistors 14 and 15, and is output at low impedance via the third and fourth emitter follower circuits, each with a capacitance of 3
9. A first clap circuit consisting of a diode 40, a second clap circuit consisting of a capacitor 40, and a diode 41.
drives the clamp circuit. Since the first and second clamp circuits are connected to the bases of transistors 20 and 21, which are the first and second input terminals of the second amplifier, the time constants of the clamp circuits are the capacitances 39 and 4.
It is determined by the parallel combination of the AC impedance of the diodes 41 and 42 and the base impedance of the transistors 20 and 21, which have a value of 0. Now, the current amplification factors of the transistors 20 and 21 are h _FE , the current sources 22,
Assuming that the current value of 23 is I ₂ , when input terminal 1 has no input and there is no output to the third and fourth emitter follower circuits, diodes 41 and 42 and transistors 20 and 21 have I ₂ /(1+h _FE ) current flows. In this state, the AC impedance when passing a minute AC current is r _e =kT/q・1/I ₂ , and the diodes 41 and 42 are (1+h _FE ) _re ,
The base input impedance of the transistor is
h _FE・_re . Therefore, the time constant of the clamp circuit at this time is approximately 1/2 h _FE r _e assuming h _FE ≫1. Furthermore, when a signal with an appropriate amplitude is input to the input terminal 1 and a sufficiently large signal is output to the third and fourth emitter follower circuit outputs, the potential determined by the voltage source 43 is applied to each input of the second amplifier. is clamped. These signals are in opposite phase, so when one diode performs a clamp operation and becomes conductive, the transistor connected to it is cut off, the other diode is cut off, and the other diode is turned off. The connected transistor becomes conductive. The transistors 20 and 21 constituting the second amplifier both become conductive when the outputs of the third and fourth emitter follower circuits are near their respective average levels, and at this time the diodes 39 and 40 are both cut off. The base input impedance of the transistors 20 and 21 is h _FE · _re , respectively, and the time constant of the clamp circuit is h _FE · _re ·C. In the end, the frequency characteristics of the amplitude limiting device when the second amplifier performs amplification operation exhibits high-pass filtering characteristics, and the cutoff frequency _c at that time is _c = 1/2π・1/h _FE・_re・It becomes C. Here, as a specific numerical example, I ₂ =
Assuming 0.1 mA and h _FE = 100, C≈12 pF is required to obtain _c = 500 KH.

In the above circuit example, by providing fifth and sixth emitter follower circuits in each space of the second amplifier and increasing the input impedance of the second amplifier, the time constant of the clamp circuit can be further multiplied by h _FE . , so the cutoff frequency can be set to 1/h _FE . However, a drawback in this case is that when a DC potential difference occurs between the fifth and sixth emitter follower circuits, the limiter balance deteriorates accordingly.

Effects of the invention A first amplifier that linearly amplifies an input signal to obtain signals with opposite phases to each other, a second amplifier that amplifies the difference signal between the two input signals and limits the amplitude, and a first amplifier and two By providing two symmetrical clamp circuits between the output terminal and the two input terminals of the second amplifier, a small input signal can be amplified by the first amplifier and its amplitude can be limited by the second amplifier. At the same time, in order to prevent the limiter balance from deteriorating due to DC voltage fluctuations occurring in the first amplifier,
By cutting off this DC voltage and reducing the capacitance value required to obtain a predetermined passband, it is possible to integrate the circuit, eliminating the need for a capacitor or coil outside the integrated circuit, and as a result reducing the number of terminals on the integrated circuit. Reduce it,
It is possible to achieve high integration and miniaturization of integrated circuit packages, which has great practical effects.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a conventional amplitude limiting device, FIG. 2 is a block diagram of an amplitude limiting device in an embodiment of the present invention, and FIG. 3 is a specific circuit diagram of the amplitude limiting device in the same embodiment. 1... Input terminal, 31... First amplifier, 32
...the first output terminal of the first amplifier, 33...the second output terminal of the first amplifier, 34...the second amplifier, 35...the first input terminal of the second amplifier,
36... second input terminal of the second amplifier, 37...
...first clamp circuit, 38...second clamp circuit, 29, 30...output terminal.

Claims (1)

[Claims] 1 It has an input means for a signal whose amplitude is to be limited, an input terminal connected to the input means, and first and second output terminals, and amplifies the signal applied to the input terminal and outputs signals having opposite phases to each other. a first amplifying means for obtaining signals at first and second output terminals; first and second input terminals; and at least one output terminal;
a second amplifying means for amplifying a difference signal between the signals applied to the input terminals of the second amplifying means, and disposed between the first output terminal of the first amplifying means and the first input terminal of the second amplifying means. a second clamping means disposed between a second output terminal of the first amplifying means and a second input terminal of the second amplifying means; An amplitude limiting device comprising an amplitude limiting signal output means connected to an output terminal of the amplifying means.