JPH0589196A - Logical processing unit - Google Patents

Abstract

(57) [Summary] (Modified) [Purpose] Operation of binary data and quaternary data can be performed without lowering the speed and increasing the configuration, maintaining versatility in memory access that is binary data. Providing equipment that can. [Structure] 2 V of the selection circuits 12 to 14 in the case of binary processing
However, in the four-value processing, 4V becomes active. In the case of binary processing, the output of the binary logic operation circuit 11 becomes the operation result.
In the case of addition, the selection circuit 12 processes the input from the adjacent odd bit in the case of binary and from the even bit in the case of quaternary. In the odd bit arithmetic processing unit 20, 2V of the selection circuit 22 becomes active in the case of binary processing and 4V becomes active in the case of quaternary processing. The decoder 23 decodes the input bits A, B and C. The selection circuit 22 outputs the result of the decoder 23 in the case of four-value processing and the result of the binary logic operation circuit 21 in the case of binary processing. In the case of four-value processing, the logical sum of the even bit output (S2i) from the binary logic operation circuit 11 and the odd bit (S2i + 1) is taken to produce a four-valued X value.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a logic operation processing device for performing logic simulation or the like.

[0002]

2. Description of the Related Art Conventionally, logic operation processing in logic simulation has been realized by software or hardware.

When performing a logic simulation by software, the logic operation processing section is usually multi-bit binary data processing, and 4-value data (0, 1, X (undefined), Z).
When processing (HZ (high impedance)), the data processing and the code processing are performed separately. Therefore, 4
There is a problem that the processing speed becomes slow when processing the value data.

On the other hand, in the case of a hardware accelerator,
Since the 4-valued logical operation circuit is used, the processing speed is faster than that in the case of the processing by the software described above. However, in order to be able to process both binary data and 4-valued data, a 4-valued logical operation circuit is required in addition to the 2-valued logical operation circuit. Therefore, in many cases, the 4-valued logical operation circuit is 1-bit or 4-valued and corresponds to the circuit model. Therefore, in order to handle multi-bit 4-valued data and 2-valued data, You have to configure dedicated hardware for each. Therefore, there is a problem that the circuit configuration of the hardware becomes complicated.

Further, in the case of a circuit for exclusive use of four-valued data, since effective data are scattered everywhere when processing binary data, it takes a lot of processing time, a large memory capacity is required, and effective utilization of the memory is aimed at. There was a problem that I could not.

[0006]

As described above, in the conventional technique, when processing multi-bit 4-value data and 2-value data, the processing speed becomes slow and the hardware configuration increases. was there.

The present invention has been made in response to such a conventional situation, and it is possible to process binary data and quaternary data without lowering the processing speed and increasing the hardware configuration. It is an object of the present invention to provide a logical operation processing device capable of effectively using a memory or the like and increasing the speed thereof, and capable of maintaining versatility in memory access which is binary data.

[0008]

That is, according to the present invention, in an arithmetic processing unit, binary data processing or 4 data processing is selectively performed.
Selecting means for selecting the value data processing; first binary logical operation means for performing arithmetic processing of an even number bit in the binary data processing or the four-value data processing based on the selection result of the selecting means; Processing or second binary logic operation means for performing odd-numbered bit arithmetic processing in four-value data processing, means for determining whether or not four-value data processing, and four-value data processing based on the determining means, 2 is provided with a unit for converting the operation result of the second binary logic operation unit into fixed data, and a unit for outputting a logical sum of the fixed data and the operation result of the first binary logic operation unit. It is characterized in that the value data processing and the code processing are provided separately.

[0009]

In the logical operation processing device of the present invention having the above structure,
When processing the value data, the speed can be increased as compared with the logic simulation by the conventional software in which the data processing and the code processing are separately performed. In addition, multi-bit 4-value data and 2-value data can be processed without using a 4-value logic operation circuit and a 2-value logic operation circuit, respectively, without increasing the hardware configuration. .. Further, it is possible to maintain versatility in memory access that is binary data.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

1A and 1B show the configuration of a logical operation processing device according to an embodiment of the present invention.
Shows an even-bit arithmetic processing unit 10 for processing the 2i-th bit, that is, the even-numbered bit.
The odd bit arithmetic processing unit 20 for processing the i + 1th bit, that is, the odd bit is shown. In FIG. 1 (a),
11 is a binary logic operation circuit for performing a logical operation on binary data,
Reference numerals 12, 13, and 14 are selection circuits that perform selection by binary processing and four-valued processing, and 15 and 16 are OR circuits that take a logical sum. Further, in FIG. 1B, reference numeral 21 is a binary logical operation circuit for performing a logical operation on binary data, 22 is a selection circuit for selecting between binary processing and four-valued processing, and 23 is a code for four-valued data. It is a decipherer that decides. In addition, in FIG.
A and B are inputs, S is an output, CI is a carry input, C
O is a carry output.

Further, FIG. 2 shows a quaternary expression in which quaternary data is represented by 2 bits, and FIG. 3 shows a truth table in a quaternary logical operation. It should be noted that FIG. 3A shows the truth value in the case of logical product, logical sum, and negation, and FIG. 3B shows the truth value in the case of addition. In FIG. 3B, the symbol * indicates that the carry output is 1, and when the addition result is X, the carry output is also X.

The operation of the arithmetic circuit will be described below.

In the even-bit arithmetic processing unit 10 of FIG. 1A, the binary logical operation circuit 11 performs the same arithmetic processing as the binary processing even in the four-value processing. In the case of binary processing, 2V of the selection circuits 12, 13, and 14 become active, and in the case of quaternary processing, 4V become active. In the case of binary processing, the selection circuits 13 and 14
The output of the binary logic operation circuit 11 is directly output as the operation result. In addition, in the case of addition, the selection circuit 12 causes the input carry bit to start from the adjacent odd bit (CO2i-1) when the value is binary, and the even bit (CO2i-) when the value is four.
Input from 2) and processed.

On the other hand, in the odd bit arithmetic processing unit 20 of FIG. 1B, 2V of the selection circuit 22 in the case of binary processing is
In the case of four-value processing, 4V becomes active. Further, the input bits A, B and C are input to the decoder 23 and are decoded. Then, according to the 4-value state table of FIG.
In the case of four-valued data, [specifically, input data of X (1,1) and (0,1), carry input = 0], bit 1
Since the (odd bit) is "1", the decoder 23 therefore judges this state and activates 4V regardless of the operation result S of the binary logic operation circuit 21 and selects circuit 2
The data of "1" is forcibly output to 2. As a result, the data of the calculation result S2i + 1 is "1". Calculation result S2i + 1
Is input to one input terminal of the OR circuit 16 shown in FIG. 1a. The operation result S2i of the binary logic operation circuit 11 is "1" from the input data A "1" and B "0" of the even-bit binary logic operation circuit 11 and the input carrier CI "0", and the OR It is input to the other input terminal of the circuit 16. Since 4V is active in the selection circuit 14, OR
The output result "1" from the circuit 16 becomes the binary logic operation result of the even bit. Therefore, the processing result of the four-value data processing is X (1,1). This is in agreement with the result of the truth table of FIG. Further, in the case of binary processing, the calculation result performed by the binary logic operation circuit 21 is output via the selection circuit 22.

In the case of four-value processing, the OR circuit 16 shown in FIG. 1A takes the logical sum of the even bit output (S2i) from the binary logic operation circuit 11 and the odd bit (S2i + 1). , (S2i + 1) is 1, (S2i) is set to 1 and a four-valued X value is created.

The OR circuit 15 takes the logical sum of the even carry bit output (C02i) of the binary logic operation circuit 11 and the odd bit operation output result (S2i + 1). (S2i + 1) and (C0
Since 2i) are both "1", the output of the OR circuit 15 becomes "1". Since it is four-value data processing, the selection circuit 13 activates 4V. After all, even carry bit output (C02
i) becomes “1” via the selection circuit 13. Figure 3
Based on the truth table of (b), the odd-numbered carry bit output (C02i + 1) becomes "1". Therefore, the carry bit value of the four-value data processing becomes the X value.

As described above, according to the logical operation processing apparatus of the present embodiment, multi-bit 4-value data and binary data can be obtained without using a 4-value logic operation circuit and a 2-value logic operation circuit, respectively. Can be processed, and even in the case of binary data processing, the valid data does not scatter and the data can be in a clogged state, so that the memory can be effectively used. In addition, when processing four-valued data, it is possible to achieve a higher speed than in the conventional logic simulation using software that separately performs data processing and code processing. Further, it is possible to maintain versatility in memory access that is binary data.

[0019]

As described above, according to the logical operation processing device of the present invention, binary data and quaternary data can be processed without lowering the processing speed or increasing the hardware configuration. Therefore, it is possible to effectively use the memory and increase the speed, and it is possible to maintain versatility in the memory access that is binary data.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of a logical operation processing device according to an embodiment of the present invention.

FIG. 2 is a diagram showing a quaternary expression in which quaternary data is represented by 2 bits.

FIG. 3 is a diagram showing a truth table in a four-valued logical operation.

[Explanation of symbols]

 10 even-bit operation processing unit 11 binary logic operation circuit 12, 13, 14 selection circuit 15, 16 OR circuit 20 odd-bit operation processing unit 21 binary logic operation circuit 22 selection circuit 23 decoder

Claims (1)

[Claims] 1. In an arithmetic processing unit, selecting means for selectively selecting binary data processing or quaternary data processing, and binary data processing or quaternary data processing based on the selection result of the selecting means. A first binary logical operation means for performing an even-numbered bit arithmetic operation in the above, a second binary logical operation means for performing an odd-numbered arithmetic operation in the binary data processing or the four-value data processing, and a four-valued data Means for deciding whether or not to process, means for setting the operation result of the second binary logic operation means to fixed data during 4-value data processing based on the deciding means, the fixed data and the first A logical operation processing device comprising: means for outputting a logical sum of the operation result of the binary logic operation means; and binary data processing and code processing provided separately.