JPH05893B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a counter that is stopped by a PAUSE signal.

[Technical background of the invention and its problems]

A conventional example of this type of counter is shown in FIG. That is, conventionally, by connecting two or more blocks 11 in series, a counter with a number of bits corresponding to the number of connections is constructed. In the figure, 1 is the input part for the data signal and pause (stops the counter) signal, 2 is the input for loading the initial value, 3 is the counter output, 4 is the NAND circuit, 5 is the inverter, 6 is the NOR circuit, and 7 is the clock. 8 is a clocked NOR circuit, 9 is a shift register (1 bit), and 1' is an output.

In block 11 of FIG. 1, data is input from input section 1 and enters NOR circuit 6.
becomes one input of the clocked NOR circuit 8.
On the other hand, data is input from the input section 1, enters the NAND circuit 4, and becomes the other input of the clocked NOR circuit 8 from the inverter 5. The signal enters the shift register 9 from this circuit 8, becomes data, and is output from the output section 3. The data fed back from the output section 3 and the data input from the input 1 are exclusive-OR'ed and input into the shift register 9, where they become the next data. Also, when a pause signal is input to input 1, this pause signal is sent to gate 4,
5 and stops the counter of its own block from gate 8, and also enters input 1 of the next stage block and becomes a counter stop signal for the next stage.

In the above configuration, the pause signal is input from input 1 of the first stage block, passes through gates 4 and 5, and is input to input 1 of the next stage. Capacity causes a delay in the pause signal. Also, since the counter is configured by cascading blocks 11,
As the number of bits increases, the pause signal is input through the gates 4 and 5 of each block, which has the disadvantage that the later the stage, the greater the delay. Then, the pause signal of the first stage, which must be input, and the ripple carry output 1' of the later stage.
This overlaps with the establishment level of . In other words, this means that the counting operation is performed when the pause signal is input, which results in a malfunction.

[Purpose of the invention]

The present invention has been made in view of the above-mentioned circumstances, and an object of the present invention is to shorten the delay of the pause signal input to each block of the counter, and to prevent malfunctions when the counter is stopped.

[Summary of the invention]

In the present invention, a plurality of blocks that receive a data signal and operate as a counter are connected in cascade, and a pause signal is supplied to two or more blocks in parallel to stop the blocks.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings. FIG. 2 shows blocks used in the same embodiment, which almost correspond to those in FIG. 1, so corresponding parts are given the same reference numerals and a description thereof will be omitted. The difference between Fig. 1 and Fig. 2 is that the NAND circuit 4
A terminal 10 that allows input of a pause signal is added to the NAND circuit 4, and the NAND circuit 4 has three inputs.

FIG. 3 shows the above embodiment, in which seven blocks in FIG. 1 and block 12 in FIG.
This is a bit block counter.

In block 12, gates 4, 5, 6, and 8 constitute an exclusive OR circuit.

This configuration normally performs an exclusive OR on the data signal input to input 1 and the output 3 of shift register 9, that is, operates as a ripple counter. However, when a pause signal "0" is input to input 1, the gate 4 and 5 becomes "0", and the output of the NOR circuit 8 becomes the same value as the output 3 of the shift register 9 due to the feedback signal from the output terminal 3. Therefore, the output of shift register 9 is the same as the output of the previous shift register. The pause signal for the next stage and subsequent stages is the gate 4 of the previous stage,
In addition to this, a pause signal input at the first stage is directly input from terminal 10 to block 12 in parallel to stop the counter. That is, the signals at inputs 1 and 10 are
As is clear from the figure, the counter operation is common, when inputs 1 and 10 are both “H”, output 3
passes through a loop of output 3 - gate 4 - 5 - 8 - register 9 - output 3 - gate 4 and outputs a 1/2 frequency divided output from output 3 to the next stage. Furthermore, input 10 can only be "0" when input 1 is "0" (see FIG. 3). At this time, data is held in the normal rotation loop of output 3 - inverting gate 6 - 8 - register 9 - output 3, and this data does not change, so it is equivalent to the counting being stopped.

According to the above embodiment, when a pause signal is input to the counter, the pause signal is directly input from the terminal 10 to the block 12 in the next stage and subsequent stages without passing through the gates 4 and 5 in the previous stage, so that the pause signal in the subsequent stage is The number of pre-stage gates through which the signal passes is reduced, and the delay time of the pause signal for stopping the counter is shortened. In other words, in each block of the ripple-carry type counter, a pause signal is directly input to the block (for example, the NAND circuit 4) at intervals that can cancel out the delay of the output 1', and the ripple-carry waveform during the pause period is skewed to perform the pause operation. This is guaranteed.

Note that the present invention is not limited to the embodiments, and can be applied in various ways. For example, block 12 may be used for block 11 in FIG.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to provide a counter that can prevent malfunctions when counting is stopped by a pause signal.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram of blocks forming a conventional counter, Fig. 2 is a circuit diagram of blocks forming a counter used in an embodiment of the present invention, and Fig. 3 is an overall diagram showing the counter of the same embodiment. FIG. 9...Shift register, 10...Pause signal input terminal, 11, 12...Block.

Claims (1)

[Claims] 1. A first gate circuit that receives a data signal and a pause signal as input and has an AND gate function, and a second gate circuit that receives the data signal and pause signal as input and has a NOR gate function. A third gate circuit is provided, which inputs the output of the first gate circuit and the output of the second gate circuit and has a clocked nor gate function, and the output of the third gate circuit is A plurality of blocks each including a shift register whose input is input and whose counter output is input to the first and second gate circuits are configured, and among the blocks, a first block of the preceding block is configured.
Each of the blocks is cascade-connected to form a ripple counter so that the output of the first gate circuit of the next block becomes the input of the first gate circuit of the next block, and of the cascade-connected blocks,
A data signal and a pause signal are commonly supplied to the input of the first gate circuit of the first block and to the input of the first gate circuit of at least a second block spaced apart enough to cancel the delay of the output to the next stage. A counter characterized in that it is configured to apply voltage. 2. The counter according to claim 1, wherein the first gate circuit comprises a NAND gate and an inverter.