JPH0590196A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH0590196A JPH0590196A JP25092291A JP25092291A JPH0590196A JP H0590196 A JPH0590196 A JP H0590196A JP 25092291 A JP25092291 A JP 25092291A JP 25092291 A JP25092291 A JP 25092291A JP H0590196 A JPH0590196 A JP H0590196A
- Authority
- JP
- Japan
- Prior art keywords
- film
- contact hole
- semiconductor device
- polysilicon
- manufacturing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
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- Electrodes Of Semiconductors (AREA)
Abstract
(57)【要約】
【目的】 アスペクト比の高いコンタクト孔で信頼性が
高く、特性のよい半導体装置の製造方法を提供するこ
と。
【構成】 半導体シリコン基板11にP型高濃度拡散層
13を形成する。次に、層間絶縁膜であるBPSG膜1
2を成膜し、このBPSG膜12にコンタクト孔14を
形成する。次に、BPSG膜12上に窒化シリコン膜1
5を成膜する。そして、コンタクト孔14の側壁以外の
部分の窒化シリコン膜15を除去する。次に、コンタク
ト孔14にポリシリコン膜16を堆積させる、この後、
イオン17をドーピングし、熱処理を行う。
(57) [Abstract] [Purpose] To provide a method for manufacturing a semiconductor device having a contact hole with a high aspect ratio, high reliability, and good characteristics. [Structure] A P-type high concentration diffusion layer 13 is formed on a semiconductor silicon substrate 11. Next, the BPSG film 1 which is an interlayer insulating film
2 is formed, and a contact hole 14 is formed in this BPSG film 12. Next, the silicon nitride film 1 is formed on the BPSG film 12.
5 is formed into a film. Then, the silicon nitride film 15 except for the side wall of the contact hole 14 is removed. Next, a polysilicon film 16 is deposited in the contact hole 14, and thereafter,
Doping with ions 17 and heat treatment.
Description
【0001】[0001]
【産業上の利用分野】本発明は、半導体装置の製造方法
に関し、特に、高集積化されたアスペクト比(コンタク
トホールの深さ対径の比)の高いコンタクト孔を有する
半導体装置の製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a semiconductor device having a highly integrated contact hole with a high aspect ratio (depth of contact hole to diameter). ..
【0002】[0002]
【従来の技術】従来アスペクト比の高いコンタクト孔を
有する半導体装置において埋め込みポリシリコンを用い
たコンタクトがあり、その製造方法を図2を用いて説明
する。まず、図2aに示すように、半導体シリコン基板
21に不純物濃度の高い拡散層23を形成した後、層間
絶縁膜をとしてBPSG膜(ボロンとリンを含んだ二酸
化シリコン)22を周知のCVD法で成膜し、拡散層2
3の部分に周知の微細加工法を用いてコンタクト孔24
を開口する。2. Description of the Related Art Conventionally, there is a contact using buried polysilicon in a semiconductor device having a contact hole having a high aspect ratio, and a manufacturing method thereof will be described with reference to FIG. First, as shown in FIG. 2a, after a diffusion layer 23 having a high impurity concentration is formed on a semiconductor silicon substrate 21, a BPSG film (silicon dioxide containing boron and phosphorus) 22 is used as an interlayer insulating film by a known CVD method. Formed and diffused layer 2
The contact hole 24 is formed on the portion 3 by a well-known fine processing method.
To open.
【0003】次ぎに、図2bに示すように、周知のCV
D法を用いてポリシリコン膜26をコンタクト孔24が
充分埋まるまで堆積させる。Next, as shown in FIG.
The polysilicon film 26 is deposited by the D method until the contact hole 24 is sufficiently filled.
【0004】そして、図2cに示すように、周知の反応
性イオンエッチング法(RIE法)を用いてコンタクト
孔以外の部分のポリシリコン膜26を除去する。Then, as shown in FIG. 2C, the polysilicon film 26 except for the contact holes is removed by using the well-known reactive ion etching method (RIE method).
【0005】その後、図2dに示すように、上記のポリ
シリコンの埋め込み層を低抵抗化するために拡散層23
と同じ導伝型をもつ不純物27を周知のイオン注入法で
注入する。Thereafter, as shown in FIG. 2d, a diffusion layer 23 is provided to reduce the resistance of the polysilicon burying layer.
Impurities 27 having the same conductivity type as in the above are implanted by a well-known ion implantation method.
【0006】最後に、熱処理を施してポリシリコン中の
不純物を拡散活性化させた後、周知の金属膜を用いて配
線を行う。Finally, heat treatment is performed to diffuse and activate the impurities in the polysilicon, and then wiring is performed using a known metal film.
【0007】[0007]
【発明が解決しようとする課題】従来は、埋め込みポリ
シリコンを用いたコンタクト孔において、コンタクト孔
側壁であるBPSG膜からリンイオンがコンタクト孔内
部のポリシリコン膜に拡散してくるため、P型拡散層上
のコンタクトにおいてpn接合が形成されてしまいコン
タクト抵抗が非オーム性を示し、半導体装置の特性が不
安定になるという問題があった。Conventionally, in a contact hole using buried polysilicon, phosphorus ions diffuse from the BPSG film, which is the sidewall of the contact hole, into the polysilicon film inside the contact hole, so that the P-type diffusion layer is formed. There is a problem that a pn junction is formed in the upper contact, the contact resistance shows non-ohmic property, and the characteristics of the semiconductor device become unstable.
【0008】そこで、本発明は、低抵抗で特性の安定し
たP型拡散層上の埋め込みポリシリコンコンタクトによ
る半導体装置の製造方法を提供することを目的とする。Therefore, an object of the present invention is to provide a method of manufacturing a semiconductor device by a buried polysilicon contact on a P-type diffusion layer having a low resistance and stable characteristics.
【0009】[0009]
【課題を解決するための手段】本発明は、上記課題を解
決するために、コンタクト孔にポリシリコンを埋め込ん
だ後、金属膜を成膜する半導体装置の製造方法におい
て、拡散層を有する半導体基板上に成膜した層間絶縁膜
にコンタクト孔を開口する工程と、前記コンタクト孔を
含む全面に不純物拡散防止膜を成膜する工程と、前記コ
ンタクト孔の側壁部の前記不純物拡散防止膜を残して前
記不純物拡散防止膜を除去する工程と、前記コンタクト
孔内にポリシリコン膜を堆積させ前記コンタクト孔を完
全に埋め込む工程と、前記ポリシリコン膜に前記拡散層
と同一の導伝型の不純物を注入し、活性化し拡散する工
程とを具備することを特徴とする半導体装置の製造方法
である。In order to solve the above-mentioned problems, the present invention provides a semiconductor substrate having a diffusion layer in a method for manufacturing a semiconductor device in which a contact film is filled with polysilicon and then a metal film is formed. A step of forming a contact hole in the interlayer insulating film formed above, a step of forming an impurity diffusion prevention film on the entire surface including the contact hole, and a step of leaving the impurity diffusion prevention film on the side wall of the contact hole. Removing the impurity diffusion prevention film, depositing a polysilicon film in the contact hole to completely fill the contact hole, and implanting the same conductive impurity as the diffusion layer into the polysilicon film. And activating and diffusing the same, the method of manufacturing a semiconductor device.
【0010】[0010]
【作用】本発明は、上記のように、コンタクト孔の側壁
に不純物拡散防止膜、例えば、窒化シリコン膜を設ける
ことにより、その後の熱処理工程において、前記側壁の
外側にあるBPSG膜から埋め込みポリシリコン膜への
リンイオンの拡散を防ぎ、良好なオーム性接触を得るこ
とが可能である。これにより、コンタクト抵抗を低下さ
せることができ、安定した動作の半導体装置を得ること
ができる。As described above, according to the present invention, by providing the impurity diffusion preventing film, for example, the silicon nitride film on the side wall of the contact hole, the BPSG film outside the side wall is filled with the polysilicon in the subsequent heat treatment step. It is possible to prevent the diffusion of phosphorus ions into the membrane and obtain a good ohmic contact. As a result, the contact resistance can be reduced, and a semiconductor device with stable operation can be obtained.
【0011】[0011]
【実施例】以下、本発明の一実施例を図1を参照して説
明する。図1は本発明の一実施例である半導体装置の製
造方法の工程順序を示す断面図である。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIG. FIG. 1 is a cross-sectional view showing the sequence of steps in a method of manufacturing a semiconductor device which is an embodiment of the present invention.
【0012】半導体装置を製造するには、まず、図1a
に示すように、半導体シリコン基板11に周知の技術
で、P型の高濃度拡散層13を形成する。この拡散層の
表面濃度は1019〜1021atom/cm3程度で、不
純物はボロンイオンである。To manufacture a semiconductor device, first, referring to FIG.
As shown in, the P-type high-concentration diffusion layer 13 is formed on the semiconductor silicon substrate 11 by a well-known technique. The surface concentration of this diffusion layer is about 10 19 to 10 21 atoms / cm 3 , and the impurity is boron ion.
【0013】この後に、周知のCVD法で、層間絶縁膜
であるBPSG膜(ボロンとリンを含んだ二酸化シリコ
ン)12を成膜する。膜厚は5,000〜10,000
オングストローム程度で、含まれているボロン、リンの
濃度は、いずれも2〜10重量%程度である。そして、
周知の微細加工技術によりコンタクト孔14を形成す
る。After that, a BPSG film (silicon dioxide containing boron and phosphorus) 12 which is an interlayer insulating film is formed by a well-known CVD method. The film thickness is 5,000 to 10,000
The concentration of boron and phosphorus contained is about 2 to 10% by weight in the order of angstrom. And
The contact hole 14 is formed by a known fine processing technique.
【0014】次に、図1bに示すように、コンタクト孔
14の形成後、周知のCVD法により窒化シリコン膜1
5を厚さ500〜1,000オングストローム程度に成
膜する。Next, as shown in FIG. 1b, after forming the contact hole 14, the silicon nitride film 1 is formed by a well-known CVD method.
5 is deposited to a thickness of about 500 to 1,000 angstroms.
【0015】次に、図1cに示すように周知の方向性エ
ッチング、例えば、反応性イオンエッチング(RIE)
法により、コンタクト孔14の側壁以外の部分の窒化シ
リコン膜15を除去する。Next, as shown in FIG. 1c, well-known directional etching, for example, reactive ion etching (RIE) is performed.
By the method, the silicon nitride film 15 on the portion other than the side wall of the contact hole 14 is removed.
【0016】次に、図1dに示すように、ポリシリコン
膜16を周知のCVD法を用いて、コンタクト孔14が
充分に埋め込まれるまで堆積させる。Next, as shown in FIG. 1d, a polysilicon film 16 is deposited using a well-known CVD method until the contact holes 14 are sufficiently filled.
【0017】そして、図1eに示すように、方向性エッ
チングにより全面をエッチングし、コンタクト孔14以
外の部分のポリシリコン16を除去する。その後、埋め
込んだポリシリコン膜16への不純物拡散を行うため、
ボロン(11B+ )またはフッ化ホウ素(49BF2 + )イ
オンを周知の方法によりイオン注入17する。Then, as shown in FIG. 1e, the entire surface is etched by directional etching to remove the polysilicon 16 in the portions other than the contact holes 14. After that, in order to diffuse impurities into the buried polysilicon film 16,
Boron ( 11 B + ) or boron fluoride ( 49 BF 2 + ) ions are ion-implanted 17 by a known method.
【0018】最後に、800〜1,000℃程度の熱処
理により不純物の活性化、拡散を行い、さらに、金属膜
の成膜を、例えば、スパッタ法により行い、そして、微
細加工技術によるパターニングを行って半導体装置が製
造される。Finally, the impurities are activated and diffused by a heat treatment at about 800 to 1,000 ° C., a metal film is formed by, for example, a sputtering method, and patterning is performed by a fine processing technique. And a semiconductor device is manufactured.
【0019】[0019]
【発明の効果】以上説明したように、本発明によれば、
層間絶縁膜であるBPSG膜からのリンの拡散を防止で
き、P型拡散層上の埋め込みポリシリコンコンタクトの
抵抗を安定にして、かつ低くすることが可能である。As described above, according to the present invention,
Phosphorus can be prevented from diffusing from the BPSG film which is the interlayer insulating film, and the resistance of the buried polysilicon contact on the P-type diffusion layer can be stabilized and lowered.
【0020】この技術を用いることにより、高集積化さ
れたアスペクト比の高いコンタクト孔で、信頼性が高
く、特性のよい半導体装置を製造することができる。By using this technique, it is possible to manufacture a semiconductor device having a highly integrated contact hole with a high aspect ratio, high reliability, and good characteristics.
【図1】は、本発明の一実施例である半導体装置の製造
方法の工程順序を示す断面概略図である。FIG. 1 is a schematic sectional view showing a process sequence of a method of manufacturing a semiconductor device according to an embodiment of the present invention.
【図2】は、従来の技術による半導体装置の製造方法の
工程順序を示す断面概略図である。FIG. 2 is a schematic cross-sectional view showing a process sequence of a method for manufacturing a semiconductor device according to a conventional technique.
11…シリコン半導体基板、 12…BPSG膜、 13…不純物拡散層、 14…コンタクト孔、 15…窒化シリコン膜、 16…ポリシリコン膜、 17…不純物イオン注入、 21…シリコン半導体基板、 22…BPSG膜、 23…不純物拡散層、 24…コンタクト孔、 26…ポリシリコン膜、 27…不純物イオン注入。 11 ... Silicon semiconductor substrate, 12 ... BPSG film, 13 ... Impurity diffusion layer, 14 ... Contact hole, 15 ... Silicon nitride film, 16 ... Polysilicon film, 17 ... Impurity ion implantation, 21 ... Silicon semiconductor substrate, 22 ... BPSG film 23 ... Impurity diffusion layer, 24 ... Contact hole, 26 ... Polysilicon film, 27 ... Impurity ion implantation.
Claims (2)
だ後、金属膜を成膜する半導体装置の製造方法におい
て、 拡散層を有する半導体基板上に成膜した層間絶縁膜にコ
ンタクト孔を開口する工程と、 前記コンタクト孔を含む全面に不純物拡散防止膜を成膜
する工程と、 前記コンタクト孔の側壁部の前記不純物拡散防止膜を残
して前記不純物拡散防止膜を除去する工程と、 前記コンタクト孔内にポリシリコン膜を堆積させ前記コ
ンタクト孔を完全に埋め込む工程と、 前記ポリシリコン膜に前記拡散層と同一の導伝型の不純
物を注入し、活性化し拡散する工程とを具備することを
特徴とする半導体装置の製造方法。1. A method of manufacturing a semiconductor device in which a metal film is formed after burying polysilicon in the contact hole, and a step of forming a contact hole in an interlayer insulating film formed on a semiconductor substrate having a diffusion layer, A step of forming an impurity diffusion prevention film on the entire surface including the contact hole; a step of removing the impurity diffusion prevention film leaving the impurity diffusion prevention film on a sidewall portion of the contact hole; The method further comprises: a step of depositing a polysilicon film to completely fill the contact hole; and a step of injecting the same conductivity type impurity as that of the diffusion layer into the polysilicon film to activate and diffuse it. Method of manufacturing semiconductor device.
る請求項1に記載の半導体装置の製造方法。2. The method for manufacturing a semiconductor device according to claim 1, wherein the impurity diffusion preventing film is made of silicon nitride.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP25092291A JPH0590196A (en) | 1991-09-30 | 1991-09-30 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP25092291A JPH0590196A (en) | 1991-09-30 | 1991-09-30 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0590196A true JPH0590196A (en) | 1993-04-09 |
Family
ID=17215022
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP25092291A Withdrawn JPH0590196A (en) | 1991-09-30 | 1991-09-30 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0590196A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100244706B1 (en) * | 1996-11-22 | 2000-03-02 | 김영환 | Semiconductor device and its manufacturing method |
| US6043130A (en) * | 1999-05-17 | 2000-03-28 | National Semiconductor Corporation | Process for forming bipolar transistor compatible with CMOS utilizing tilted ion implanted base |
| US6262472B1 (en) | 1999-05-17 | 2001-07-17 | National Semiconductor Corporation | Bipolar transistor compatible with CMOS utilizing tilted ion implanted base |
-
1991
- 1991-09-30 JP JP25092291A patent/JPH0590196A/en not_active Withdrawn
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100244706B1 (en) * | 1996-11-22 | 2000-03-02 | 김영환 | Semiconductor device and its manufacturing method |
| US6043130A (en) * | 1999-05-17 | 2000-03-28 | National Semiconductor Corporation | Process for forming bipolar transistor compatible with CMOS utilizing tilted ion implanted base |
| US6262472B1 (en) | 1999-05-17 | 2001-07-17 | National Semiconductor Corporation | Bipolar transistor compatible with CMOS utilizing tilted ion implanted base |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A300 | Withdrawal of application because of no request for examination |
Free format text: JAPANESE INTERMEDIATE CODE: A300 Effective date: 19981203 |