JPH059031U - High precision filter device - Google Patents

Abstract

(57) [Summary] [Object] To suppress an increase in hardware scale and arithmetic processing time of a high-precision filter device suitable as an IIR filter for LPF, and to improve the accuracy of filter coefficients. [Structure] Data X (n), X (n-
1), X (n-2) are read out, and attenuators 15, 1
The filter coefficients A0, A1, and A2 multiplied by f in the feedforward section are set in 6 and 17, and the multiplication is performed with the above data, and the result is stored in the accumulator 11. Memory 2
By reading 1 / f from 3 and setting it in the attenuator 22, the content of the accumulator 11 is made 1 / f and stored in the accumulator 12. Data Y (n-
1), Y (n-2) are read out, and attenuators 20, 21
Then, the filter coefficients B1 and b2 of the feedback section are set, and multiplication with the above data is performed, and the accumulator 1
2 and stores the calculation result Y from the accumulator.
(N) is output.

Description

[Detailed description of the device]

[0001]

[Industrial applications]

  The present invention is applied to car audio, home audio, etc., for example, DSP processing. The present invention relates to a high-precision filter device used in a circuit or the like, and particularly to an LPF (low-pass filter). ) Is composed of a second-order IIR (Infinite Impulse Response) filter The present invention relates to a configuration for improving the accuracy of filter coefficients when performing.

[0002]

[Prior art]

  Generally, the second-order IIR filter has a structure as shown in FIG.   In the figure, 1 is an adder, 2-1 to 2-5 are attenuators (or multipliers), 3 -1 to 3-4 are delay circuits, and a0, a1, a2, b1 and b2 are the attenuator 2 respectively. It is a filter coefficient set by -1 to 2-5.

[0003]   In the IIR filter, X (n) is the input data signal and Y (n) is from the adder 1. This is the output composite signal, which is the output data signal. Input data signal X (n) And the output data signal Y (n) is delayed by the delay circuits 3-1 and 3-3, Signals X (n-1) and Y (n-1), and Xn-1 and Yn-1 are the delay circuit 3 The delayed data signals X (n-2) and Y (n-2) are delayed by -2 and 3-4. In addition, (n) represents a subscript of X in X (n) and the like.

[0004]   Each data signal X (n), X (n-1), X (n-2), Y (n-1), Y (N-2) is multiplied by each filter coefficient set by the attenuators 2-1 to 2-5. Are combined in the adder 1.

[0005]   When the above arithmetic processing is displayed by a mathematical expression, it becomes as shown in Expression (1).   Yn = a0 * Xn + a1 * Xn-1 + a2 * Xn-2 + b1 * Yn-1         + B2 * Yn-2 (1)

[0006]

[Problems to be solved by the device]

  However, the conventional IIR filter described above has the following drawbacks.

[0007]   (I) First, each filter coefficient of a0 to b2 is calculated from desired characteristics (transfer function) However, the number of digits in the register that holds each filter coefficient is finite. Therefore, an error occurs between the filter coefficient used for actual processing and the theoretical value.

[0008]   For example, assuming that the theoretical value of the filter coefficient a0 is 0.417531294, Assuming that the number of digits of the register is 8, as shown in FIG. The minimum two digits are truncated, resulting in an error of 0.0000000094. Clear from the figure As can be seen, if the theoretical value of the filter coefficient becomes smaller, the error rate increases. Accuracy becomes worse.

(Ii) Since some of the filter coefficients take values in the range of +1 to +2, a fixed point (a value that can be expressed in the range of −1 to +1 and a determined bit length, for example, a bit length is If it is 16, if it is configured by hardware that can handle only -1 to 1/2 + ¹⁵ in steps of ¹⁵ ), set each filter coefficient to 1/2 in advance, and then perform shift processing (1 bit left shift). I was dealing with it. However, this shift processing further deteriorates the accuracy of the filter coefficient. For example, when 0.84375 is displayed with a fixed decimal point, it is expressed in the following form (binary number display).

0.84375 = 0.5 + 0.25 + 0.0625 + 0.03125 = 1/2 ¹ × 1 + 1/2 ² × 1 + 1/2 ⁴ × 1 + 1/2 ⁵ × 1 = 011011 (However, the highest "0" is a code Means a plus sign)

[0011]   Therefore, when the filter coefficient takes a value over 1, Set the number to 1/2 (shift 1 bit to the right in binary display) to a number less than 1. To process.

[0012]             1 bit shift right   011011 → 0011011 = 0.25 + 0.125 + 0.03125 + 0.015625                                   = 0.416875             0.84375 x 1/2 = 0.416875 After processing, double the value halved (shift 1 bit to the left in binary display) It

[0013]   By the way, setting the numerical value of the filter coefficient to 1/2 in this way is a binary number display. Since it is to shift 1 bit to the right in the above, as shown in FIG. Since the length (number of digits) of the register that holds is fixed, the least significant bit is Therefore, the filter coefficient accuracy is deteriorated.

[0014]   (Iii) Furthermore, when the IIR filter is used as an LPF, each filter Of the filter coefficients, the filter coefficients (a0, a1, a2) of the feedforward section are Since it is extremely small compared to other filters, it is processed by the same hardware (register). If you try to make sense, the error will increase and the accuracy will deteriorate. Therefore, conventional If this happens, increase the length of the register that holds the filter coefficient. I had to do it.

[0015]   In this case, the number of filter coefficients can be used as a method of processing without changing the register length. The value is divided into upper and lower values and stored in a register, and processed separately (data and There is also a method of multiplying and adding later.

[0016]   For example, filter coefficient a0 = 0.41753129407, input data Xn = When the processing of a0 * Xn is set to 0.5, as shown in FIG. Retain 0.417531, 0.29407 in M (or register) respectively Then, multiplication and addition are performed.   However, according to this method, although the accuracy is improved, the arithmetic processing is divided into two times, A register or memory that holds the filter coefficients divided into lower and upper ranks is required. Since it is necessary, the processing time and the scale of hardware will be almost doubled. There was a problem.

[0017]   The object of the present invention is to suppress the increase in hardware scale and processing time, and to further improve the filter coefficient. High accuracy suitable as an IIR filter for LPF that can improve the accuracy of It is to provide a filter device.

[0018]

[Means for Solving the Problems]

  In order to achieve the above-mentioned object, the present invention provides an input data signal for receiving the input data signal. Signal and a plurality of first delay data obtained by delaying this input data signal with different delay times. A first delay means for outputting the data signal,   Each of the first delayed data signals is attenuated by a predetermined different coefficient, The first attenuating means for outputting a plurality of corresponding first attenuating signals and the respective first attenuating signals. A synthesizing means for outputting the synthesized signal obtained,   A plurality of second delay data signals obtained by delaying the composite signal with a plurality of different delay times, Second delay means for outputting,   Attenuating each of the second delayed data signals with a coefficient different from that of the first attenuating means, A plurality of second attenuated signals corresponding to the respective second delayed data signals, and In a high-precision filter device including a second attenuating means for combining by a combining means , Multiplying the plurality of first attenuated signals by a predetermined numerical value, Multiplication means for outputting to the synthesis means,   Dividing means for dividing the combined signal by the predetermined numerical value,   The second delay data signal from the second delay means and the second delay data signal from the second delay means. By combining the second attenuation signal from the second attenuation means with the first and second attenuation signals. It is characterized in that the accuracy of the coefficient attenuation processing by the attenuation means is improved.

[0019]

[Action]   In the filter device of the present invention, the input data signal is delayed by a plurality of different delay times. Are delayed into a plurality of first delayed data signals, each first delayed data signal having a different coefficient. Are attenuated by a number to form a plurality of first attenuation signals, and these first attenuation signals are combined. Then, the combined signal is output. This composite signal is delayed with different delay times. Into a plurality of second delayed data signals, each second delayed data signal being reduced by a different coefficient. It is attenuated to form a second attenuated signal, which is combined with the first attenuated signal. Thus, the first attenuation signal The number is multiplied by a predetermined number and output to the combining means, and the combined signal is the reciprocal of the above specified number. Is multiplied by.

[0020]

【Example】

  An embodiment of the present invention shown in the drawings will be described below.   FIG. 1 shows a second-order IIR filter for LPF, which is an embodiment of the high-precision filter device of the present invention. The configuration of the computer is shown below. In the figure, 11 and 12 are adders (accumulators). , Which constitutes a synthesizing means. Reference numerals 13 and 14 are delay circuits, which constitute the first delay means. It Reference numerals 15 to 17 denote attenuators, which constitute the first attenuating means. 18 and 19 are delay circuits Then, the second delay means is configured. 20 and 21 are attenuators, which constitute the second attenuating means. It

[0021]   22 is an attenuator, which functions as a dividing means. 23 is a memory, which will be described later. The filter coefficient of the feedforward section is multiplied by f in advance and stored. It has the function of multiplication means. A control unit (CPU) 24 has filter coefficients (A0 to A0). b2) and data (X (n) to Y (n-2)) are read from the memory 23 and written. Performs controls such as cutting.

[0022]   When the LPF is designed to be composed of IIR filters, As a feature, as described above, (i) the value of the filter coefficient of the feedforward unit ( a0, a1, a2) is extremely small, and (ii) the filter of the feedback section One of the coefficients (b1) can take a value in the range of +1 to +2. .

[0023]   In the present invention, in consideration of the above-mentioned matters, the equation (1) is modified as follows. As shown in the equation (2), the equation (2) is changed to the filter coefficient of the present invention. It is the basis of calculation processing by.   Yn = a0 * Xn + a1 * Xn-1 + a2 * Xn-2 + b1 * Yn-1         + B2 * Yn-2 (1)   Yn = (a0 * Xn + a1 * Xn-1 + a2 * Xn-2) * f * (1 / f) +         (B1-1) * Yn-1 + Yn-1 + b2 * Yn-2   Yn = {(a0 * f) * Xn + (A1 * f) * Xn-1 + (a2 * f) * Xn-2}           * (1 / f) + (b1-1) * Yn + Yn-1 + b2 * Yn-2   Yn = (A0 * Xn + A1 * Xn-1 + A2 * Xn-2) * (1 / f)           + B1 * Yn-1 + Yn-1 + b2 * Yn-2 (2)   However, A0 = a0 * f, A1 = a1 * f, A2 = a2 * f, B1 = b1-1

[0024]   That is, in the present invention, the feed-forward section filter that takes an extremely small value is used. The calculation value of the feedforward section is calculated by using the coefficient value obtained by multiplying the filter coefficient by f times (f> 1). After processing, the output is 1 / f. As described above, by multiplying by f, The lower digit of the coefficient value that was truncated due to register length limitation is used. Therefore, the accuracy is improved.   In addition, the operation (b1 * Y (n-1)) that handles filter coefficients exceeding +1 is divided into Therefore, it is necessary to reduce the filter coefficient to 1/2 as in the conventional case. The accuracy is improved compared to the conventional one.

[00025]   Next, the operation of the above embodiment will be described with reference to the flowchart of FIG.   First, in step ST1 of FIG. The filter coefficients A0 (a0xf), A1 (a1xf) and A2 (a2xf) It is stored in the memory 23. In step ST2, it is determined whether or not data has been input, and NO. If this is the case, this determination is performed again, but if YES, then in step ST3 Read A0 and data X (n) from the memory 23, set A0 in the attenuator 15 and set A0. 0 * X (n) is stored in the accumulator 11. In steps ST4 and ST5, A1, A2, X (n-1), and X (n-2) are read from the memory 23, and A1, A2 Is set in the attenuators 16 and 17, and the result is multiplied, and the result is stored in the accumulator. It is stored in 11.

[0026]   Next, in step ST6, 1 / f is read from the memory 23 and the attenuator 22 is read. By setting to, the content of accumulator 11 is multiplied by (1 / f) and the result is The fruit is stored in the accumulator 12. In step ST7, the memory 23 to B1 , Y (n-1) are read, B1 is set in the attenuator 20, and multiplied by Y (n-1). Then, the result is added to the contents of the accumulator 12, and the addition output is added to the accumulator 1 Store in 2. In step ST8, Y (n-1) is read from the memory 23 The contents are added to the contents of the accumulator 12 and stored in the accumulator 12. And At step ST9, b2 and Y (n-2) are read from the memory 23 and b2 is read. Multiply by setting in the attenuator 21, the result is the contents of the accumulator 12 And the added output is stored in the accumulator 12. Then step 10 Outputs the processing result Y (n) of the accumulator 12, and in step 11, the memory 23 Update the data of (update over the old data).

[0027]   The attenuator 22 for multiplying the filter coefficient by 1 / f is obtained by multiplying 1 / f by 2. If it is displayed in exponentiation, it may be used as a shift register. Also, all of these processes, It is also possible to use a DSP (Digital Signal Processor) or the like.

[0028]

[Effect of device]

  As described above, according to the high-precision filter device of the present invention, the hardware scale and processing IIF filter LPF according to the conventional configuration method without significantly changing the time It is possible to realize a more accurate LPF.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a filter device of the present invention.

FIG. 2 is a flowchart for explaining the operation of the above embodiment.

FIG. 3 is a block diagram showing a configuration of a conventional IIR filter.

4 is an explanatory diagram of a calculation method by the IIR filter of FIG.

[Explanation of symbols]

11,12 Adder (accumulator) 13, 14, 18, 19 Delay circuit 15,16,17,20,21,22 attenuator 23 memory 24 Control unit (CPU)

Claims (2)

[Scope of utility model registration request] 1. A first delay means for inputting an input data signal and outputting the input data signal and a plurality of first delayed data signals obtained by delaying the input data signal with a plurality of different delay times; First attenuating means for attenuating the first delayed data signal with a predetermined different coefficient to output a plurality of first attenuating signals corresponding to the respective signals, and a synthetic signal obtained by synthesizing the first attenuating signals. A second delay means for outputting a plurality of second delayed data signals obtained by delaying the combined signal with a plurality of different delay times; and a second attenuating means for outputting each of the second delayed data signals. A high-precision filter device comprising: a first attenuating signal that is attenuated by different coefficients, and a plurality of second attenuating signals corresponding to the respective second delayed data signals, and a second attenuating means that is combined by the combining means The plurality of 1 multiplication signal which multiplies a 1 attenuation signal by a predetermined numerical value, and outputs the obtained multiplication data signal to said synthesizing means, division means which divides said synthetic signal by said predetermined numerical value, said synthesizing means, said second delay By combining the second delayed data signal from the means and the second attenuated signal from the second attenuating means, it is possible to improve the accuracy of the coefficient attenuating process in the first and second attenuating means. Characteristic high precision filter device. 2. A storage means for storing the coefficient and the data signal, and a control means for controlling reading and writing of the coefficient and the data signal from the storage means to the respective means at a predetermined timing. The high precision filter device according to claim 1.