JPH0590331A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To prevent the exfoliation of an electrode pad from a dielectric film by setting a junction area between the electrode pad and the dielectric film large as compared with a junction area between the electrode pad and a metal brazing material. CONSTITUTION:There are provided, a semiconductor substrate 1 on the surface of which elements are formed, a dielectric film 3 formed over the surface of the semiconductor substrate 1 on which the elements are formed, and electrode pads 4, 5, and 7 disposed on the surface of this dielectric film 3. There are also provided an interconnection layer 2 buried in the dielectric film 3 for electrically connecting the elements with each other or the elements with the electrode pads 4, 5 and 7, and micro pins 9 bonded to the electrode pads 4, 5 and 7 by means of a metal brazing material 8. A junction area between the electrode pads 4, 5 and 7 and the dielectric film 3 is set large as compared with a junction area between the electrode pads 4, 5 and 7 and the metal brazing material 8. Thereby, the bonding strength produced the dielectric film 3 and the electrode pads 4, 5 and 7 is large, and hence it is possible to prevent the exfoliation of the electrode pads 4, 5 and 7.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device mounted on a substrate made of ceramic or the like via micro pins arranged in a direction perpendicular to an element formation surface of a semiconductor chip.

[0002]

2. Description of the Related Art Recently, with the increase in scale of semiconductor chips, it is desired to increase the number of external connection terminals per semiconductor chip. Therefore, in contrast to the method of arranging the electrode pads in the area around the chip where the elements are not arranged and connecting the leads in the horizontal direction to the element formation surface of the chip, the electrode pads are arranged over the entire surface of the chip. The surface mounting method has been adopted in which leads are connected in a direction perpendicular to the element formation surface of the chip.

FIG. 5 is a schematic sectional view showing an example of this type of semiconductor integrated circuit device (Japanese Patent Application No. 63-279789).

The semiconductor integrated circuit has a silicon semiconductor substrate 2 having elements formed on its surface (lower side surface in FIG. 5).
1. The wiring 22 for electrically connecting the elements and the insulating film 23 filling the wiring 22. An opening reaching the wiring 22 is provided in the uppermost film (that is, the passivation film) of the insulating film 23, and an electrode pad for external connection is provided in the opening. This electrode pad is composed of a titanium tungsten film 24,
The gold film 25 and the gold pad 27 are laminated. Note that the titanium-tungsten film 24 and the gold film 2 are usually used.
5 is formed by a sputtering method, and the gold pad 27 is formed by a plating method.

One end of the micro pin 29 is fixed to the electrode pad for external connection by a brazing metal material 28 (eg, gold-tin eutectic alloy).

This semiconductor integrated circuit device is mounted on, for example, a ceramic multilayer wiring board 30 via micro pins 29. That is, predetermined wiring and electrodes 31 are provided on the surface of the ceramic multilayer wiring board 30. The ends of the micro pins 29 of the semiconductor integrated circuit device are fixed to the electrodes 31 with solder 32.

[0007]

However, in the conventional semiconductor integrated circuit device having the above-mentioned structure, the micro pin 29 is affected by stress and impact due to temperature change.
Between the pad and the pad, between the pad and the passivation film, and between the metal films forming the pad, there is a problem that peeling easily occurs. Generally, since the bonding force between metals is strong, peeling is usually most likely to occur at the interface between a passivation film made of a silicon nitride film or a polyimide resin film and an electrode pad made of metal.

The present invention has been made in view of the above problems, and a semiconductor integrated circuit device having a high bonding force between a passivation film and an electrode pad, which can suppress peeling of the electrode pad and has high reliability. The purpose is to provide.

[0009]

In a semiconductor integrated circuit device according to the present invention, a semiconductor substrate having an element formed on the surface thereof, an insulating film formed on the element forming surface of the semiconductor substrate, and the insulating film are provided. An electrode pad disposed on the surface of the wiring layer, a wiring layer that is embedded in the insulating film and electrically connects the elements or between the element and the electrode pad, and is joined to the electrode pad by a metal brazing material. The bonding area between the electrode pad and the insulating film is larger than the bonding area between the electrode pad and the metal brazing material.

[0010]

In the present invention, the bonding area between the electrode pad and the insulating film is set larger than the bonding area between the electrode pad and the metal brazing material for micropin bonding. Therefore, the bonding strength between the electrode pad and the insulating film is high, and the electrode pad can be prevented from peeling off from the insulating film.

[0011]

Embodiments of the present invention will now be described with reference to the accompanying drawings.

FIG. 1A is a sectional view showing a semiconductor integrated circuit device according to the first embodiment of the present invention.

The semiconductor integrated circuit chip comprises a silicon semiconductor substrate 1 on which elements are formed and wirings 2 formed on the surface thereof.
And the interlayer film 3 (insulating film). The uppermost layer of the interlayer film 3 (passivation film; for example, plasma S
An opening reaching the wiring 2 is formed in the iON film and has a thickness of 1.0 μm), and an electrode pad for external connection is arranged in this opening. This electrode pad is composed of a titanium-tungsten film 4 (thickness is about 1000Å), a gold film 5 (thickness is about 1000Å) and a gold pad 7 (thickness is about 3 μm). Micro pins 9 are fixed to the surface of the gold pad 7 by a brazing metal material 8.

FIG. 1B is a sectional view showing a method of manufacturing the above-mentioned semiconductor integrated circuit device.

First, an interlayer film 3 is formed on a semiconductor substrate 1 on the surface of which an element is provided, and wiring 2 is formed on the interlayer film 3.
To form. By repeating this a plurality of times, the substrate 1
A multilayer wiring pattern is formed on top. After that, a passivation film is formed as the uppermost layer film of the interlayer film 3.

Next, after forming an opening reaching the wiring 2 in a predetermined region of the interlayer film 3, a titanium tungsten film 4 and a gold film 5 are formed to a thickness of about 1000 Å by a sputtering method. After that, a resist 6 is selectively formed on the gold film 5 using a photolithography technique, and gold plating is performed to about 3.4 μm.
To form a gold pad 7 for external connection.

In general, as a characteristic of the plating method, even if there is a step at the bottom, the surface of the plating layer becomes gentle as the thickness of the plating layer becomes thicker, so that the upper surface of the gold pad 7 becomes substantially flat. Further, the area between the adjacent pads is set to the minimum value determined by the photolithography technique or the etching technique in the subsequent etching process of the gold film 5 and the titanium-tungsten film 4 so that the area of the gold pad 7 is as small as possible. Increase to. For example, the diameter of the micro pin
Assuming 100 μm, the minimum pad value is about 1 side.
It is a square of 50 μm. Assuming that the pad pitch is 250 μm, current ion milling technology enables sufficient electrical isolation if the distance between adjacent pads is 5 μm. Therefore, the size of the pad can be expanded to a square having a side of 245 μm.

Then, after removing the resist 6, the gold pad 7 is etched by ion milling or the like as in the conventional case.
The gold film 5 and the titanium-tungsten film 4 in the region other than the portion covered with the are removed. At this time, the surface of the gold pad 7 is also slightly etched, but it suffices if the gold pad 7 remains with a thickness of 3 μm or more. Then, a gold brazing material 8 (for example, a gold-tin eutectic alloy) is attached to the tips of the micro pins 9, and the gold brazing material 8 is arranged vertically to the gold pad 7 and heated and fixed. This allows
The semiconductor integrated circuit device of this embodiment shown in FIG. 1A is completed.

In the present embodiment, the bonding area between the gold pad 7 and the interlayer film 3 is wider than the conventional one and the bonding strength is high, so that peeling of the electrode pad can be avoided.

FIG. 2 is a sectional view showing a semiconductor integrated circuit device according to the second embodiment of the present invention.

When the area of the pad is expanded as described in the first embodiment, the metal brazing material 8 easily spreads over a wide area of the pad surface. If the brazing filler metal spreads thinly on the pad surface, the film thickness of the metal brazing filler metal 8 around the micropins 9 becomes thin, and there is a possibility that connection failure of the micropins 9 may occur.

Therefore, in this embodiment, as shown in FIG. 2, a convex portion 10 is provided on the surface of the pad for suppressing the spread of the metal brazing material. The semiconductor integrated circuit according to this embodiment is formed by, for example, the method described below.

First, as in the first embodiment, FIG.
As shown in (b), after forming the pad and removing the resist 6, a second resist is formed and gold plating is performed to form the convex portion 10 on the gold pad 7 in a shape surrounding the bonding region with the micropin. Form. Then, after the second resist is removed, the entire surface is etched by ion milling or the like to remove the gold film 5 and the titanium-tungsten film 4 in the region other than the part covered with the gold pad 7 as in the conventional case. After that, a metal brazing material 8 (for example, a gold-tin eutectic alloy) is attached to the tips of the micropins 9, the metal brazing material 8 is arranged vertically to the gold pad 7, and heating is performed to fix it. As a result, the semiconductor integrated circuit device according to this embodiment is completed.

In the present embodiment, since the spread of the metal brazing material 8 can be suppressed, it is possible to prevent the metal brazing material 8 around the micropins 9 from having a thin film thickness and avoiding poor connection. be able to.

FIG. 3 is a sectional view showing a semiconductor integrated circuit device according to the third embodiment of the present invention.

The present embodiment is different from the first embodiment in that recesses are provided also in the portions other than the micropin joint portion of the electrode pad, and other configurations are basically the first embodiment. 3, the same components as those in FIG. 1 are designated by the same reference numerals and detailed description thereof will be omitted.

In the present embodiment, when an opening reaching the wiring 2 is provided in the uppermost layer film (passivation film) of the interlayer film 3, the opening is also provided in a portion without wiring. Then, the titanium tungsten film 4 and the gold film 5 are formed by the sputtering method. Next, a resist 6 is formed by a photolithography technique and gold plating is performed to form a gold pad 7 for external connection. Then, the area of the portion of the lower surface of the external connection pad which is in contact with the interlayer film 3 is increased by the area of the side wall of the extra opening. After that,
The micropins are connected in the same manner as in the first embodiment.

As a result, the bonding strength between the pad and the interlayer film can be further improved as compared with the first embodiment. Also in this embodiment, similarly to the second embodiment, a convex portion may be provided around the micropin joint portion of the pad. As a result, the bonding strength between the pad and the micro pin can be improved.

FIG. 4 is a sectional view showing a semiconductor integrated circuit device according to the fourth embodiment of the present invention.

This embodiment is different from the third embodiment in that the dummy pattern 11 is embedded in the interlayer film 3, and the other structure is basically the same as that of the third embodiment. 4, the same parts as those in FIG. 3 are designated by the same reference numerals, and detailed description thereof will be omitted.

In this embodiment, the dummy pattern 11 is formed when the wiring layer 2 is formed. Then, when forming the opening reaching the wiring in the uppermost layer film (passivation film) of the interlayer film 3, the opening reaching the dummy pattern 11 is formed. Then, the pad and the dummy pattern 11 are joined.

In this embodiment, it is possible to obtain the effect that the pad is more difficult to peel off as compared with the third embodiment.

[0033]

As described above, according to the present invention,
Since the bonding area between the electrode pad and the insulating film is set to be larger than the bonding area between the electrode pad and the metal brazing material for micropin bonding, the bonding strength between the electrode pad and the insulating film is high, It is possible to prevent the electrode pad from peeling off from the insulating film.

[Brief description of drawings]

1A is a cross-sectional view showing a semiconductor integrated circuit device according to a first embodiment of the present invention, and FIG. 1B is a cross-sectional view showing the same manufacturing method.

FIG. 2 is a sectional view showing a semiconductor integrated circuit device according to a second embodiment of the present invention.

FIG. 3 is a sectional view showing a semiconductor integrated circuit device according to a third embodiment of the present invention.

FIG. 4 is a sectional view showing a semiconductor integrated circuit device according to a fourth embodiment of the present invention.

FIG. 5 is a sectional view showing a conventional semiconductor integrated circuit device.

[Explanation of symbols]

 1, 21; Substrate 2, 22; Wiring 3; Interlayer film 4, 24; Titanium tungsten film 5, 25; Gold film 6; Resist 7, 27; Gold pad 8, 28; Metal brazing material 9, 29; Micropin 10 ; Convex portion 11; dummy pattern

Claims (1)

[Claims] 1. A semiconductor substrate having an element formed on the surface thereof, an insulating film formed on the element forming surface of the semiconductor substrate, an electrode pad provided on the surface of the insulating film, and the insulating film. A wiring layer that is embedded in a film and electrically connects the elements or between the element and the electrode pad, and a micropin joined to the electrode pad by a metal brazing material, and the electrode pad and the insulation A semiconductor integrated circuit device characterized in that a bonding area with a film is larger than a bonding area between the electrode pad and the metal brazing material.