JPH0590423A - Semiconductor device - Google Patents

Abstract

PURPOSE:To attain excellent flatness of an interlayer insulating film together and to realize a stable electric connection by making etching back of a silica film unneccesary. CONSTITUTION:After a silicon oxide film 4, a silica film 5 formed by an application method and a silicon oxide film 6 are formed one after another on the surface including a lower wiring 3 consisting of a metal film, a via hole 7 isopened and an upper layer wiring 88 consisting of a metal film is formed so as to connect the wirings 3, 8. Thereby, flatness of an interlayer insulating film is improved with requiring no etching back by using gold as a wiring material.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device having multi-layer wiring.

[0002]

2. Description of the Related Art As the density of semiconductor devices has increased, the number of wiring layers has increased, and the planarization of interlayer insulating films has become more and more important.

FIGS. 4A to 4F are cross-sectional views of a semiconductor chip showing the order of steps for explaining a conventional method for manufacturing a semiconductor device.

First, as shown in FIG. 4A, the aluminum wiring 9 is selectively provided on the insulating film 2 provided on the semiconductor substrate 1.

Next, as shown in FIG. 4B, a silicon oxide film 4 is deposited on the surface including the aluminum wiring 9 by a plasma CVD method, and a silicon compound is applied on the silicon oxide film 4 by a coating method. 400 ℃ after forming the film
The silica film 5 is formed by performing a heat treatment to some extent.

Next, as shown in FIG. 4C, the silica film 5 is etched back by a plasma etching method to expose the surface of the silicon oxide film 4 on the aluminum wiring 9.

Next, as shown in FIG. 4D, a silicon oxide film 6 is deposited on the surface including the silicon oxide film 4 by the plasma CVD method.

Next, as shown in FIG. 4E, the silicon oxide films 6 and 4 on the aluminum wiring 9 are selectively and sequentially etched by a photolithography technique to form a via hole 7.

Next, as shown in FIG. 4 (f), an aluminum film is deposited on the surface including the via holes 7 and then patterned to form the upper aluminum wiring 10.

By using the silica film 5, such a multilayer wiring structure has a relatively excellent flatness of the interlayer insulating film. Here, it is necessary that the silica film 5 is not exposed on the side surface of the via hole 7, and if the silica film 5 is exposed on the side surface of the via hole 7. Moisture is released from the silica film 5 when the upper aluminum wiring 10 is formed, and the moisture oxidizes the surface of the aluminum wiring 9 to hinder the electrical connection between the aluminum wiring 9 and the aluminum wiring 10.

[0011]

In this conventional semiconductor device, in order to obtain a stable electrical connection between the lower layer wiring and the upper layer wiring, it is essential to etch back the silica film formed by the coating method. For this reason, there is a drawback in that the flatness of the interlayer insulating film is sacrificed to some extent in addition to the increase in the manufacturing process.

The object of the present invention is to eliminate the above-mentioned drawbacks and to eliminate the need for etching back the silica film, thereby providing a multi-layer wiring structure which can not only shorten the manufacturing process but also achieve excellent flatness of the interlayer insulating film. That is.

[0013]

The semiconductor device of the present invention comprises:
An interlayer insulating film having a laminated structure of a lower layer wiring having a gold film on at least an upper surface provided on a semiconductor substrate, an inorganic insulating film provided on the surface including the wiring, and a silica film formed by a coating method; An interlayer insulating film is provided as an opening and a via hole exposing the silica film on the side surface, and an upper layer wiring connected to a lower layer wiring of the via hole are provided.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIGS. 1A to 1D are cross-sectional views of a semiconductor chip shown in the order of steps for explaining a first embodiment of the present invention.

First, as shown in FIG. 1A, a gold film having a thickness of 1 μm is deposited and patterned on an insulating film 2 provided on a semiconductor substrate 1 to form a lower wiring 3. .

Next, as shown in FIG. 1B, a silicon oxide film 4 is deposited to a thickness of 0.2 μm on the surface including the wiring 3 by a plasma CVD method, and then a silicon compound is added to an organic solvent by a coating method. A coating film containing the same is formed, the surface of the silica film 5 is flattened by heat treatment at about 400 ° C., and a silicon oxide film 6 is deposited on the silica film 5 by plasma CVD to a thickness of 0.2 μm.

Next, as shown in FIG. 1C, the silicon oxide film 6 on the wiring 3 is formed by photolithography.
Via holes 7 are formed by selectively sequentially opening the silica film 5 and the silicon oxide film 4.

Next, as shown in FIG. 1D, a gold film is deposited on the surface including the via hole 7 and patterned to form an upper wiring 8 which is connected to the wiring 3 of the via hole 7.

In the multilayer wiring thus formed, since the lower wiring 3 is a gold film, water is released from the silica film 5 of the via hole 7 when the gold wiring of the upper wiring 8 is formed. However, the surface of the wiring 3 is not oxidized and a stable electrical connection between the wiring 3 and the wiring 8 is realized. Moreover, since the silica film 5 is not etched back,
It has a wiring structure in which the manufacturing process is shortened and the flatness of the interlayer insulating film is very excellent.

FIG. 2 is a sectional view of a semiconductor chip showing a second embodiment of the present invention, and FIG. 3 is a sectional view of a semiconductor chip showing a third embodiment of the present invention.

As shown in FIGS. 2 and 3, the first embodiment is different from the first embodiment except that the silicon oxide film 6 provided on the upper surface of the silica film 5 or the silicon oxide film 4 provided on the lower surface is omitted.
The structure is similar to that of the above embodiment, and there is an advantage that the process is simplified. The lower wiring 3 may have a laminated structure with another metal film having a gold film on the upper surface.

[0023]

As described above, according to the present invention, the combination of the lower layer wiring having the gold film on at least the upper surface thereof and the silica film formed by the coating method is excellent in flatness and stable with the upper layer wiring. The effect is that a multi-layer wiring having electrical connection can be realized.

[Brief description of drawings]

FIG. 1 is a cross-sectional view of a semiconductor chip showing the order of steps for explaining a manufacturing method according to a first embodiment of the present invention.

FIG. 2 is a sectional view of a semiconductor chip showing a second embodiment of the present invention.

FIG. 3 is a sectional view of a semiconductor chip showing a third embodiment of the present invention.

FIG. 4 is a cross-sectional view of a semiconductor chip showing the order of steps for explaining a conventional method for manufacturing a semiconductor device.

[Explanation of symbols]

 1 Semiconductor Substrate 2 Insulating Film 3,8 Wiring 4,6 Silicon Oxide Film 5 Silica Film 7 Via Hole 9,10 Aluminum Wiring

Claims (1)

[Claims] 1. An interlayer having a laminated structure of a lower layer wiring having a gold film on at least an upper surface provided on a semiconductor substrate and an inorganic insulating film provided on a surface including the wiring and a silica film formed by a coating method. An insulating film, a via hole provided by opening the interlayer insulating film and exposing the silica film on a side surface, and an upper wiring provided in connection with a lower wiring of the via hole. Characteristic semiconductor device.