JPH0590847A - Power amplifier - Google Patents

Abstract

PURPOSE:To obtain a highly efficient power amplifier by varying two positive/ negative power supply voltages so that the voltage between the emitter and collector of the output stage transistor in a complimentary symmetric circuit can hold a predetermined voltage value regardless of an input signal condition. CONSTITUTION:Terminals 3 and 4 of variable voltage power supply VVC are supplied with positive and negative voltages, respectively. Both the switching power supply circuit (at the positive power supply side) of power supply VVC and the switching power supply circuit (at the negative power supply side) act the same operation. That is, output voltages that have the same absolute values as those of the voltages set at the non-reversible input terminals of their respective comparators 21 and 34 and that have predetermined polarities are output to output terminals 5 and 7. Accordingly, the voltage difference between the collector and emitter of output stage transistor Q1 of the SEPP circuit and the voltage difference between the collector and emitter of output stage transistor Q2 of the SEPP are controlled by power supply VVC so as to be kept constant regardless of the variation in amplitude of a signal subject to amplification. With this, the power amplifier can highly efficiently carry out amplification operation.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION This invention relates to power amplifiers.

[0002]

2. Description of the Related Art Conventionally, power amplifiers having various configurations have been known. For example, as an output circuit in an audio device, a single ended push pull (SEP) is used.
P) has been widely used. And the above-mentioned SE
The efficiency of the PP circuit shows the same value as the efficiency of the class B PP circuit of 78.5%, but it is used in electronic devices for which power consumption is desired to be reduced, such as a magnetic tape recorder with a portable radio receiver. As a power amplifier, a power amplifier with higher efficiency has been desired. A pulse width modulation type power amplifier has been conventionally known as a highly efficient power amplifier. FIG. 5 is a block diagram showing a schematic configuration of the above-mentioned pulse width modulation type power amplifier. In FIG. 5, reference numeral 48 denotes an audio signal Sb to be amplified (in FIG. 6).
(see (b)), and 49 is a pulse width modulation circuit. In the pulse width modulation circuit 49, the carrier source 50
Carrier wave Sa supplied from {see (a) of FIG. 6}
Is pulse-width modulated by the above-mentioned audio signal Sb,
The pulse width modulated wave Sc {see (c) of FIG. 6} is output and supplied to the pulse amplifier 51.

The pulse width modulated wave Sc amplified by the pulse amplifier is used as an opening / closing control signal for the switching circuits 52 and 53, and the switching circuit 5 described above is used.
2, 53 are controlled to open and close so that the ON and OFF states are opposite to each other, and when the switching circuit 52 is in the ON state, the plus side of the power supply 56 → the switching circuit 52 in the ON state → low pass. Filter 54 → load (speaker) 55 → load 55 by the circuit on the negative side of power supply 56
When the switching circuit 53 is in the ON state, the positive side of the power source 57 → the load (speaker) 55 → the low-pass filter 54 → the switching circuit 53 in the ON state → the negative side of the power source 57. An electric current is caused to flow to the load 55 by the circuit. Then, the load 55 described above has a signal Sd having a waveform as shown in FIG. 6D, that is, the audio signal Sb to be amplified {in FIG.
The signal having the same waveform as in (b) is sent. In the above-mentioned pulse width modulation type power amplifier, since the semiconductor element of the output stage performs the switching operation to supply the power to the load, the power wasted by the semiconductor element of the output stage is extremely small. It can operate as a power amplifier with few and therefore high efficiency.

[0004]

However, in the above-mentioned pulse width modulation type power amplifier, the frequency of the carrier wave Sa must be several tens of times the maximum frequency value of the audio signal Sb to be a modulated wave, and a good output is obtained. Because no signal is obtained,
Also as the switching circuit, an expensive switching element is required so that good switching control can be performed by the switching control signal having the repetition frequency of the carrier wave Sa, which is set to the high frequency value described above. There is a problem that an unnecessary radiated electromagnetic field is generated by using the signal of the frequency value. Therefore, in the case of an electronic device in which the pulse width modulation type power amplifier has a functional portion for receiving a signal by a radiated electromagnetic field, such as a magnetic tape recorder with a radio receiver, the above As described above, there are drawbacks such as that it is necessary to perform strict electromagnetic shielding and electrostatic shielding so that an unnecessary radiated electromagnetic field generated from the power amplifier is not received by the wireless reception unit.

[0005]

According to the present invention, in a power amplifier in which at least an output stage is constructed as a complementary symmetrical circuit and operating power is supplied from two positive and negative power supplies, each transistor of the output stage is provided. Provided is a power amplifier including means for changing the voltage of two positive and negative power supplies so that the collector-emitter voltage is maintained at a predetermined voltage value regardless of the state of an input signal.

[0006]

The voltage of the two positive and negative power supplies is changed so that the collector-emitter voltage of each transistor in the output stage, which is configured as a complementary symmetric circuit, is maintained at a predetermined voltage value regardless of the state of the input signal. By doing so, the loss generated in each transistor of the output stage is extremely reduced, and a highly efficient power amplifier can be provided.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The specific contents of the power amplifier of the present invention will be described in detail below with reference to the accompanying drawings. 1 is a block diagram of an embodiment of the power amplifier of the present invention, FIG. 2 is a waveform diagram for explaining the operation of the power amplifier of the present invention, and FIG. 3 is for explaining the configuration principle and operation principle of a variable voltage power supply. 4 is a waveform diagram for explaining the operation of the variable voltage power supply shown in FIG. In FIG. 1, reference numeral 1 is an input terminal of a signal (for example, an acoustic signal) to be amplified, 2 is a voltage amplifier of the excitation stage, and the output signal from the voltage amplifier 2 of the excitation stage is the transistors Q1 and Q2. , Resistance R1
˜R5 and diodes D1 and D2 are applied as an input signal to the output stage of the SEPP circuit, and the output signal from the output stage is supplied to the load 47. The operating power of the output stage described above is supplied to the output stage from terminals 5 to 7 in the variable voltage power supply shown by the chain line frame VVC in FIG. To the variable voltage power supply VVC, a positive voltage is applied to the terminal 3 and a negative voltage is applied to the terminal 4. In the variable voltage power supply VCC described above, the collector-emitter voltage Vce of each of the transistors Q1 and Q2 in the output stage of the power amplifier is preset regardless of the change in the amplitude of the acoustic signal to be amplified. A power supply configured to be capable of supplying an operating voltage for maintaining a predetermined voltage value to the output stage of the power amplifier via the terminals 5 to 7 described above. It can be configured by modifying the switching power supply.

FIG. 3 is a block diagram of a switching power supply for explaining the configuration principle and operation principle of the variable voltage power supply VVC described above. In FIG. 3, the positive and negative power supplies shown in FIG. 1 are used. Only the basic components of the circuit configuration on the positive power source side, which is configured between the terminals 3 and 5 in the variable voltage power source VVC, are shown representatively. FIG. 4 is a waveform diagram for explaining the operation of the variable voltage power supply shown in FIG. In FIG. 3, Q is a P-channel switching power MOS FET (hereinafter sometimes referred to as P-channel FET Q),
The P-channel FET Q whose positive power supply input smoothed by the smoothing capacitor Cs is supplied to the source.
Is turned on when the voltage supplied from the comparator COMP to the gate is at a low level, and the positive power supply input power is supplied from the drain to the smoothing capacitor C via the return coil L as shown by the solid line arrow in the figure. And supply to
Further, when the voltage supplied from the comparator COMP to the gate is at a high level, the P-channel FET Q is turned off. When the P-channel FET Q is turned off, the magnetic energy accumulated in the return coil L when the P-channel FET Q is turned on is recovered as a current in the circuit, It flows through the free wheeling diode D as indicated by the dotted arrow.

Since the amount of electric power supplied to the load side by the ON / OFF operation of the P-channel FET Q described above increases in proportion to the period during which the P-channel FET Q is in the ON state, the amount of power supplied to the drain of the P-channel FET Q is The voltage value supplied to the load of the switching power supply in a state of being smoothed by the return coil L and the smoothing capacitor C provided between the load and the load is the period of the P channel FET Q in the ON state and the OFF state. It can be changed by changing the ratio with the period. And FE of P channel
The ratio of the on-state period and the off-state period of T Q is, for example, a variable voltage applied to the non-inverting input terminal of the comparator in which a triangular wave signal having a predetermined peak value is supplied to the inverting input terminal. By supplying a signal having a varying pulse width to the gate of the FET Q of the P channel, as illustrated in FIGS. Can be changed.

FIG. 4A shows a triangular wave signal having a predetermined peak value supplied to the inverting input terminal of the comparator and a variable voltage (+ Vx in the figure) applied to the non-inverting input terminal of the comparator. → 0 → −Vx), and FIG. 4 (b) shows that when the voltage supplied to the non-inverting input terminal of the comparator is −Vx, the P-channel FET Q from the output side of the comparator is shown. 4 shows the voltage waveform applied to the gate of FIG.
(C) shows a voltage waveform given to the gate of the FET Q of the P channel from the output side of the comparator when the voltage supplied to the non-inverting input terminal of the comparator is 0V. (D) is P from the output side of the comparator when the voltage supplied to the non-inverting input terminal of the comparator is + Vx.
It shows the voltage waveform applied to the gate of the FET Q of the channel.

A P-channel FET is connected to the non-inverting terminal of the comparator in FIG. 3 which operates as described above.
The positive voltage supplied to the load of the switching power supply in a state smoothed by the return coil L and the smoothing capacitor C provided between the drain of Q and the load is fed back via the feedback resistor Rb, and When a variable negative voltage for output voltage control is supplied from the set voltage input terminal to the non-inverting terminal of the comparator via the comparator input resistor Ra, the voltage value of the positive voltage supplied to the load is It changes according to the change in the voltage value of the variable negative voltage for controlling the output voltage. A specific example of the above point will be described as follows. That is, the feedback resistor Rb and the comparator input resistor R
The resistance value is the same as a, and the set voltage input terminal is -5
If a negative voltage of V is applied, and if the triangular wave voltage with a peak-to-peak value of 0.1 V (± 50 mV) is supplied to the inverting terminal of the comparator, the voltage value of the positive power supply input is +10 V. Taking the case of doing as an example,
First, when the power is turned on, the terminal voltage of the smoothing capacitor C provided between the drain of the P-channel FET Q and the load is 0 V, so the voltage supplied to the non-inverting input terminal of the comparator in this state is -2. It becomes 0.5V.

When the voltage supplied to the non-inverting input terminal of the comparator is -2.5 V as described above, the voltage of the non-inverting input terminal of the comparator is ± 50 mV of the triangular wave supplied to the inverting input terminal. Since it is sufficiently lower than the value, the output of the comparator is always in the low level state regardless of the change in the voltage value of the triangular wave voltage. So, the P-channel FET Q keeps on continuously,
The terminal voltage of the smoothing capacitor C gradually rises from 0V. The above-mentioned ON state of the FET Q of the P channel continues until the terminal voltage of the smoothing capacitor C reaches 4.9V, and when the terminal voltage of the smoothing capacitor C becomes 4.9V or more, the comparison result with the triangular wave voltage in the comparator The high-level voltage with the pulse width changing corresponding to is supplied from the comparator to the gate of the P-channel FET Q, and the P-channel FET
Since Q turns off when the high level voltage is supplied to the gate, when the terminal voltage of the smoothing capacitor C becomes 4.9 V or higher, the P-channel FET Q starts switching operation. Start. P mentioned above
In the switching operation of the FET Q of the channel, the ON period is long when the terminal voltage of the smoothing capacitor C is around 4.9 V, and the ON period becomes shorter as the voltage value rises (see FIG. 4). Is something
When the terminal voltage of the smoothing capacitor C is 5.1 V or more, the FET Q of the P channel remains off.

In the switching power supply circuit shown in FIG. 3, the voltage value of the positive power supply, which is supplied to the load as the output of the switching power supply by the switching operation of the P-channel FET Q as described above, is the set voltage input terminal. If the negative voltage set to is -5V, it is + 5V,
Further, the negative voltage set at the set voltage input terminal is, for example, 0
In the case of V, the voltage value of the positive power supply supplied to the load as the output of the switching power supply is 0V, and when the negative voltage set in the set voltage input terminal is, for example, -10V, the output of the switching power supply is The voltage value of the positive power supply supplied to the load as the output of the switching power supply is the same as the voltage value of the positive power supply supplied to the load as the voltage value of the negative voltage set to the set voltage input terminal. Positive voltage with the same absolute value.

Up to now, the positive and negative two shown in FIG.
P-channel switching power MO between terminal 3 and terminals 5 and 6 of variable voltage power supply VVC
FIG. 3 representatively shows only the basic components of the circuit configuration on the positive power source side including the S-FET 10.
The configuration principle and operation principle of the switching power supply circuit used for the variable voltage power supply VVC have been described with reference to FIG. 1, but the terminal 4 and the terminal 7 in the variable voltage power supply VVC shown in FIG. It is easy to understand that the circuit configuration and operation on the negative power source side including the N-channel switching power MOS FET 11 between 6 and 6 are similar to those of the positive power source side switching power source circuit described above. Since it is possible, a detailed description of the switching power supply circuit on the negative power supply side will be omitted.

Now, the terminal 3 and the terminal 5, in the variable voltage power supply VVC composed of two positive and negative power supplies shown in FIG.
P channel switching power MOS between 6 and
A switching power supply circuit on the positive power supply side including the FET 10, and a switching power supply on the negative power supply side including the N-channel switching power MOS FET 11 between the terminal 4 and the terminals 7 and 6. In the circuit, 8 and 9 are smoothing capacitors (corresponding to the smoothing capacitor Cs in FIG. 3), 14 and 15 are return coils (corresponding to the return coil L in FIG. 3) 12, 13 are return diodes (in FIG. 3). Reflux diode D), 16 and 17 are smoothing capacitors (corresponding to smoothing capacitor C in FIG. 3) 21,
34 is a comparator (corresponding to the comparator COMP in FIG. 3), 25 and 38 are feedback resistors (corresponding to the feedback resistor Rb in FIG. 3), 27 and 40 are comparator input resistors (corresponding to the comparator input resistor Ra in FIG. 3). ).

The emitter of the transistor Q1 at the output stage of the power amplifier in which the output terminal 5 on the positive power supply side of the variable voltage power supply VVC is connected to the collector is connected to the terminal 6 of the variable voltage power supply VVC via the resistor R1. Output terminal 7 on the negative power supply side of the variable voltage power supply VVC.
The emitter of the transistor Q2 at the output stage of the power amplifier, which is connected to the collector, is connected to the terminal 6 of the variable voltage power supply VVC via the resistor R2. An inverting amplifier IAp composed of an operational amplifier 28 and resistors 29 and 30 is provided between the terminal 6 and the non-inverting input terminal of the positive power supply side comparator 21.
And a comparator input resistor 27 are connected to a circuit including a series circuit, and an operational amplifier 41 and resistors 42 and 43 are provided between the terminal 6 and the non-inverting input terminal of the negative power supply side comparator 34. A circuit including a series circuit of an inverting amplifier IAm configured by and a comparator input resistor 40 is connected.

The comparator 2 is provided between the non-inverting input terminal of the comparator 21 on the positive power source side and the ground.
1, a clamp diode 26 is connected to prevent an excessive input from being supplied, and a feedback is provided between the non-inverting input terminal of the comparator 21 and the non-grounding side terminal of the smoothing capacitor 16. The resistor 25 and the level shift diodes 22 and 23 for setting the collector-emitter voltage in the output stage transistor Q1 of the power amplifier are connected in series, and the feedback resistor 25 and the level shift diode 23 described above are connected. A predetermined bias voltage is applied from the negative bias voltage source to the level shift diodes 22 and 23 through the resistor 24 at the connection point. Further, between the non-inverting input terminal of the comparator 34 on the negative power source side and the ground,
A clamp diode 39 for preventing an excessive input from being supplied to the comparator 34 is connected, and between the non-inverting input terminal of the comparator 34 and the non-grounded side terminal of the smoothing capacitor 17, The feedback resistor 38 and the level shift diodes 35 and 36 for setting the collector-emitter voltage of the transistor Q2 at the output stage of the power amplifier are connected in series, and the feedback resistor 38 and the level shift diode 36 described above are connected. A predetermined bias voltage is applied from a positive bias voltage source to the level shift diodes 35 and 36 via a resistor 37 at a connection point between the and.

The inverting input terminal of the comparator 21 on the positive power supply side and the inverting input terminal of the comparator 34 on the negative power supply side are connected to the other end of the triangular wave reference voltage setting resistor 46 whose one end is grounded. In addition, a coupling capacitor 45 is connected between the input terminal 44 of the triangular wave reference voltage and the input terminal 44. In the embodiment shown in FIG. 1, the output side of the comparator 21 on the positive power source side and P
Channel switching power MOS FET10
A gate drive amplifier composed of transistors 18 and 19 and an output resistor 20 is connected between the gate of the comparator 3 and the gate of the negative power supply side comparator 3 described above.
4 output side and N channel switching power MO
A transistor 3 is provided between the gate of the S-FET11.
A gate drive amplifier composed of 1, 32 and an output resistor 33 is connected. That is, P-channel switching used as a switching element
The power MOS-FET 10 and the N-channel switching power MOS-FET 11 have a relatively large capacitance (several hundred PF) between their source and drain terminals.
Since a drive circuit having a large current capacity is required in order to increase the operation speed of ON → OFF and OFF → ON at the time of switching operation, the drive circuit having the large current capacity is required. In the example, the configuration is such that a gate drive amplifier is used, but an operational amplifier capable of obtaining an output sufficient to drive the gates of the P-channel switching power MOS FET 10 and the N-channel switching power MOS FET 11 Is used instead of the comparators 21 and 34, the gate drive amplifier described above need not be used.

In the power amplifier shown in FIG. 1 provided with the variable voltage power supply VVC having the above-mentioned structure, the signal (eg, acoustic signal) to be amplified supplied to the input terminal 1 is excited. After being amplified by the stage voltage amplifier 2, the final stage transistors Q1 and Q2 and resistors R1 to R
5. The output signal of the SEPP circuit, which is composed of the diodes D1 and D2, is supplied as an input signal to the load 47. The output signal of the SEPP circuit is supplied to the load 47. In the operation mode of the output stage, the difference voltage between the collector voltage and the emitter voltage in each of the final stage transistors Q1 and Q2 is targeted for amplification as illustrated in the waveform diagram of FIG. With the signal held constant regardless of the change in signal magnitude,
It is adapted to be controlled by the variable voltage power supply VVC. The curve E1 in FIG. 2 is the voltage value of the operating voltage supplied from the output terminal 5 on the positive power supply side of the variable voltage power supply VVC to the collector of the transistor Q1 in the output stage of the power amplifier, and the curve E2 in FIG. Is the voltage value of the operating voltage supplied from the output terminal 7 on the negative power supply side of the variable voltage power supply VVC to the collector of the transistor Q2 at the output stage of the power amplifier, and the curve Vp in the figure is the emitter of the transistors Q1 and Q2. It shows the output voltage of the power amplifier output from the. It should be noted that the resistance R1 connected to the emitter of the transistor Q1 in the output stage of the power amplifier and the resistance R2 connected to the emitter of the transistor Q2 in the output stage of the power amplifier do not reduce the output power from the amplifier. Since a resistor having a small resistance value is used, a large trouble does not occur even if the voltage drop amount due to the resistors R1 and R2 is not considered.

The flat part of the curve E1 in FIG. 2 showing the voltage value E1 of the operating voltage supplied from the variable voltage power supply VCC to the collector of the transistor Q1 and the collector of the transistor Q2 are variable. The flat portion in the curve E2 in FIG. 2 showing the voltage value E2 of the operating voltage supplied from the voltage power supply VCC corresponds to the minute portion of the collector current of each of the transistors Q1 and Q2 described above. The collector voltages of the respective transistors Q1 and Q2 are shown. The voltage of the difference between the curve E1 and the curve Vp in the positive voltage range shown in FIG. 2 is set by the level shift diodes 22 and 23 provided in the positive power supply of the variable voltage power supply VCC. The voltage corresponding to the value substantially corresponds to the difference between the curve E2 and the curve Vp in the negative voltage range shown in FIG. 2 is provided in the negative power supply of the variable voltage power supply VCC. It substantially corresponds to the voltage value set by the level shift diodes 35 and 36. The amount of voltage drop due to the resistor R1 connected to the emitter of the transistor Q1 and the resistor R2 connected to the emitter of the transistor Q2 is negligibly small compared to the voltage value set by the level shift diode.

The variable voltage power supply VVC shown in FIG. 1 is composed of an operational amplifier 28 and resistors 29 and 30 connected between the terminal 6 and the non-inverting input terminal of the positive power supply side comparator 21. Inverting amplifier I
Ap inverts and amplifies the output voltage Vp of the power amplifier output from the emitters of the transistors Q1 and Q2 at the final stage of the power amplifier, and sets it as the set voltage of the positive side power supply through the comparator input resistor 27 to the positive power supply side. The voltage is supplied to the non-inverting input terminal of the comparator 21, and the variable voltage power supply VV
Operational amplifier 4 connected between terminal 6 at C and the non-inverting input terminal at comparator 34 on the negative power supply side
1 and the resistors 42 and 43, the inverting amplifier IAm is the final stage transistor Q1 and Q2 of the power amplifier.
The output voltage Vp of the power amplifier output from the emitter of the inverter is inverted and amplified, and the inverted voltage is set as the setting voltage of the negative power source, and the negative voltage side comparator 34
Supply to the non-inverting input terminal at.

As described above, the comparator 21 on the positive power source side
To the non-inverting input terminal of the P-channel FET 10 via the feedback resistors 25 and the level shifting diodes 22 and 23 for setting the collector-emitter voltage in the transistor Q1 of the output stage of the power amplifier. Smoothing capacitor 1 provided between
6 is supplied, and the inverting input terminal of the comparator 21 is supplied with the reference triangular wave voltage from the triangular wave voltage input terminal 44 through the coupling capacitor 45. In the switching power supply circuit on the positive power supply side, a gate drive amplifier, a P-channel switching power MOS FET 10, a freewheel coil 14 and a freewheeling diode 12, a smoothing capacitor 16, and a reference triangular wave voltage are supplied to the inverting input terminal on the positive power supply side. Comparator 21, power amplifier output stage,
An inverting amplifier IAp, a level shift diode 22,
By the automatic voltage control operation by the circuit such as 23 and the feedback resistor 25, the positive voltage of the absolute value corresponding to the voltage value preset by the level shifting diodes 22 and 23 is always applied to the terminal 5 of the variable voltage power supply VVC. , 6
An output signal with a pulse width that can be generated between them is output from the comparator 21, which is the transistor 1
It is adapted to be applied to the gate of the P-channel switching power MOS FET 10 via a gate drive amplifier composed of 8 and 19 and an output resistor 20.

The non-inverting input terminal of the negative power supply side comparator 34 has a transistor Q at the output stage of the power amplifier.
Level-shifting diodes 35 and 36 for setting collector-emitter voltage in 2 and feedback resistor 3
8 is supplied to the terminal voltage of the smoothing capacitor 17 provided between the drain of the N-channel FET 11 and the terminal 7, and the comparator 34
Since the reference triangular wave voltage is supplied to the inverting input terminal of the triangular wave voltage from the input terminal 44 of the triangular wave voltage via the coupling capacitor 45, in the switching power supply circuit on the negative power supply side of the variable voltage power supply VVC, the gate drive amplifier and the N channel are connected. Switching power MOS-FET 11, free wheel coil 15, free wheel diode 13, smoothing capacitor 17, negative comparator side comparator 34 whose reference triangular wave voltage is supplied to the inverting input terminal, output stage of power amplifier, inverting amplifier IAm, level By the automatic voltage control operation by the circuits such as the shift diodes 35 and 36 and the feedback resistor 38, the level shift diodes 35 and 3 described above.
The comparator 34 outputs an output signal having a pulse width that allows a negative voltage having an absolute value corresponding to the voltage value preset by 6 to be constantly generated between the terminals 7 and 6 of the variable voltage power supply VVC. Is an N-channel switching power MOS via a gate drive amplifier composed of transistors 31 and 32 and an output resistor 33.
-It is designed to be applied to the gate of FET 11.

That is, the switching power supply circuit on the positive power supply side and the switching power supply circuit on the negative power supply side in the variable voltage power supply VVC shown in FIG. 1 are the same as those already described with reference to FIG. By performing the operation, an output voltage having a predetermined polarity with the same absolute value as the absolute value of the voltage value set on the non-inverting input terminal side of each comparator 21, 34 is output to the output terminals 5 and 7. Therefore, the SE in the power amplifier shown in FIG. 1 including the variable voltage power supply VVC having the above-described configuration is
The operation mode of the output stage of the PP circuit is such that the difference voltage between the collector voltage and the emitter voltage in each of the final stage transistors Q1 and Q2 is targeted for amplification as illustrated in the waveform diagram of FIG. It is controlled by the variable voltage power supply VVC while being kept constant regardless of the change in the magnitude of the signal being generated, whereby the power amplifier can perform an amplifying operation with high efficiency. In the case of a power amplifier used in a stereophonic sound signal reproducing apparatus, a common variable voltage controlled by the larger signal voltage in the power amplifier for the left channel signal and the power amplifier for the right channel. A power supply can be used. That is, since the large-amplitude component in the stereophonic audio signal is usually a low-frequency band signal and a monaural signal, even if the common variable voltage power supply is used for the power amplifiers of the left and right channels as described above, it causes a big trouble. Never.

[0025]

As is clear from the above description, the power amplifier of the present invention is constructed as a complementary symmetrical circuit, and the collector-emitter voltage of each transistor in the output stage is independent of the state of the input signal. By changing the voltage of the positive and negative 2 power supplies so that the voltage is maintained at a predetermined voltage value, the loss generated in each transistor of the output stage is extremely reduced, and the heat generation amount of the power amplifier is greatly reduced. The triangular wave voltage used in the variable voltage power supply of the power amplifier of the present invention is the carrier wave used in the conventional pulse width modulation type power amplifier. Since a triangular wave voltage with a repetition frequency much lower than the repetition frequency (for example, a triangular wave voltage with a repetition frequency of 100 KH or less) is used, There is little unnecessary radiation from the power supply, so even if simple electrostatic or electromagnetic shielding is applied to the variable voltage power supply part, it will not interfere with the component part that has the function of receiving radiated electromagnetic fields. The advantages such as being able to be obtained are obtained.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of a power amplifier of the present invention.

FIG. 2 is a waveform diagram for explaining the operation of the power amplifier of the present invention.

FIG. 3 is a block diagram for explaining a configuration principle and an operation principle of a variable voltage power supply.

FIG. 4 is a waveform diagram for explaining the operation of the variable voltage power supply shown in FIG.

FIG. 5 is a block diagram showing a schematic configuration of a pulse width modulation type power amplifier.

FIG. 6 is a waveform diagram for explaining the operation of the pulse width modulation type power amplifier.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Input terminal of the signal (for example, acoustic signal) to be amplified, 2 ... Excitation stage voltage amplifier, 5-7 ... Terminal, 11
... N-channel switching power MOS / FE
T, 22, 23, 35, 36 ... Level shift diode for setting collector-emitter voltage in transistors Q1 and Q2 of output stage of power amplifier, 47 ... Load, V
VC ... Variable voltage power supply, Q1, Q2 ... Transistor, R1 ...
R5 ... Resistor, D1, D2 ... Diode, Q, 10 ... P channel switching power MOS FET, Cs,
C, 8, 9 ... Smoothing capacitors, D, 12, 13 ... Return capacitors, IAp, IAm ... Inverting amplifier, COMP, 2
1, 34 ... Comparator, L, 14, 15 ... Return coil, Rb, 25, 38 ... Feedback resistance, Ra, 2
7, 40 ... Comparator input resistance,

Claims (1)

[Claims] 1. A power amplifier in which at least an output stage is configured as a complementary symmetric circuit and operating power is supplied from two positive and negative power supplies, the collector-emitter voltage of each transistor in the output stage is input. A power amplifier provided with means for changing the voltage of the positive and negative two power supplies so that the voltage is held at a predetermined voltage value irrespective of the state of the signal.