JPH0590895A - Time constant automatic adjusting circuit - Google Patents

Abstract

(57) [Summary] [Purpose] The adjustment of the time constant and temperature drift were made difficult. [Structure] The current path switch 11 is arranged for the output currents I01 and I02 of the Gm amplifier 21, and the Gm amplifier 21 is operated by DC. As a result, it is possible to eliminate the delay time when the current of the Gm amplifier 21 is turned on and off, and to eliminate the occurrence of the error current. The single-ended circuit 101 driven based on the current path switch 11 includes a capacitor C
Charge to 7 without error current.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an automatic time constant adjusting circuit for controlling a bias current of a filter circuit.

[0002]

2. Description of the Related Art FIG. 4 shows a conventional time constant adjusting circuit. The reference voltage generation circuit 1 outputs a reference voltage Vref and a certain difference voltage ΔVi from the generated voltage. Clock signal C from a reference signal generating circuit (not shown)
K1 is input, and the output terminal of one side of the current path switch 5 for switching the current path of the current source 6 is subjected to voltage-current conversion (G
m) Connect to amplifier 2. Gm amplifier 2 has a difference voltage ΔV
Input i and perform voltage-current conversion. Converted current output I
01 and I02 are input to the single-ended circuit 10, the current is single-ended, and is passed through the integrating capacitor 7. The other output terminal of the current path switch 5 is connected to the capacitor 7. The peak hold circuit 3 detects the peak of the voltage waveform of the capacitor 7, and uses the hold capacitor 8 to hold the peak voltage Vp until the next peak. Peak voltage Vp
And the reference voltage Vref are input to the comparison circuit 4. The comparison result is stabilized by the smoothing capacitor 9, and the current source 6 is controlled by the comparison output.

The operation of FIG. 4 will be described in more detail with reference to the waveform chart of FIG. The clock signal CK1 is shown in FIG.
Assume that the signal is as shown in (a), and the clamp circuit (not shown) operates when the voltage of the capacitor 7 decreases. Since the difference voltage ΔVi voltage is applied, G
The output current of the m-amplifier 2 has different values. In FIG. 4, the relationship between the current outputs I01 and I02 of the Gm amplifier 2 and the bias current IB of the current source 6 is I01> I02 (I01 + I02 = I
B) is assumed. When a current is passed through the Gm amplifier 2 when the pulse of the clock signal CK1 is Hi, the output current of the Gm amplifier 2 appears only in a half cycle of the clock signal CK1.
When this current is passed through the single end circuit 10, the difference component (I01-I02) is output. Therefore, the capacitor 7 is charged during this period and rises as shown in FIG. When the pulse of the clock signal CK1 is Lo, the output of the current path switch 5 is on the capacitor side. At this time, there is no current output from the single end circuit 10, and all the bias current IB flows into the capacitor 7 and is discharged. At this time, the voltage waveform of the capacitor 7 sharply falls as shown in FIG. 5B, and when it becomes sufficiently low, the clamp circuit operates and becomes constant at a predetermined voltage.

The peak hold circuit 3 holds the peak voltage Vp of this waveform (b). The comparison circuit 4 compares the peak voltage Vp with the reference voltage Vref, applies negative feedback to the current source 6, and controls so that the peak voltage Vp and the reference voltage Vref become equal.

Japanese Patent Application No. 2-33 filed previously by the same applicant
As described in No. 5635, if the current source is controlled by such a method, the time constant indicated by the product of the resistance and the capacitor built in the IC or the ratio of the current and the capacitor can be kept constant. ..

A specific example of the Gm amplifier 2 is shown in FIG.
The one using a differential amplifier as shown in is typical.
Even if the bias current source 6 is turned on, this differential amplifier takes several nS to several tens nS before the output current appears. In addition, since Gm increases from a minute level at the rising of the current-on, it is not constant. Therefore,
The rising waveform of FIG. 5 (b) becomes a little at the moment of turning on, as indicated by the dotted line. This is the clock signal CK
This indicates that the voltage that should be reached in the half cycle period of 1 is not reached, and the automatically adjusted time constant deviates. Moreover, since the period fluctuates with respect to the temperature, the adjusted current causes temperature drift.

[0007]

In the above-mentioned conventional time constant automatic adjustment circuit, it takes time for the output current to rise when the power of the Gm amplifier is turned on, and the automatically adjusted time constant deviates. Current drifts due to temperature.

An object of the present invention is to provide a time constant automatic adjustment circuit which is less likely to cause time constant adjustment deviation and temperature drift.

[0009]

According to the present invention, the current source switching means is applied to the output current of the Gm amplifier and the discharging operation of the capacitor is performed by the single end circuit.

[0010]

By doing so, the Gm amplifier does not operate by switching, and the output current becomes DC. Further, since the current always flows through a part of the single-ended circuit, the transient response at the time of the switching operation is smooth and fast, so that the deviation of the adjustment current and the temperature drift, which have been conventionally generated, can be greatly improved.

[0011]

Embodiments of the present invention will be described in detail below with reference to the drawings. FIG. 1 shows an embodiment of the present invention, and the same parts as in FIG.

The reference voltage generating circuit 1 has a reference voltage V
It outputs ref and a certain difference voltage ΔVi. The Gm amplifier 21 inputs the difference voltage ΔVi and outputs 2 based on the bias current IB.
Create one output current I01 and I02 (I01> I0
2). These current outputs I01 and I02 are connected to the current path switch 1
1 to switch the path at the timing of the clock signal CK1 and output it to the single end circuit 101. The output current of the single end circuit 101 is passed through the capacitor 7 to charge it. Capacitor voltage peak hold circuit 3
To hold the peak voltage Vp of the charging waveform. The peak voltage Vp and the reference voltage Vref are input to the comparison circuit 4, and the comparison result is smoothed by the smoothing capacitor 9 to control the control current source 6.

Since the current path switch 11 is arranged for the output current of the Gm amplifier 21, the Gm amplifier 21
Operates on DC. Therefore, the conventional ON
There is no delay time due to / OFF and no error current is generated here.

FIG. 2 shows a specific example of the current path switch 11 and the single end circuit 10. The current output I01 of the Gm amplifier 21 is supplied to the common emitter of the transistors Q5 and Q6, and the collector of the transistor Q5 is connected to the transistors Q7 and Q8 and the first current mirror circuit CM1 of the resistors R1 and R2. The collector of the transistor Q6, together with the current output I02, together with the transistors Q9, Q10
And a second current mirror circuit CM of resistors R3 and R4
Connect to 2. The output current of the second current mirror circuit CM2 is input to the third current mirror circuit CM3 including the transistors Q11 and Q12 and the resistors R5 and R6, and the collector of the transistor Q12 and the collector of Q8 are connected to form a single-ended current. To create.

The current path switch 11 is a transistor Q5.
, Q6, and the switching operation is clock signal CK2
And the clock signal CK3 having the opposite polarity. Transistors Q5 and Q6 are clock signals CK input to the base.
2 Since it operates as a differential amplifier by CK3, the switching time is equal when the transistor Q5 is on and when the transistor Q6 is on, and the delay time is constant.

First, in the case of charging operation, the clock signal CK
2 turns on the transistor Q5. The current output I01 is led to the output terminal Iout through the transistor Q5 and the first current mirror circuit CM1. The output current I02 passes through the second and third current mirror circuits CM2 and CM3 and is output to the output terminal Iout, and as a result, the charging current (I01> I02) of I01-I02 is output.

In the discharging operation, the transistor Q6 is turned on. Since the current output I01 flows through the transistor Q6 to the second and third current mirror circuits CM2 and CM3, all the bias current IB is output to the output terminal Iout.
Output to. At this time, the discharge current becomes the bias current IB as in the conventional case.

As described above, since the predetermined current always flows through the second and third current mirror circuits CM 2 and CM 3, the follow-up is quick even when the current level is changed by switching. Since the time to respond to a change in current is shorter than that in the case where the conventional cutoff is performed, the time to generate an error is short, so that the transient response factor that causes an adjustment deviation or temperature drift can be drastically reduced.

Although the above description has been made with respect to the case of operating at the timing of FIG. 5, the automatic adjusting circuit which operates at the timing as shown in FIG. 3 of Japanese Patent Application No. 2-335635 filed by the applicant earlier. In addition, the same effect as the present invention can be realized by adding the current path switch 11 for the current output I02 and the means for bypassing the current to the power outputs for the current outputs I01 and I02.

[0020]

As described above, according to the time constant automatic adjustment circuit of the present invention, the time constant adjustment deviation and the temperature drift can be suppressed.

[Brief description of drawings]

FIG. 1 is a system diagram showing an embodiment of the present invention.

FIG. 2 is a circuit diagram showing a specific example of a main part of FIG.

FIG. 3 is another charging / discharging waveform diagram handled in FIG.

FIG. 4 is a system diagram showing a conventional time constant automatic adjustment circuit.

FIG. 5 is a charge / discharge waveform chart of FIG.

FIG. 6 is a circuit diagram showing an example of the Gm amplifier shown in FIGS. 1 and 5.

[Explanation of symbols]

 Reference voltage generation circuit 3 Peak hold circuit 4 Comparison circuit 6 Current source 7 Capacitor 21 Gm amplifier 11 Current path switch 101 Single circuit End circuit

Claims (2)

[Claims] 1. A charging / discharging waveform generating circuit for generating a charging / discharging waveform using a timing pulse serving as a time reference, a capacitor for charging / discharging based on the charging / discharging waveform of the charging / discharging waveform generating circuit, Detects the amplitude of the charge / discharge waveform of the discharge waveform generation circuit,
A time constant automatic adjusting circuit, comprising: a control circuit for controlling the amplitude of the charge / discharge waveform by comparing the detected amplitude with a reference voltage. 2. The time constant automatic adjustment circuit according to claim 1, wherein the charge / discharge waveform generation circuit comprises a voltage-current conversion amplifier and a switch means provided on the output side for switching a current path.