JPH0591274A - Image forming device - Google Patents

Abstract

(57) [Summary] (Correction) [Purpose] After a density pattern is roughly generated by the density pattern generation table, fine pulse width modulation is performed using a multi-phase clock created by delaying High-resolution, high-gradation halftone images can be obtained without using an expensive high-speed device such as a clock crystal oscillator. [Structure] The upper 4 bits of multi-valued image data sent from a printer controller are input to a density pattern generation table 4. Table 4 shows 2 input data of 1 pixel.
With × 2 pixels, one pixel is further divided into four and output as a pattern signal of 16 regions. Each of the 16 areas is further divided into 8 areas by the pulse width modulation circuit 100. A clock from the multi-phase clock generation circuit 200 is used to divide the eight regions. With this configuration, the gradation of one pixel input at 300 dpi can be expressed by 16 × 8 = 128 levels.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus for gradation processing of input image data.

[0002]

2. Description of the Related Art FIG. 16 shows an overall view of a conventional printer having a gradation processing function for multivalued image data. Printer 32
The printer controller 310 of 0 receives image data (including a photographic image and a character image) output from the host computer 330 which is an external device, and for the character image, a predetermined bit map signal (3F [H] for black). , White is converted to 00 [H]), and a photographic image is converted into a code signal indicating the density (white is 00 [H], the numerical value is increased as the density is increased, and 3F [H] represents black). 6-bit image data is sent to the processing unit 300. Then, the semiconductor laser 340 blinks according to the output signal from the image processing unit 300.

FIG. 17 is a detailed block diagram of the image processing unit 300 of the printer for printing a halftone image. In FIG. 17, reference numeral 301 denotes a δγ correction table, which is composed of, for example, a ROM. 302 is a 2-bit main scanning counter,
Reference numeral 303 is a sub-scanning counter, and 304 is a ROM or R
6 is a density pattern generation table configured by AM. Reference numeral 305 represents the 8-bit data output from the density pattern generation table 304 as the image clock VCLK.
It is a parallel-to-serial converter that outputs a clock with a double frequency.

Next, the operation will be described. 600d in this example
The printer will be described as a pi printer. From the printer controller (not shown), 6-bit multivalued image data is sent in synchronization with the image clock VCLK sent for each dot at a density of 600 dpi. The multi-valued image data is .gamma.-corrected by the .gamma.-correction table 301, converted into 7-bit image data, and input to the addresses A0 to A6 of the density pattern generation table 304. On the other hand, the image clock VCLK is counted by the main scanning counter 302, and its 2-bit output is input to the addresses A7 and A8 of 304. Further, each time the semiconductor laser 340 scans once, the horizontal scanning signal BD sent from the printer engine is counted by the sub-scanning counter 303, and its 2-bit output is 30
Input into addresses A9 and A10 in the table of No. 4. Thirty
When the above-mentioned addresses are input to the density pattern generation table of No. 4, 8-bit data D0 to D7 preloaded at the addresses are output, which are sequentially output from the MSB by the parallel-serial converter 305 to the image clock VCLK of 8 bits. It starts with the clock VCLK × 8 having the double frequency. As a result, one dot of 600 dpi forms 4 dots in the main scanning direction, and 4 dots in the sub scanning direction, a total of 16 dots form a minimum unit (pixel) representing the density.
Further, since one dot of 600 dpi is divided into eight, one pixel has 128 sections. In other words, 12 of 1 pixel
The density is expressed by how many black areas are filled in the eight areas (see FIG. 18).

FIG. 19 shows an example of the density pattern. Figure 1
Reference numeral 9 represents a density pattern when the multi-valued image data is 20 (010010).

[0006]

[Problems to be Solved by the Invention]
One dot of 00 dpi is grouped into 16 dots, and one dot is further divided into 8 to obtain 150d.
128 gradations were possible with pi. (Actually, the gradation is 128 or less due to the γ characteristic of the printer.) Therefore, the data input by the printer control 310 from the host computer 330 in FIG. 16 is premised on the data of 150 dpi.

However, at 128 gradations of 150 dpi, halftone images could not be sufficiently reproduced because the pixels were coarse at 150 dpi. Especially, the outline of the character is not sharp. Therefore, in order to input an image of 300 dpi from a host computer and to express 128 gradations with an engine of 600 dpi, it is necessary to express data of 1 pixel with 4 dots of 600 dpi, and further divide the 1 dot into 32.
The clock input to the parallel-serial converter 305 of FIG. 17 becomes a high frequency clock. For example, 600d
Since the image clock is 6.25 MHZ in a machine with 8 pi / min, the clock of the parallel-serial converter is 6.2.
5 × 32 = 200 MHZ. Therefore, there is a drawback that it cannot be realized without using an expensive crystal oscillator or an expensive ECL device.

The present invention eliminates the above-mentioned drawbacks of the prior art, and provides an image processing apparatus capable of obtaining a halftone image of high resolution and high gradation without using an expensive high speed device such as a high frequency clock crystal oscillator. Is provided.

[0009]

In an image forming apparatus for inputting a multi-valued image signal and performing halftone processing, a multi-phase clock signal generation means for generating clock signals of a plurality of phases from a basic clock signal is provided. , A density pattern generating means for generating a density pattern based on the inputted multi-valued image signal, and a density pattern signal outputted from the density pattern generating means are further finely pulsed by using a clock signal from the multi-phase clock signal generating means. A pulse width modulation means for width modulation, and after the density pattern is roughly generated by the density pattern generation means, fine pulse width modulation is performed to improve the resolution without lowering the gradation number of one pixel. You can The pulse width modulation is performed by delaying the clock without using a high frequency clock to generate clocks with a plurality of phases and using the multiphase clocks.

[0010]

1 is a block diagram showing a first embodiment of an image processing apparatus of the present invention. FIG. 2 shows the time chart. In the figure, reference numeral 1 is a latch A, 2 is a γ correction table configured by a ROM or the like for correcting input / output characteristics, and 4 is an R correction table.
A density pattern generation table 5 composed of an OM or the like for generating a density pattern according to input data, 5 is a frequency divider A, 6
Is a frequency divider B, 7 is a sub-scanning counter, 8 is a parallel-serial conversion circuit A (hereinafter referred to as PS circuit A), 9 is a parallel-serial conversion circuit B (hereinafter referred to as PS circuit B), 1
Reference numeral 0 is a latch B, 100 is a pulse width modulation circuit, and 200 is a multi-phase clock generation circuit. In this embodiment, data of 300 dpi (dots per inch) is input from the host computer, and a laser beam printer of 600 dpi is used. The smallest unit for expressing density)
Further, a case will be described in which each dot is divided into 32, one pixel is divided into 128, and gradation reproduction is performed depending on how many of the 128 sections are irradiated with the laser. Figure 8
Shows a diagram when one pixel is divided into 128 sections. The area gradation of 128 partitions per pixel means that the printer has 12
Since up to 8 gradations can be expressed, this image processing circuit receives 7-bit, 300-dpi multivalued image data via the host computer and print controller.

The operation will be described below.

First, the image processing apparatus receives multi-valued image data and an image clock VCLK (6.25 MHZ) of 600 dpi from a printer controller (not shown) in the preceding stage. The multi-valued image data is sent in synchronization with the rising edge of the image clock VCLK, and then the same image data of 2 dots is sent. (See (1) and (2) in FIG. 2) Image clock VC
LK is frequency-divided by a frequency divider A5 by 2 and has a width of 2 dots in the main scanning direction, that is, 1/2 V having a cycle of 300 dpi in the main scanning direction.
Output CLK. Then, the multi-valued image data is latched with this 1/2 VCLK, and image data of 300 dpi unit is created in the main scanning direction. (See Fig. 2 (4) and (5))
Then, the multi-valued image data of 300 dpi unit is converted into the data whose gradation is corrected by the γ correction table 2, and the upper 4 bits are the addresses A0 to A of the density pattern generation table 4.
Input to 3. On the other hand, the 1-bit signal obtained by counting the horizontal synchronizing signal BD by the sub-scanning counter 7 is input to the address A4 of the table. As described above, the 9-bit data of the address designated by A0 to A4 is D0 to D in the table.
7, output from DM. DM is a modulation enable signal, and in the case of "High", pulse width modulation circuit described later performs pulse width modulation. (See (6), (8), and (9) in FIG. 2) Table addresses and data will be described later.
Among the 9-bit output signals of the density pattern generation table 4, 8 bits of D7 to D0 are P-S circuits A8 and P- of the subsequent stage.
The S circuit B9 sequentially outputs the MSBs. P-
The S circuits 8 and 9 operate to load and eject data in a toggle state in units of 300 dpi in the main scanning direction. Use the Load bar to load data and the E bar to load. (Fig. 2
(Refer to (10) to (15)) and the logical sum is made in the latter stage,
It becomes the image data VS. (See FIG. 2 (16)) As a result, the data of 300 dpi in the main scanning direction can be divided into eight. The pulse-width modulation circuit 10 outputs the signal divided into eight.
By 0, the phase is further shifted by 8 and a total of 64 divisions of pulse width modulation is performed. In the multi-phase clock generation circuit 200, a clock P0VCLK with a phase difference of control clock VCLK × 4
~ Make P7VCLK.

FIG. 3 shows an example of the pulse width modulation circuit. In the figure, the pulse width is the same as VS from V00 to V07 by hitting the D signal with the image signal VS and the eight phase-shifted clocks generated by the multiphase clock generation circuit 200. Are output by 5 nS each (Fig. 4 (11))
~ (18)). On the other hand, the 3-bit output signal of the latch B10 is logically ANDed with the modulation enable signal DM, and is input to the decoder 102 in synchronization with P0CLK in the latch 101. The decoder 102 outputs “High” if the input signal is 000B and “Low” otherwise, if the input signal is 111B, outputs 7 “High” otherwise “Low”, if the input signal is 011B. The output 3 operates as "High" and otherwise "Low". Then, the logical sum 103 is V _1X and “High” by the decoder.
h "is all but one signal output" Low ", and the logical sum of the first signal in the the V _1X V00~V07 is image signal VD0 taken. (time chart see FIG. FIG. 4 shows the case where the latch B output signal is 011B.) That is, with the same pulse width as VS represented by a pattern divided into 8 determined by the γ correction table and VS based on the lower 3 bits of the input data. The logical sum with the phase-shifted signal is output as VDO When the modulation enable signal DM is "Low", the decoder 10
The input signal of 2 is 000B, and pulse width modulation is not performed.

FIG. 5 shows an example of the multi-phase clock generation circuit. FIG. 6 is the time chart. Next, the operation will be described. The circuit performs a multi-phase clock selection operation before the printing operation. First, the set signal SET of FIG.
Selector selects the selection operation start signal start. And sh one-shot pulse
Input to the D flip-flop 202 as ot signal,
The O output synchronized with VCLK × 4 is input to a circuit in which 80 buffers are connected in series as a start signal. st
From the rising edge of the art signal, one cycle of VCLK × 4 (4
Q of 203 D flip-flop after a delay of 0 ns)
The stop signal, which is the bar output, falls. That is, each of the delay signals S0 to S80 changes from "Low" to "High" while sequentially delaying from S0 by the gate delay time.
When changing from “Low” to “High”, the Q output of the flip-flop connected to that point changes from “Low” to “High”. 40 ns from the rising edge of the start signal to the falling edge of the stop signal
During the period of, the Q output of the flip-flop connected to the buffer of the gate of the buffer 80 to which the start signal has advanced becomes “High”. (Refer to (1) to (20) in FIG. 6) As shown in FIG. 6, for example, if the start signal is "High" up to S75, A0 to A75 is "High" and A76 to A80 is "Low". ,
C75, which is the output of the exclusive OR in the latter stage, becomes "High", and the other C0 to C74 and C76 to C79 are "L".
ow ”. 79 line to 7 line encoder 20
5, B0 to B6 are coded into 7 bits of 1001100B and input to the control signal of the multiphase clock selection unit 204. When the coded control signals B0 to B6 are determined, the set signal SET is invalidated and VCLK ×
4 outputs from the selector. In the multi-phase clock selection section, eight signals are selected from the delay signals S0 to S80 by the control signals B0 to B6, and P0CLK to P7 are selected.
CLK. In FIG. 7, 8 selected from the control signals B0 to B6 and S0 to S80 in the multiphase clock selection unit 204
A logic diagram showing the relationship between the two signals P0CLK to P7CLK is shown. In the example of the time chart of FIG. 6, since the control signals BO to B6 are 1001100B, P0CL
K is SO, P1CLK is S10, P2CLK is S19,
P3CLK is S29, P4CLK is S38, P5CLK
Selects S48, P6CLK selects S57, and P7CLK selects S67. P0CLK to P7CLK are each about 5ns
The frequency clock (50 MHZ) is the same as VCLK × 4 whose phase is shifted from each other.

The multi-phase clock generation circuit 200 is preferably composed of a gate array. On the same chip,
The delay times of the buffers are almost the same. In this example, the gate delay of the buffer is 0.5 ns minimum and 1.0 maximum.
In the case of ns, 40 [ns] /0.5 [ns] = 80 gates are set so that the delay time can be 0.5 ns.

FIG. 9 shows an example of the address and data of the density pattern generation table (4 in FIG. 1). FIG. 10 shows the addresses A3 to A0 when the table of FIG. 9 is used, that is, the upper 4 bits of the .gamma. Correction table (2 in FIG. 1) and the state of 1 pixel (600 dpi 4 dots) at the time of outputting the density pattern generation table. Show.

FIG. 11 shows a pulse width modulation circuit (100 in FIG. 1) for the output signal of the density pattern generation table described above.
2 shows the lower 3 bits of the output of the γ correction table (2 in FIG. 1) and the state of the image signal VDO of 1 pixel (600 dpi 4 dots) when pulse width modulation is performed. This drawing is an example in the pattern of (A3, A2, A1, A0) = (0, 1, 1, 0) in FIG.

In this way, after converting one pixel into a pattern obtained from 16 sections in the density pattern table, the pulse width modulation circuit finely pulse-width modulates the signal of 16 patterns, and thereby the pulse width is divided into 8 stages. The density can be changed and the density of 16 × 8 = 128 gradations can be reproduced. In this embodiment, all circuits shown in FIG. 1 are composed of logic circuits, and the gate array is a one-chip IC.
Can fit in. Further, the outputs P0CLK to P7CLK of the multi-phase clock generation circuit are adjusted before each printing operation, so that they are not affected by the ambient environment such as temperature and humidity.
A stable intermediate image can always be output.

Further, in this embodiment, since the logical sum is used in the final stage of the pulse width modulation circuit, the pulse width modulation is the right side growth, but the logical product may be used for the left side growth.

Second Embodiment FIGS. 12, 13 and 14 show a second embodiment of the present invention. In this embodiment, the size of one pixel is changed by changing the contents of the γ correction table and the density pattern generation table in the first embodiment. The contents of the density pattern generation table are shown in FIG. And in FIG.
The pattern of one pixel after the output of the shift register of the subsequent stage is shown.

As is apparent from FIG. 13, the main scan 600d
Pi and the sub-scanning 300 dpi are substantially one pixel. Further, in this case, the number of gradations that can be expressed is 8 × 8 = 64 gradations.
In FIG. 13, the unused area is corrected so as not to be addressed by the γ correction table in the previous stage. FIG. 14 shows a pattern after output from the pulse width modulation circuit. Although the number of gradations is smaller than that in the first embodiment, the resolution is increased and a fine halftone image can be obtained. This example is suitable for graphic images and character images with a small number of gradations. The density pattern generation table shown in FIG. 12 and the density pattern generation table shown in FIG. 9 are stored in the density pattern generation table of FIG. 1, and are used for processing in response to a table switching command from each unit device (host). Is selected.
Accordingly, by selecting the table of FIG. 9 in the case of emphasizing the gradation and selecting the table of FIG. 12 in the case of emphasizing the resolution, it is possible to obtain a high-quality image according to the image quality.

Third Embodiment The third embodiment is a simplified version of the multi-phase clock generation circuit in the first embodiment. FIG. 15 shows an example of the multi-phase clock generation circuit. In the figure, a delay line with eight taps is used and buffered externally. The delay time between taps is 5 ns.

As described above, according to the embodiment of the present invention, a density pattern is first roughly generated by a density pattern generation table, and then a fine phase width modulation is used by using a multiphase clock generated by delaying. By doing so, it becomes possible to obtain an intermediate image with high resolution and high gradation without using an expensive high-speed device such as a high-frequency clock crystal oscillator.

Further, the rough density pattern is generated by using the clock of the crystal without depending on the environmental change, and only the fine pulse width modulation is made dependent on the delay, so that accurate input image data can be obtained. Gradation processing can be performed.

[0025]

As described above, according to the present invention, it is possible to obtain a high resolution, high gradation halftone image without using an expensive high speed device such as a high frequency clock crystal oscillator.

[Brief description of drawings]

FIG. 1 is a block diagram showing details of an image forming apparatus that is an embodiment of the present invention.

FIG. 2 is a time chart diagram showing the operation of FIG.

FIG. 3 is a diagram showing details of a pulse width modulation circuit.

FIG. 4 is a time chart diagram of a pulse width modulation circuit.

FIG. 5 is a diagram showing details of a multiphase clock generation circuit.

FIG. 6 is a time chart diagram of a multi-phase clock generation circuit.

FIG. 7 is a logic diagram of a multiphase clock selection unit.

FIG. 8 is a diagram showing 600 × 2 × 2 dots in the present embodiment.

FIG. 9 is a diagram showing an example of a density pattern generation table.

FIG. 10 is a diagram showing an output example from a density pattern generation table.

FIG. 11 is a diagram showing an output example from a pulse width modulation circuit.

FIG. 12 is a diagram showing another example of a density pattern generation table.

13 is a diagram showing an output example of the density pattern generation table shown in FIG.

14 is a diagram showing an example of pulse width modulation of the pattern of FIG.

FIG. 15 is a diagram showing another embodiment of the multiphase clock generation circuit.

FIG. 16 is a diagram showing a relationship between a host computer and a printer.

FIG. 17 is a diagram showing a conventional density pattern method.

FIG. 18 is a diagram showing 4 × 4 dots at 600 dpi.

FIG. 19 is a diagram showing an example of a density pattern.

[Explanation of symbols]

 1, 10 Latch 2 γ correction table 4 Density pattern generation table 5, 6 Frequency divider 7 Sub-scanning counter 8, 9 Parallel-serial conversion circuit 100 Pulse width modulation circuit 200 Multi-phase clock generation circuit

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Jun Kashihara 3-30-2 Shimomaruko, Ota-ku, Tokyo Canon Inc. (72) Inventor Tetsuo Saito 3-30-2 Shimomaruko, Ota-ku, Tokyo Canon (72) Inventor Manabu Takebayashi 3-30-2 Shimomaruko, Ota-ku, Tokyo Canon Inc. (72) Toshihiko Sato, 3-30-2 Shimomaruko, Ota-ku, Tokyo Canon Inc.

Claims (6)

[Claims] 1. An image forming apparatus for inputting a multi-valued image signal to perform halftone processing, and a multi-phase clock signal generating means for generating clock signals of a plurality of phases from a basic clock signal, and an input multi-valued image. Density pattern generating means for generating a density pattern based on the signal, and pulse width modulation for further finely pulse-width modulating the density pattern signal output from the density pattern generating means by using the clock signal from the multi-phase clock signal generating means. An image forming apparatus having means. 2. The pulse width modulation means is a logical sum of one clock signal of a plurality of clock signals output from the multi-phase clock signal generation means and a density pattern signal from the density pattern generation means. The image forming apparatus according to claim 1, wherein pulse width modulation is performed based on a logical product. 3. The multi-phase clock signal generating means delays a basic clock signal through a plurality of gates to generate clock signals of a plurality of phases, and a delay for detecting a gate delay time of the delay circuit group. 2. The image forming apparatus according to claim 1, wherein the image forming apparatus comprises a selection circuit that selects a predetermined number of clock signals from the plurality of phase clock signals based on the detection results of the time detection circuit and the delay time detection circuit. 4. The image forming apparatus according to claim 1, wherein the multi-phase clock signal generating means uses a delay line. 5. The density pattern generating means has a plurality of density patterns or a density pattern of a plurality of lines, and selects a density pattern to be generated by a command from an external device. 1. The image forming apparatus of 1. 6. The gradation is expressed as one pixel, which is a combination of 4 dots of 600 dots / inch in the main scanning direction and 2 dots in the sub scanning direction. 1. The image forming apparatus of 1.