JPH11275355A - Image forming method and apparatus - Google Patents

Abstract

(57) [Summary] A high quality image is formed based on high frequency image information. Kind Code: A1 A plurality of first delay clocks having different delay times are generated in synchronization with a reference clock obtained by dividing a pixel clock, and one pixel time is required to divide one pixel time from among them. The number of first delay clocks 206 are selected, and first pulses 207 having a time width corresponding to the delay time of the selected first delay clocks are generated. A plurality of different second delayed clocks 226 are generated, and the required number of second delayed clocks 23 for dividing one pixel time from among them are generated.
0, a second pulse 232 having a time width corresponding to the selected delay time of the second delay clock is generated, and the first or second pulse is converted to a binary image based on the pattern 203 of the image information. Output as information 233.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image forming method and apparatus capable of forming a halftone image by changing the size of recording pixels by pulse width modulation based on input multi-valued image information. More particularly, the present invention relates to a method and apparatus for forming an inclined edge of an image into a smooth shape.

[0002]

2. Description of the Related Art There are an analog generation method and a digital generation method as a method for generating a signal having a multi-step pulse width. The analog generation method is a method of comparing a triangular wave generated in synchronization with image information with a D / A conversion output of the image information, as described in Japanese Patent Application Laid-Open No. 62-39972. The digital generation method is a method in which a clock signal faster than the pulse width to be generated is input, and the clock signal is frequency-divided by a counter or the like.

[0003] These prior arts have low frequencies (approximately 2
(0 MHz or less) It can be applied to processing of image information, but cannot be applied to processing of image information having a high frequency.

Therefore, an image forming method and apparatus which can be applied to high frequency image information have been proposed.

In this image forming method and apparatus, in an image forming method for converting binary image information into binary image information modulated in a time axis direction, delay times differ stepwise in synchronization with a pixel clock. Generate multiple delayed clocks,
From among them, the number of delay clocks necessary to divide one pixel time is selected, and a pulse on a time axis corresponding to the delay time of the selected delay clock is generated, and the input gradation of the multi-valued image information is generated. It is characterized in that a corresponding pulse of a corresponding time width is output as binary image information.

The required number of delayed clocks are measured from the plurality of generated delayed clocks that fall within the one pixel time, and are selected stepwise. In the case where the delay time difference between the stepwise delayed clocks generated thereby is not constant, the accuracy of dividing the pixel time can be improved, and the high-speed pixel clock can be followed.

Further, when the pixel time changes due to a change in the resolution of the binary image information, the number of delay clocks to be selected is increased or decreased according to the pixel time. This makes it possible to respond to changes in the resolution specifications of printers and displays.

[0008] An image forming apparatus for realizing these methods includes:
A delay clock generating means for generating a plurality of delay clocks having different delay times stepwise from a reference clock synchronized with the pixel clock;
Delay time measuring means for measuring a delay clock corresponding to a pixel time; delay clock selection means for selecting a required number of delay clocks within the delay time of the measured delay clock; A pulse generating means for generating a pulse having a stepwise different pulse width by a logical operation of each of the reference clocks and a binary image by selecting a pulse having a pulse width corresponding to the input gradation of the multi-valued image information And a binary image information converting means for outputting information.

According to such an image forming method and apparatus, a large number of generated delay clocks having a short delay time are measured, and a delay clock necessary for dividing a pixel time corresponding to a resolution is selected with high accuracy. Therefore, a multi-step pulse having a short pulse width can be easily generated, and can be easily applied to high-frequency multi-value image information processing.

Hereinafter, the image forming method and apparatus will be described in detail with reference to FIGS.

The gradation expression of the displayed and recorded images includes a method of changing the coloring density of the pixels constituting the image, a method of changing the coloring area, and a method of changing both of them. Whichever method is adopted, binary image information pulse-width-modulated in the time axis direction is created in accordance with multi-value image information (density information of each image), and pixels are displayed or recorded by the binary image information. .

The pulse width modulation method and apparatus and the image forming method and apparatus are such a method for generating binary image information and the apparatus.

FIG. 21 is a block diagram showing an example of a pulse width modulation recording signal generator in the image forming apparatus. This pulse width modulation recording signal generating apparatus includes a delay clock generating means 1, a delay time measuring means 2, a delay clock selecting means 3, a pulse generating means 4, a pulse selecting means 5,
Is provided.

The operation of the pulse width modulation recording signal generator will be described with reference to a time chart shown in FIG.

The reference clock 6 shown in (a) is obtained by dividing the synchronous clock (pixel clock 205) for each pixel by half. The pixel clock 205 shown in (x) is
This is a synchronization signal for inputting the multi-value image information 11 shown in (y).

The delay clock generating means 1 generates a plurality of delay clocks 7 (7-1) having different delay times as shown in (b) to (i) based on the reference clock 6 shown in (a).
To 7-15). In FIG. 22, eight odd-numbered clocks (7-1, 7-3,...) Are extracted from the sixteen delayed clocks 7 generated by the delayed clock generator 1, and illustrated. The delay times of the eight delay clocks 7 shown in (b) to (i) from the reference clock 6 are t1 to t8, respectively.

FIG. 23 is a block diagram showing an example of the delay clock generating means 1. This delay clock generation means 1 connects 16 buffer gates 13 to 28 in series, and 16 delay clocks 7 (with delay steps different from the reference clock 6 input to the first buffer gate 13 stepwise). 7-1 to 7-16).
The number of buffer gates 13 to 28 is determined by the relationship between the required number of generated pulses 10 and the delay time per buffer gate. Generally, the delay time per buffer gate is as short as about 5 ns. Accordingly, if the delay time of one pixel is about 30 ns (corresponding to a pixel frequency of 33 MHz), six buffer gates are connected in series to obtain each delayed clock output from the output terminal of each buffer gate, thereby obtaining 1 A delay time obtained by dividing the time of a pixel into six can be obtained. As described above, according to the delay clock generation means 1, by increasing the number of stages of the buffer gates connected in series, it is possible to easily obtain many and short delay times to be applied to a high-frequency image.

However, the delay time per buffer gate is not always equal for each buffer gate, but depends on the configuration (individual difference) of the buffer gate, connection method, environmental conditions, and the like. That is, a discrete TTL gate, a gate formed inside the LSI, or the like is used as the buffer gate, but the delay time of each buffer gate is not constant due to the effects of wiring delay and temperature. For this reason, a delay clock corresponding to one pixel time cannot be fixed and handled. It is necessary to measure a delay clock corresponding to one pixel time at least until the image forming apparatus is activated and the operating temperature is stabilized, or for each screen or sheet of the image output apparatus.

The delay time measuring means 2 receives the delay time measuring signal 65, periodically or irregularly at the time of starting up the apparatus or immediately before the image forming process, etc.
The delay time of (7-1 to 7-16) is measured. That is, the falling clock (time T1) of the reference clock 6 is used as the sampling clock 34, and the delay clock 7 (7-x) that obtains the delay time corresponding to the time t0 of one pixel is selected. In the example shown in FIG. 22, the delay clock 7-11 (t6) and the delay clock 7-13 in which the state of the delay clock 7 changes from “1” to “0” immediately before and immediately after the time T1.
(T7) is detected. From this detection result, it is determined that the delay clock 7-11 (t6) is a delay clock that obtains a delay time corresponding to one pixel time t0, and outputs “11” represented by a decimal number as a delay time measurement value 8. (Figure 2
4 and in FIG. 25 are output in binary).

The delay clock selecting means 3 includes 16 delay clocks 7-1 to 7 generated by the delay clock generating means 1.
A desired number of delay clocks 7 (in the example, some of 7-1 to 7-11) falling within the time of the delay time measurement value 8 from -16
Select The desired number is determined according to the maximum gradation (number of gradations) of the input image information 11 or the required halftone of the output image. In the illustrated example, from among the delay clocks 7-1 to 7-11 falling within the time of the delay time measurement value 8, FIG.
As shown in (j) to (o), in order to obtain a generated pulse 10 (10-1 to 10-6) in which the pulse width difference is substantially equal (strictly different from the characteristics of the buffer gate), Odd-numbered buffer gates 13, 15, 17, 1
Six delayed clocks 9, 9, 21 and 23 are selected and output as the selected delayed clock 9. The method of selecting the selection delay clock 9 may be, for example, such that the pulse width ratio of the generated pulse 10 is constant, other than equalizing the pulse width difference.

The pulse generating means 4 performs a logical operation on the selected reference clock 6 and the selected delay clock 9 (six in this example), and as shown in FIGS. The generation pulse 10 (10-1 to 10-6) is generated.

The pulse selecting means 5 receives multi-valued (for example, eight-stage) image information 11 and generates six generated pulses 10
And one of eight pulses including all white (all 0) and all black (all 1) corresponding to the multi-valued image information 11 is selected, and a binary pulse width modulated in the time axis direction is selected. Image information 1
Output as 2.

In the example shown in FIG. 22, since the multivalued image information 11 (y) is "2" in decimal in the period from time T0 to time T1, the pulse selecting means 5 generates the generated pulse 10-2.
(K) is selected and the binary image information 12 as shown in (s) is selected.
Is output. Then, during the period from time T1 to time T2, the multilevel image information 11 (y) is “5” in decimal, so the pulse selecting means 5 selects the generated pulse 10-5 (n) and sets it to 2 It is output as value image information 12 (s).

FIG. 24 is a block diagram showing an example of the delay time measuring means 2. The delay time measuring means 2 is constituted by a microcomputer 29. The 16 delay clocks 7 are sampled at the falling timing of the reference clock 6 by the delay time measurement signal 65, and from the sampling result, the delay time t0 shown in FIG. 22, that is, the delay time corresponding to one pixel is obtained. The number of stages of the buffer gate is detected. Here, the number of stages of the buffer gate for generating the delay clock 7-11 shown in (g) (= 11)
And outputs this as the delay time measurement value 8.

FIG. 25 is a block diagram showing another example of the delay time measuring means 2. This delay time measuring means 2
Comprises an inverter 30, a latch 31, and an encoder 32. The latch 31 that starts operating in response to the delay time measurement signal 65 latches the 16 delay clocks 7 (7-1 to 7-16) at the rising edge of the sampling clock 34 obtained by inverting the reference clock 6 and generates the latched data 33. Output. The encoder 32 encodes the latch data 33, that is, converts the latch data 33 into 4-bit binary data, and outputs the measured delay time 8 (8-1 to 8).
-4).

In the example of the time chart shown in FIG. 22, the measured delay time 8 is “1011” or “110”.
0 "(" 11 "or" 12 "in decimal).

In this way, it is possible to configure the delay time measuring means 2 that does not require a program.

FIG. 26 is a block diagram showing an example of the delay clock selection means 3. This delay clock selection means 3
Is composed of γ setting means 40, delay calculating means 41, and delay selecting means 42. The delay calculation means 41 calculates the delay time measurement value 8 (8-1 to 8-4) and the γ characteristic setting value 44, and calculates a delay time corresponding to each gradation to be assigned to a plurality of gradations. The delay selecting means 42 calculates an operation value (delay time) 43 (43-
1 to 43-8), the delay clock 7 (7-1 to 7-16) corresponding to the delay time of each gradation is selected and output as the selected delay clock 9 (9-1 to 9-8).

The delay time of each gradation to match the display or recording γ characteristic can be set as shown in FIG. FIG.
26 is an example of a γ characteristic curve of the γ setting means 40 shown in FIG. 26, and three types of curves are stored so as to be selectable. Thereby, the selection delay clocks 9 (9-1 to 9-
8) can be easily obtained.

FIG. 28 is a block diagram showing an example of the pulse generating means 4. The pulse generating means 4 is constituted by eight exclusive OR gates 50 to 57. 8 exclusive or gates 50-57
Is a reference clock 6 and eight selected delay clocks 9 (9-1 to 9-85) output from the delay clock selection means 3.
Is executed, and eight generated pulses 10 (10-
1 to 10-8).

FIG. 29 is a block diagram showing an example of the pulse selecting means 5. This pulse selecting means 5 is constituted by a selector 60. In correspondence with 3 bits, that is, 8 levels of multi-valued image information 11, 8 levels of generated pulses 1
0 (10-1 to 10-8) is selected, and the selected pulse 10-x is output as the binary image information 12.

By such an operation, the multi-level image information 11 of eight gradations is converted into binary image information 12 of which pulse width is modulated to eight gradations in the time axis direction.

By doing so, it is possible to easily generate binary image information pulse-width modulated in multiple stages in synchronization with the pixel clock, so that even a multi-valued image signal having a high pixel clock frequency can be easily generated. Can be applied to
In addition, since the delay clock that is the source of the multi-step pulse width is selected by measuring the delay time, the accuracy of dividing the pixel time corresponding to the gradation resolution can be improved, and a high-quality image can be obtained. Can be formed.

FIG. 32 is a block diagram of an image forming system using a laser printer as an image forming apparatus.
This image forming system includes a pulse width modulation recording signal generator 80, a personal computer 81, a laser printer 82, and a controller 83.

The control unit 83 sends a BD corresponding to a synchronization signal of one scanning line from the laser printer 82 for scanning and recording.
When a signal 84 is input, a pixel clock for each line is generated, and the reference clock 6 obtained by dividing the pixel clock by １ ／.
Is output. Further, it outputs a gradation number designation signal 75 of the laser printer 82 and a delay time measurement signal 65 at a timing that requires measurement.

As described above, the pulse width modulation recording signal generator 80 generates a plurality of delay clocks starting from the reference clock 6, and generates a delay clock corresponding to one pixel time at the timing of the delay time measurement signal 65. Measure, Part 1
The number of delay clocks required to divide the pixel time in accordance with the resolution designation signal 75 is selected, and a pulse having a pulse width corresponding to the delay time of each selected selected delay clock is generated. Then, a pulse having a corresponding pulse width is selected in accordance with the gradation of the multi-valued image information 11 input from the personal computer 81, and converted into binary image information (pulse width modulated pulse signal) 12 to the laser printer 82. Output.

The laser printer 82 blinks the laser beam with the pulse width modulated binary image information 12 to create and record a halftone image.

In this example, the multi-valued image information source is the personal computer 81. However, a digital camera or an image scanner that outputs a multi-valued image signal can be used. As the image output device, a printer using another recording method such as an ink jet printer or a thermal printer, or a display device can be used.

Next, an image forming apparatus capable of coping with a change in resolution of multi-valued image information will be described. FIG.
FIG. 2 is a block diagram of a pulse width modulation recording signal generator in the image forming apparatus. The same components as those of the pulse width modulation recording signal generator shown in FIG. 21 are denoted by the same reference numerals, and redundant description will be omitted. The difference from the pulse width modulation recording signal generator shown in FIG. 21 is that a clock selection means 70, a second delay clock selection means 71, and a third delay clock selection means 72 are added.

The operation of the pulse width modulated recording signal generator will be described with reference to a time chart shown in FIG.

This image forming apparatus has a resolution specifying signal 73
As a result, the time of one pixel shown in FIG. 31 changes to two types, t9 (resolution A) and t10 (resolution B). For example, signals (a), (d),
(L) is the signal (p), (q),
(R).

The clock selecting means 70 receives the first reference clock 74 and the second reference clock 75, selects one of them based on the resolution designation signal 73, and outputs it as a selected reference clock 76. Each pulse width of the first reference clock 74 and the second reference clock 75 corresponds to one pixel time at each resolution.

As in the case of the delay clock selecting means 3, the second delay clock selecting means 71 selects a desired one of the plurality of delay clocks 7 (7-1 to 7-15) based on the measured delay time 8. A plurality of delayed clocks are selected and output as a second selected delayed clock 77.

The third delay clock selection means 72 selects one of the delay selection clock 9 and the second delay selection clock 77 in accordance with the resolution designation signal 73, and generates a pulse as the third selection delay clock 78. Enter 4

According to this example, since the selection reference clock and the third selection delay clock are selected according to the designated resolution, even if the resolution changes, the same multi-valued image information 1 is obtained.
In the case of 1, the binary image information 12 is a pulse signal having the same pulse width with respect to the time of one pixel, so that an image of the same quality can be formed.

[0046]

According to the above-described image forming method and apparatus, even if the image frequency of the multi-valued image signal increases, the binary image signal that has been pulse-width modulated in synchronization with the pixel clock can be obtained. Since it can be generated, a high-quality halftone image can be formed at high speed.

Further, since the delay time of the delay clock, which is the base of the pulse width, is measured online to cope with the fluctuation, a large number of delay clocks with a small delay time can be easily generated by a buffer gate or the like. In addition, it is possible to easily form an image based on high-frequency multivalued image information.

By the way, in such an image forming method and apparatus, in order to improve the quality of an image to be formed, it is necessary to reduce the jaggedness appearing on the inclined edge of the image and to make it smooth.

An object of the present invention is to provide a method and apparatus for forming an inclined edge of an image into a smooth shape suitable for an image forming method and apparatus based on such high-frequency image information. is there.

[0050]

One feature of the present invention is that:
In an image forming method for converting binary image information into binary image information modulated in a time axis direction based on a pattern detection signal, a plurality of delay clocks having delay times different in stages are generated in synchronization with a pixel clock. Then, the number of delay clocks necessary to divide one pixel time is selected from among them,
A pulse having a time width corresponding to the delay time of the selected delay clock is generated, and a pulse on a corresponding time axis corresponding to the pattern detection signal is output as binary image information.

Another feature is that a plurality of delay clocks having different delay times are generated in synchronization with the pixel clock, and the number of delay clocks necessary to divide one pixel time is selected from the plurality of delay clocks. An image forming method for generating a pulse having a time width corresponding to the delay time of the selected delay clock and outputting a pulse having a time width corresponding to the input gradation of the multi-valued image information as binary image information. In other words, a pulse of a corresponding time width is selected according to the input gradation of the multi-valued image information and is output as binary image information.

Further, another characteristic is that a plurality of first delay clocks having different delay times in stages are generated in synchronization with a reference clock obtained by dividing the pixel clock, and one pixel time is divided from the first delay clocks. The first delay clock of the number necessary for the first delay clock is selected, a first pulse having a time width corresponding to the delay time of the selected first delay clock is generated, and the delay time is gradually changed in synchronization with the pixel clock. A plurality of different second delay clocks are generated, a number of second delay clocks necessary to divide one pixel time are selected from among them, and a time corresponding to the delay time of the selected second delay clock is selected. A second pulse having a width is generated, and the first or second pulse is output as binary image information based on a pattern of image information.

Another feature is an image forming apparatus that controls a laser beam of a laser printer using binary image information output by these image forming methods.

[0054]

BRIEF DESCRIPTION OF THE DRAWINGS FIG.
This will be described with reference to FIG.

Binary image information (pulse signal) obtained by modulating multi-valued image information other than ordinary gradation information in the time axis direction
An image forming apparatus which is used to form an image after converting it into an image will be described.

FIG. 8 is a block diagram of an image forming system using a laser printer as an image forming apparatus. This image forming system includes a pulse width modulation recording signal generation device 200, a personal computer 81, and an image processing device 2
01 and the control device 83.

The control device 83 receives a BD signal 84 corresponding to a synchronizing signal of one scan line from the laser printer 82 for scanning and recording, as in the case of the control device 83 in the conventional image forming system shown in FIG. Clock 2
05, and outputs a reference clock 6 obtained by dividing the pixel clock 205 by １ ／ and a delay time measurement signal 65.

The image processing apparatus 201 synchronizes the binary image information 202 inputted from the personal computer 81 with the main scanning direction corresponding to the laser scanning direction of the laser printer 82 in synchronization with the BD signal 84 and the pixel clock 205. ,
The image is developed in two dimensions (bit map data) in the sub-scanning direction orthogonal to the main scanning direction, detects a specific pattern in which jaggies appearing on the inclined edge of the image are noticeable, and detects a pattern detection signal 203 of a pixel of interest described later. Output as For example, as shown in FIG. 9, the binary image information 202 is composed of 5 pixels in the main scanning direction and 5 × 5 (= 25) of 5 pixels in the sub-scanning direction.
In the image developed in the pixel area, the pixel surrounded by a bold frame at the center of the image is set as the pixel of interest and the NO. 1 to NO. Which of the eight types of patterns up to 8 is applicable is detected by pattern recognition and output. Also, the pattern detection signal 2
It also outputs the binary image information 204 of the target pixel synchronized with 03.

The pulse width modulation recording signal generating device 200
A plurality of delay clocks are generated starting from the reference clock 6, a delay clock corresponding to one pixel time is measured at the timing of the delay time measurement signal 65, and the number of delay clocks required to divide the one pixel time is measured. Is selected, and a pulse having a pulse width corresponding to the delay time of each selected delay clock is generated. Then, in accordance with the pattern detection signal 203 input from the image processing apparatus 201, as shown in FIG. 9, the binary image information (pulse) modulated in the time axis direction corresponding to the corrected modulation pattern of the target pixel. 233).

FIG. 1 shows a pulse width modulation recording signal generator 2
FIG. 2 is a block diagram showing an embodiment of the present invention. The difference from the conventional pulse width modulation recording signal generator shown in FIG.
The configuration is such that a generated pulse pattern setting means 90 is provided, and further, a second pulse generation system is added, and the pulse selecting means 211 selects and outputs one of the three signals. The first delay clock generation means 220 corresponds to the delay clock generation means 1 and the first delay time measurement means 222
Corresponds to the delay time measuring means 2. In addition, the second delay clock generation means 225 and the second delay time measurement means 2
27 has the same configuration as the delay clock generation means 1 and the delay time measurement means 2.

The pulse width modulated recording signal generator 200
Will be described with reference to a time chart shown in FIG.

The reference clock 6 shown in (a) is obtained by dividing the pixel clock 205 shown in (x) by 1/2. The pixel clock 205 shown in (x) is a synchronization signal for inputting the binary image information 204 shown in (y). Also,
The pattern detection signal 203 shown in (r) is also input in synchronization with the pixel clock 205.

The first delayed clock generation means 220
Based on the reference clock 6 shown in FIG.
A plurality of first delay clocks 221 (22) shown in (i)
1-1 to 221-15) are generated. FIG. 4 shows the delay clock 221-6 shown in (d) and the delay clock 221-1 shown in (g) among the 16 delay clocks 221 generated by the first delay clock generation means 220.
With the exception of 2, the odd numbers (221-1, 221-3,...)
..) Are extracted and illustrated. The delay times of the eight first delay clocks 221-1 to 221-15 shown in (b) to (i) from the reference clock 6 are t1, t3, t6, t7, and t, respectively.
9, t12, t13, and t15.

The first delay time measuring means 222
Is determined to be the delay clock 221-12 (t12) for obtaining the delay time corresponding to one pixel time t0, and this is referred to as the first delay time. The measured value 223 is a decimal number “1”.
2 "(in the example of FIGS. 24 and 25, a binary number was output).

The first delayed clock selecting means 210 outputs the one generated by the first delayed clock generating means 220.
Six first delay clocks 221 (221-1 to 221)
-15), a corresponding delay clock is selected in accordance with the first measured delay time value 223 and the first generated pulse pattern setting signal 91 from the generated pulse pattern setting means 90, and this is selected as a first selected delay. Output as clock 206. In the illustrated example, assuming that the generated pulse pattern setting means 90 has set so as to output the generated pulse 207-6 having a pulse width of の of the time t0 of one pixel, the delay clock 221 shown in FIG. -6 is the first selection delay clock 206. In the example of FIG. 4, since the delay clock for obtaining the delay time corresponding to the time t0 of one pixel is the delay clock 221-12 shown in (g), the pulse 207 that can be set by the generated pulse pattern setting means 90 is used. The division number is “12”.

The first pulse generation means 224 performs a logical operation of the reference clock 6 and the selected delay clock 206 to generate a generation pulse 207 (207-6) shown in FIG.

The second delay clock generation means 225
Based on the pixel clock 205 shown in (x), (m)
A plurality of second delayed clocks 226 shown in (q) are generated. FIG. 4 shows the five delayed clocks 22 shown in (m) to (q) out of the eight delayed clocks 226.
6-1 to 226-5 are illustrated.

The second delay time measuring means 227 is a delay clock for obtaining the delay time corresponding to t0 / 2 from the delay clock 226-4 shown in (p), similarly to the first delay time measuring means 222. It determines that there is, and outputs “4” in decimal as the second measured delay time 228.

The second delay clock selection means 229 is operated by the second delay clock generation means 225 according to the second measured delay time value 228 and the second generation pulse pattern setting signal 92 from the generation pulse pattern setting means 90. A corresponding delay clock is selected from the generated eight second delay clocks 226, and this is output as a second selected delay clock 230. In the illustrated example, it is assumed that the second generated pulse pattern setting unit 231 is set to output a generated pulse 232-2 having a pulse width of の of the time t0 / 2, which is half of one pixel.
The delay clock 226-2 shown in (n) becomes the second selection delay clock 230. In FIG. 4, since the delay clock for obtaining the delay time corresponding to half the time t0 / 2 of one pixel is the delay clock 226-4 shown in (p), the second clock that can be set by the generated pulse pattern setting means 90
Of the generated pulse 232 becomes “4”.

The second pulse generation means 231 performs a logical operation of the pixel clock 205 and the second selection delay clock 230, and generates a second generation pulse 232- shown in FIG.
Generate 2.

The pulse selecting means 211 receives the pattern detection signal 203, selects one pulse from the binary image information 204, the first generated pulse 207 and the second generated pulse 232, and It is output as binary image information (pulse width modulation recording signal) 233 modulated in the direction.
Not all the binary image information 233 is modulated in the time axis direction, and the binary image information 233 differs depending on the pattern detection result by the image processing apparatus 201. For example, a pixel of interest when eight types of patterns shown in FIG. Only will be modulated.

In the example of FIG. 4, during the period from time T0 to time T1, the NO. 1 comes, and the pattern detection signal 203 becomes the pattern NO. 1 is detected, the pulse selection means 211 determines (k)
Is generated. In the period from time T1 to time T2, since the pattern detection signal 203 indicates that there is no corresponding pattern, the pulse selecting unit 211 selects and outputs the binary image information 204. In this way, the binary image information 233 shown in (s) is determined.

FIG. 14 shows the generated pulse pattern setting means 9.
0 is a block diagram showing one embodiment. FIG. The generated pulse pattern setting means 90 is provided by the microcomputer 27.
0. First delay time measurement 223
And the second delay time measurement value 228, the number of generation pulse stages that can be set is determined, and a first generation pulse pattern setting signal 91 and a second generation pulse pattern setting signal 92 are output according to the respective setting values.

FIG. 3 shows an example of this setting pattern. For example, when the pulse width of the generated pulse 207 is set to 6/12 (one pixel is divided into 12 steps to have a pulse width of 6 steps), the first generated pulse pattern setting signal 91 is used as the arithmetic expression “÷ 2.0 "is output.

FIG. 2 is a block diagram showing an embodiment of the delay clock selection means 210. The delay clock selecting means 210 includes a delay calculating means 234 and a delay selecting means 2
12. The delay calculating means 234 calculates the measured delay time 223 according to the calculation formula given by the generated pulse pattern setting signal 91 and calculates
Outputs 1. The delay selecting means 212 calculates the calculated value 21
1, the delayed clock 221 (221-1 to 221)
-16), and selects one from the selected delay clock 2
06 is output. In this example, the pulse width “6/1” shown in FIG.
2 ”(1 pixel is divided into 12 pixels and the pulse width of the 6 pixels is set), so that the delay calculation means 234 receives the generated pulse pattern setting signal 91 indicating the operation formula“ ÷ 2 ”. Is entered. In FIG. 4, the first delay time measurement value 223 (corresponding to the first delay clock 221-12) is 10
The arithmetic value 211 is “6” in decimal because it is “12” in decimal notation, and the delayed clocks 221-1 to 221-16
The sixth delay clock 221-6 is selected from the above and becomes the selected delay clock 206.

The selected delay clock 206 changes depending on the arithmetic expression of the arithmetic processing performed by the delay arithmetic means 234, and as shown in FIG. 3, the arithmetic expression is changed so that the pulse width of the generated pulse 207 changes.

FIG. 12 is a block diagram showing an embodiment of the first pulse generation means 224. The first pulse generating means 224 is provided with the exclusive OR gate 26.
0 and an inverter 261. The exclusive OR gate 260 is connected to the reference clock 6 and the first
Of the selected delayed clock 206 (corresponding to the delayed clock 221-6 shown in FIG. 4) to generate a first generated pulse 207-6. And inverter 2
61 inverts the first generated pulse 207-6 to generate a first inverted generated pulse 207-6N.

FIG. 13 is a block diagram showing an embodiment of the second pulse generation means 231. The second pulse generating means 231 is provided with the exclusive OR gate 26.
2 and an inverter 263. The exclusive OR gate 262 performs a logical operation of the pixel clock 205 and the second selected delay clock 230 (corresponding to the delay clock 226-2 shown in FIG. 4) to perform the second operation.
Is generated. Inverter 263
Generates the second inverted generated pulse 232-2N by inverting the second generated pulse 232-2.

FIG. 10 is a block diagram showing one embodiment of the pulse selecting means 211. This pulse selecting means 21
1 is constituted by a selector 264. The selector 264 outputs four bits, that is, binary image information 204, a first generated pulse 207-6, a first inverted generated pulse 207-6N, in accordance with the pattern detection signal 203 indicating eight types of pattern information. Second generated pulse 232-
2 and one pulse from among four types of second inversion generation pulses 232-2N are selected and output as binary image information 233. By this operation, the pattern detection signal 20
3, the binary image information 23 modulated in the time axis direction
3 is obtained.

FIG. 11 shows the pattern detection signal 203 and FIG.
Shows the relationship with the pattern numbers shown in FIG. The pattern detection signal 20 according to the pattern number in FIG.
3 changes, and the binary image information 233 changes. In this way, it is possible to obtain the binary image information 233 of the pixel of interest subjected to pulse width modulation as shown in the column after correction in FIG.

According to the above-described embodiment, it is possible to easily set the pattern of the generated pulse which is the basis of the pulse width-modulated binary image information, and the pulse width is synchronized with the pattern detection signal. Since modulated binary image information can be generated, it is possible to form a high-quality image with reduced (smooth) jaggedness appearing on the inclined edge of the image.

Next, another embodiment of the pulse width modulation recording signal generator 200 according to the present invention will be described.

FIG. 5 is a block diagram of a pulse width modulation recording signal generator 200 according to another embodiment. Pulse width modulation recording signal generator 20 in this embodiment
0 is the delay clock generation means 1 and the delay time measurement means 2
, Delay clock selection means 290, and pulse generation means 2
42, a generated pulse pattern setting means 240, and a pulse selecting means 292.

This pulse width modulation recording signal generator 200
Will be described with reference to a time chart shown in FIG.

The reference clock 6 shown in (a) is obtained by dividing the pixel clock 205 shown in (x) by 1/2. The pixel clock 205 (x) shown in (x) is (y)
Is a synchronization signal for inputting the binary image information 204 shown in FIG. 7 and the pattern detection signal 203 shown in FIG.

The delay clock generator 1 generates eight delay clocks 7 (7-1 to 7-8) shown in (b) to (i) based on the reference clock 6 shown in (a). In the example shown in FIG. 6, the delay times of the eight first delay clocks 7-1 to 7-8 shown in (b) to (i) from the reference clock 6 are represented by t1 to t8, respectively. did.

The delay time measuring means 2 performs the delay clock 7-6 (t6) in the same manner as the above-described delay time measuring device.
Is determined to be a delay clock that obtains a delay time corresponding to one pixel time t0, and
Outputs "6" in base 0.

The delayed clock selecting means 290 combines the eight delayed clocks 7 generated by the delayed clock generating means 1 in accordance with the generated pulse pattern clock setting signal 293 given from the generated pulse pattern setting means 240 to generate the generated clock 291-1. To 291-8.
In this example, the generated clocks 291-7 and 291-8 are "0". In the example shown in FIG. 6, the delay clock for obtaining the delay time corresponding to the time t0 of one pixel is (g).
, The generated pulse 2 which can be set by the generated pulse pattern setting means 240
The number of divisions of 43 becomes “6”.

The pulse generating means 242 generates the generated pulse 243 shown in FIG. 6 (t) according to the generated pulse pattern setting signal 241.

The pulse selecting means 292 selects one of the binary image information 204 and the generated pulse 243 according to the input pattern detection signal 203, and outputs the binary image information modulated in the time axis direction (pulse width). (Modulated recording signal) 233.

In the example shown in FIG. 6, during the period from time T0 to time T1, the pattern detection signal 203 changes the pattern NO. Since it indicates 1, the pulse selecting means 292 selects and outputs the generated pulse 243 of (t). In addition,
The example of FIG. 6 differs from the example of FIG.
At the time of 1, the generation pulse 243 of (t) is output. In the period from time T1 to time T2, since the pattern detection signal 203 indicates that there is no corresponding pattern, the pulse selecting means 292 selects and outputs the binary image information 204. Thus, the binary image information 23 shown in FIG.
3 is determined.

FIG. 17 is a block diagram showing an embodiment of the delay clock selection means 290. The delay clock selecting means 290 is composed of a microcomputer 294 and eight exclusive OR gates 301 to 308. Then, according to the generated pulse pattern clock setting signal 293 given from the generated pulse pattern setting means 240, the microcomputer 294 and the exclusive OR gates 301 to 308 combine the eight delayed clocks 7-1 to 7-8 inputted. The generated clocks 291-1 to 291-8 are generated. In this example, the generated clocks 291-7 and 291-8 are "0" (= Low).

FIG. 15 shows generated pulse pattern setting means 2.
FIG. 4 is a block diagram illustrating one embodiment of the present invention. The generated pulse pattern setting means 240 is constituted by a microcomputer 280. Then, the delay time measurement value 8 determines the number of stages of the generated pulse that can be set,
According to the set value, the generated pulse pattern setting signal 24
1 and a generated pulse pattern clock setting signal 293 are output.

FIG. 16 shows an example of the setting pattern.
For example, when the generated pulse 243 is set as shown in FIG. 16, the generated pulse pattern setting means 240 sets so as to output a signal having a pattern as indicated by the generated pulse pattern setting signals 241-1 to 241-6.

FIG. 7 is a block diagram showing an embodiment of the pulse generating means 242. This pulse generating means 242
Are OR gates 257 and 258 and an inverter 259
, P / SA, P / SB (P / S = parallel input serial output shift register) 251, 253, and a selector 256.

The OR gate 257 generates a shift clock A250 based on the input generated clocks 291-1, 291-3, 291-5, and 291-7. The OR gate 258 receives the generated clocks 291-2 and 291
The shift clock B252 is generated based on -4,291-6,291-8.

The P / S-A 251 generates the generated clock 291
-1 as the load A signal, the odd-numbered patterns 241-1 and 241- in the generated pulse pattern setting signal 241.
3, 241-5 are loaded, and the serial output A signal 254 is shifted by the shift clock A250. Similarly, the P / S-B 253 sets the generated pulse pattern setting signal 241 using the generated clock 291-2 as the load B signal.
Even-numbered patterns 241-2, 241-2, and 24 in
1-6 are loaded, and the serial output B signal 255 is shifted by the shift clock B252.

The selector 256 outputs the serial output A signal 2
54 and the serial output B signal 255 are switched according to the selection signal 275 and output as a generated pulse 243.

FIG. 18 is a block diagram showing one embodiment of the pulse selecting means 292. This pulse selecting means 29
2 comprises a selector 285. And
Binary image information 204 according to pattern detection signal 203
And one of the generated pulses 243 is selected and output as binary image information (pulse width modulated recording signal) 233.

With such an operation, the binary image information 233 modulated in the time axis direction according to the pattern detection signal 203 is generated.

According to this embodiment, it is possible to arbitrarily set the pattern of the generated pulse which is the basis of the pulse width modulated binary image information, and to perform the pulse width modulated pulse synchronization with the pattern detection signal. Since the value image information can be generated, it is possible to form a high-quality image with less jaggedness appearing at the edge of the image.

In the above example, one generated pulse is used. However, by using a plurality of pulse generating means 242, a plurality of generated pulses can be easily generated.

As shown in the example of FIG. 30, by inputting the resolution designation signal 73, the laser printer 82
Even if the resolution changes, a modulation signal having the same ratio of pulse width to the time of one pixel can be generated to form an image of the same quality.

FIG. 19 is a block diagram showing another embodiment of the pulse generating means 242. This pulse generating means 2
42 is AND gates 311 to 320 and OR gate 3
22.

The operation of this pulse generation means 242 is shown in FIG.
This will be described with reference to the time chart of FIG.

The generated clock 291 shown in (b) to (k)
-1 to 291-10 are delay clock selection means 290
(See FIG. 17). In the case where the high time of each generated clock is minimized, ignoring the delay time due to the wiring, the buffer gates 13 to 13 constituting the delayed clock generating means 1 shown in FIG. It is equal to the delay time of each of the 28 stages. That is, the generated clock 291-
The pulse width of 1 becomes the delay time of the buffer gate 13 shown in FIG. The pulse width of each of the generated clocks 291-1 to 291-10 shown in (b) to (k) is the time of each step of the generated pulse pattern setting signal 241 shown in (a), that is, the time for dividing one pixel time. become.

Here, when the generated pulse pattern setting signal 241 shown in (a) is set, each bit 241-1 to 241-10 of each generated pulse pattern setting signal and each generated clock 291-1 to 291- 10 is ANDed by each of AND gates 311 to 320, and each pixel divided output 32
1-1 to 321-10, and the pixel division output 321
-1 to 321-10 are further ORed with an OR gate,
The generated pulse 243 shown in FIG.

The case where the number of divisions of the generated pulse pattern setting signal 241 shown in (a) is "10" has been described, but this number of divisions is the same as that of the buffer gate 1 shown in FIG.
It depends on the delay time of 3-28. That is, when the delay time of the buffer gates 13 to 28 is short, the number of divisions of the generated pulse pattern setting signal 241 is large, and conversely, when the delay time of the buffer gates 13 to 28 is long, the number of divisions of the generated pulse pattern setting signal 241 is small. Less. When the delay time of the buffer gates 13 to 28 becomes longer, FIG.
End of one pixel shown at 0 (right side in FIG. 20)
Is no longer generated (L
ow), so even if it is set, it becomes invalid (not generated).

As shown in FIG. 15, the measured delay time 8 is input to the generated pulse pattern setting means 240, and the number of divisions per pixel time becomes clear before the generated pulse pattern is set. So there is no need to set unusable steps.

[0110]

According to the present invention, the pulse width modulated 2
It is possible to arbitrarily set the pattern of the generated pulse that is the basis of the value image information, and it is possible to generate pulse width modulated binary image information synchronized with the pattern detection signal. A high-quality image with less jagged appearance can be formed.

Further, even if the image frequency of the multi-valued image signal is increased, a binary image signal whose pulse width is modulated can be generated at a stage synchronized with the pixel clock, so that a high-quality halftone image can be formed at high speed. be able to.

Further, since the delay time of the delay clock, which is the source of the pulse width, is measured online to cope with the fluctuation, a large number of delay clocks with a short delay time can be easily generated by a buffer gate or the like. In addition, it is possible to easily form an image based on high-frequency multivalued image information.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a pulse width modulation recording signal generating device in an image forming system according to the present invention.

FIG. 2 is a block diagram of a first delay clock selecting means in the pulse width modulation recording signal generator shown in FIG.

FIG. 3 is a diagram showing a relationship between a pulse width of a generated pulse shown in FIG. 1 and a first generated pulse pattern setting signal.

FIG. 4 is a time chart showing an operation of the pulse width modulation recording signal generator shown in FIG.

FIG. 5 is a block diagram showing another embodiment of the pulse width modulation recording signal generator according to the present invention.

FIG. 6 is a time chart showing an operation of the pulse width modulation recording signal generator shown in FIG.

FIG. 7 is a block diagram of a pulse generation unit in the pulse width modulation recording signal generation device shown in FIG.

FIG. 8 is a block diagram of an image forming system according to the present invention.

9 is an explanatory diagram of image processing in the image forming system shown in FIG.

FIG. 10 is a block diagram of a pulse selecting means in the pulse width side recording signal generating apparatus shown in FIG. 1;

FIG. 11 is a diagram illustrating a relationship between a pattern number and a pattern detection signal illustrated in FIG. 9;

FIG. 12 is a block diagram of a first pulse generation means in the pulse width modulation recording signal generation device shown in FIG.

FIG. 13 is a block diagram of a second pulse generation unit in the pulse width modulation recording signal generation device shown in FIG.

FIG. 14 is a block diagram of a generated pulse pattern setting means in the pulse width modulation recording signal generator shown in FIG.

FIG. 15 is a block diagram of a generated pulse pattern setting means in the pulse width modulation recording signal generator shown in FIG.

16 is a diagram showing a relationship between a generated pulse pattern setting signal and a generated pulse in the pulse width side recording signal generator shown in FIG. 5;

FIG. 17 is a block diagram of delay clock selection means in the pulse width modulation recording signal generator shown in FIG.

FIG. 18 is a block diagram of a pulse selecting means in the pulse width modulation recording signal generator shown in FIG.

19 is a block diagram showing another embodiment of the pulse generation means in the pulse width modulation recording signal generation device shown in FIG.

FIG. 20 is a time chart showing the operation of the pulse generation means shown in FIG.

FIG. 21 is a block diagram of a pulse width modulation recording signal generator in a conventional image forming apparatus suitable for applying the present invention.

FIG. 22 is a time chart showing an operation of the pulse width modulation recording signal generator shown in FIG.

FIG. 23 is a block diagram of delay clock generation means in the pulse width recording signal generation device shown in FIG. 21;

24 is a block diagram of delay time measuring means in the pulse width recording signal generator shown in FIG.

25 is a block diagram showing another example of the delay time measuring means in the pulse width modulation signal generator shown in FIG.

FIG. 26 is a block diagram of delay clock selecting means in the pulse width modulated recording signal generator shown in FIG.

FIG. 27 is a γ characteristic diagram of γ setting means in the delay clock selecting means shown in FIG. 26;

FIG. 28 is a block diagram of a pulse generation unit in the pulse width modulation recording signal generation device shown in FIG.

FIG. 29 is a block diagram of a pulse selection means in the pulse width modulation recording signal generator shown in FIG.

FIG. 30 is a block diagram of another conventional image forming apparatus suitable for applying the present invention.

FIG. 31 is a time chart illustrating an operation of the image forming apparatus illustrated in FIG. 30;

FIG. 32 is a block diagram of a conventional image forming apparatus suitable for applying the present invention.

[Explanation of symbols]

1 ... delay clock generation means, 2 ... delay time measurement means, 3
... delay clock selection means, 4 ... pulse generation means, 5 ... pulse selection means, 6 ... reference clock, 7 ... delay clock,
8: measured delay time, 9: selected delay clock, 10: generated pulse, 11: multi-value image information, 12: binary image information,
90: Generated pulse pattern setting means, 203: Pattern detection signal.

Claims (7)

[Claims] 1. An image forming method for converting binary image information into binary image information modulated in a time axis direction based on a pattern detection signal, wherein a plurality of delay times different in stages are synchronized in synchronization with a pixel clock. , A delay clock having a time width corresponding to the delay time of the selected delay clock is generated, and the pattern detection signal is generated. Outputting a pulse on a time axis corresponding to the image data as binary image information. 2. The image forming method according to claim 1, wherein the generated pulse on the time axis is set by generated pulse pattern setting means. 3. A plurality of delay clocks having different delay times in stages are generated in synchronization with the pixel clock, and a delay clock of a necessary number for dividing one pixel time is selected from the plurality of delay clocks. An image forming method for generating a pulse having a time width corresponding to a delay time of a clock and outputting a pulse having a time width corresponding to an input gradation of multi-valued image information as binary image information, comprising the steps of: An image forming method for selecting a pulse of a corresponding time width according to the input gradation of the image and outputting the selected pulse as binary image information. 4. The delay clock according to claim 3, wherein the required number of delay clocks is measured within the one pixel time from among the plurality of generated delay clocks, and is selected stepwise. An image forming method comprising: 5. The method according to claim 3, wherein when the pixel time changes due to a change in resolution of the binary image information, the number of delay clocks to be selected is increased or decreased according to the pixel time. Image forming method. 6. A plurality of first delay clocks having different delay times in stages are generated in synchronization with a reference clock obtained by dividing the pixel clock, and a number of first delay clocks required to divide one pixel time out of the first delay clocks are generated. Selecting the first delay clock, and selecting the selected first
A first pulse having a time width corresponding to the delay time of the delay clock is generated, and a plurality of second delay clocks having different delay times in stages are generated in synchronization with the pixel clock. The number of second delay clocks required to divide the second delay clock is selected, a second pulse having a time width corresponding to the delay time of the selected second delay clock is generated, and the second pulse is generated based on a pattern of image information. An image forming method, comprising: outputting the first or second pulse as binary image information. 7. An image forming apparatus, wherein a laser beam of a laser printer is controlled by binary image information outputted by the image forming method according to claim 1.