JPH0591491A - Digital signal transmission device - Google Patents

Abstract

(57) [Abstract] [Purpose] When a digital data signal of a predetermined number of channels is superimposed on a video signal as a time division multiplexed signal for transmission, the number of channels is changed in the middle of the field or frame of the video signal. Even if it is done, noise should not occur. [Structure] The received signal is a serial / parallel conversion circuit 1,
Audio / video separation circuit 5, 3 sample synthesis circuit 6
And a time-division-multiplexed digital audio signal of a predetermined number of channels is obtained. The time division multiplexed signal is time-axis expanded in the memory 7 controlled by the memory control circuit 4 and supplied to the audio data processing circuit 8. When the number of channels of the time division multiplexed signal changes, the audio data processing circuit 8 detects this and immediately controls the memory control circuit 4 to set the read frequency of the memory 7 according to the new number of channels. ..

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a device for superimposing digital data such as digital audio data on a digital video signal and converting it into serial data for transmission.
In particular, the present invention relates to a digital signal transmission device suitable for transmitting digital audio data of a plurality of channels together with a digital video signal.

[0002]

2. Description of the Related Art A system for converting digital data into serial data in 1-bit units and transmitting the data has hitherto been known.
For example, a digital audio serial interface standard has been proposed by AES (Audio Engineering Society). According to this standard, redundant bits are added to a 20-bit digital audio signal to form 32 bits, and serial data is transmitted in 1-bit units from the least significant bit side. According to this, a 2-channel digital audio signal can be transmitted through one transmission path.

By the way, in recent years, influenced by the development of a digital VTR, a serial digital signal for serial data transmission of a digital video signal on which time division multiplexed signals of up to 4 channels of digital audio signals are superposed. An interface standard has been proposed by SMPTE (Society of Motion Picture and Television Engineers). this is,
In this system, time-division multiplexed signals of digital audio signals are intermittently inserted in the horizontal and vertical synchronization areas of the digital video signals to transmit serial data. According to this, it becomes possible to transmit the digital video signal and the digital audio signals of up to 4 channels through one transmission path.

[0004]

In the serial interface system as described above, the received serial data is usually converted into parallel data, and thereafter the digital data is converted from the parallel data. Separated and extracted. Since the extracted digital audio data is intermittent data, it is processed on the time axis and becomes a continuous signal on the time axis. This time base processing is performed, for example, at the sampling frequency of the digital video signal in the parallel data, and the digital audio data is stored in the memory in the field or frame unit (1
A memory address is reset every 1 field or 1 frame) and the field is written from the memory at a frequency corresponding to the number n of channels of the digital audio data received and written. This is performed by reading out in frame units. According to such processing, digital audio signals of any number of channels can be transmitted.

By the way, the number of channels of a digital audio signal may be changed during transmission. If such a change is made by delimiting fields or frames, which are the writing units of the memory, the frequency of the memory read clock is changed according to the number of channels of the new digital audio signal in synchronization with the memory read reset. As a result, there is no excess or deficiency of data in each channel, and a time division multiplexed signal of a digital audio signal can be obtained in the original data string.

However, when the number of channels of the digital audio signal is changed in the middle of the field or frame, the frequency of the read clock of the memory is changed at the time of changing the number of channels. Because you can't
Within that field or frame, a digital audio
Even after the number of channels of the Dio signal is changed, the digital audio signal is read from the memory by the read clock having the frequency corresponding to the number of channels before the change. Therefore, the sampling frequency of each digital audio signal read out during this period is different from the original one, and when this portion is digital-to-analog converted, excess or deficiency of data may occur and noise may occur. become.

An object of the present invention is to solve such a problem and to prevent the generation of noise even if the number of channels of digital data is changed in the middle of a field or frame. It is to provide a digital signal transmission device.

[0008]

In order to achieve the above object, the present invention time-division-multiplexes different digital data signals of n channels (n ≧ 1) into one continuous digital data stream. Means for dividing the digital data sequence into periods of a horizontal or vertical synchronizing signal of a digital video signal, and digital data of each division is time-axis compressed to form an intermittent time division multiplex signal. Second means for inserting the intermittent time division multiplex signal into the digital video signal on the time axis by inserting in a predetermined area of horizontal or vertical synchronization of the video signal, and the digital on which the intermittent time division multiplex signal is time axis multiplexed. A third means for converting the video signal into serial data in 1-bit units and transmitting the serial data, a fourth means for receiving the serial data, and a parallel means for receiving the received serial data. Fifth means for converting to digital data to reconstruct the digital video signal, and the intermittent time division multiplex signal is separated and extracted from the reconstructed digital video signal and sequentially written, and the time axis is expanded to digitally Sixth means for reading out as a data stream and the number n of channels of the digital data signal in the digital data stream read out from the memory means are constantly detected, and the channel for which the read frequency of the memory is detected is detected. And a seventh means for setting the frequency according to the number n.

[0009]

In the transmission system, the n-channel digital data signal is time-division multiplexed to form an intermittent time-division multiplexed signal so as to match the digital video signal, and the intermittent time-division multiplexed signal is time-axis multiplexed to the digital video signal. Transmitted.

In the receiving system, the intermittent time division multiplexed signal is separated from the received digital video signal, and the sixth signal is generated.
Although the original time-division multiplexed signal on the time axis is obtained by writing and reading by the means, the reading by the sixth means is controlled by the seventh means. The seventh means constantly detects the number of channels of the time division multiplexed signal read from the sixth means, and makes the sixth reading at a frequency corresponding to the detected number of channels. Therefore, when the number of channels of the time division multiplexed signal changes, the sixth read frequency also changes accordingly,
All the digital data of the time division multiplexed signal of this channel number is read from the sixth means at a predetermined correct sampling frequency.

[0011]

Embodiments of the present invention will be described below with reference to the drawings. 1 and 2 are block diagrams showing an embodiment of a digital signal transmission apparatus according to the present invention. First, the transmission system thereof will be described with reference to FIG. However, in the figure, 10 is a synchronization detection circuit, 11 is a timing generation circuit,
12, 13 are data selectors, 14 are division processing circuits, 1
5 is a time axis processing circuit, 16 is a parallel / serial conversion circuit, 17 is a line drive circuit, 160, 170, 18
0, 190, 200 and input terminals, and 210 are output terminals.

In FIG. 2, it is assumed here that the maximum number of channels of the digital audio signal multiplexed and transmitted with the digital video signal is four channels. A parallel digital video signal having the bit number n2 is input from the input terminal 160, and input terminals 170, 180, 190, 2
00 to channel 1 (CH1) and channel 2 (CH
2), channel 3 (CH3), and channel 4 (CH4) parallel digital audio signals are input. The number of bits of these digital audio signals is n2.

The parallel digital video signal input from the input terminal 160 is supplied to the sync detection circuit 10 and the data selector circuit 12. The sync detection circuit 10 detects a horizontal sync signal and a vertical sync signal from the supplied digital video signal, and accordingly, a frame pulse signal having a frame cycle (FIG. 4A) and a line pulse signal having a line cycle. (FIG. 4B) is generated and output.
The frame pulse signal and the line pulse signal are supplied to the timing generation circuit 11.

The timing generation circuit 11 has these frames.
Input terminal 17 by the line pulse signal and the line pulse signal
0, 180, 190, 200 digital audio signals of respective channels (here, channel 1 (CH1), channel 2 (CH2), channel 3)
(CH3) and four digital audio signals of channel 4 (CH4) are input) to form and output channel designating signals CHM and CHL. The channel designation signal CHM is a signal having a frequency equal to the sample frequency FS of these digital audio signals, and the channel designation signal CHL is a signal having a frequency 1/2 times the sample frequency FS of these digital audio signals. These channel indication signals CHM, C
Depending on the HL level (HIGH level “H”, LOW level “L”), the channel of the digital audio signal is designated as follows. Channel 1 when CHM: "L" and CHL: "L"
(CH1) Channel 2 when CHM: "L" and CHL: "H"
(CH2) Channel 3 when CHM: "H" and CHL: "L"
(CH3) Channel 4 when CHM: "H" and CHL: "H"
(CH4).

The timing generation circuit 11 also receives the frame reset signal RST-W (FIG. 4C) and the memory read reset signal RST-W in the time axis processing circuit 15 in response to the frame pulse signal and the line pulse signal from the synchronization detection circuit 10. The reset area signal RST-R (FIG. 4 (d)) and the insertion area designating signal SEL1 (FIG. 3 ((3)) indicating the area in which the time-axis compressed digital audio signal within the horizontal synchronizing period of the digital video signal is to be inserted. g)) is formed. Write reset signal RST-W, read reset signal RST-
R is supplied to the time axis processing circuit 15, and the insertion area instruction signal SEL1 is supplied to the data selector 12 and the time axis processing circuit 15.
Supplied with.

Input terminals 170, 180, 190, 200
The sampling clocks of the digital audio signals of the respective channels input from are frequency equal to FS and are synchronized in phase, and the data selector 13 controls the channel specifying signals CHM and CHL from the timing generating circuit 11.
As shown in FIG.
As shown in (a), (b), and (c), channel 1,
The digital audio signals are repeatedly selected in the order of 2, 3, 4 and the digital audio signals of the channels 1, 2, 3, 4 are time-division-multiplexed in sample data units to form a time-division multiplexed signal. In this time division multiplexed signal,
Sampling data of digital audio signals of channels 1, 2, 3, and 4 are arranged one by one for each cycle of 1 / FS. This time division multiplexed signal is generated by the timing generation circuit 11
Channel designation signals CHM and CHL from FIG. 3 are added, and the time division multiplexed signal AUD1 having the number of bits (n1 + 2) (see FIG.
(C)) is supplied to the division processing circuit 14.

In the division processing circuit 14, a redundant bit such as a parity bit is added to the time division multiplexed signal AUD1 so that the bit number n2 of the digital video signal input from the input terminal 160 becomes an integer multiple of the bit number. Thereafter, each sample data is divided into the number of bits n2 of this digital video signal. FIG. 3D shows the time-division multiplexed signal AUD2 obtained in this way, but here, the time-division multiplexed signal AUD1 with the redundant bit added.
The number of bits of n is 3 of the number of bits n2 of the digital video signal
In this case, each sample data of the time division multiplexed signal AUD1 is divided into three. In this way, the time division multiplexed signal AUD2 having the same number of bits n2 as the digital video signal is obtained.

The time division multiplexed signal AUD2 (FIG. 3 (d)) output from the division processing circuit 14 is supplied to the time axis processing circuit 15. The time axis processing circuit 15 is composed of, for example, a memory, and starts writing the time division multiplex signal AUD2 to the memory based on the write reset signal RST-W from the timing generation circuit 11, and also the timing generation circuit 11 Read reset signal RST-R from
Based on the above, the reading of the time division multiplexed signal AUD2 from the memory is started. In this case, the write reset signal RST-
W is synchronized with the sample frequency FS of the digital audio signal, and the frequency is 12 times the sample frequency FS in order from the sample data of the channel 1 (CH1) digital audio signal in the time division multiplexed signal AUD2. Is written to memory. Then, in synchronization with the sample frequency Vck of the digital video signal, for example, the timing of the read reset signal RST-R delayed by one line with respect to the write reset signal RST-W is output from the timing generation circuit 11 as a time reference. During the "H" period of the insertion area designating signal signal SEL1, a time division multiplexed signal for almost one line is read from the memory at the same frequency as the sampling frequency Vck of the digital video signal. That is,
The time-division multiplexed signal AUD2 is sequentially written in this memory, but the sample data of the bit number n2 for almost one line at the same frequency as the sample frequency Vck of the digital video signal for each "H" period of the insertion area designating signal signal SEL1. The time division multiplexed signal is read out one by one. As a result, the sample data of each line of the time division multiplexed signal AUD2 is sequentially time-axis compressed within a predetermined period of the horizontal sync area of the input digital video signal indicated by the "H" period of the insertion area indication signal SEL1. Thus, the time-division-compressed time-division multiplexed signal (intermittent time-division multiplexed signal) AUD3 is obtained. FIG. 3E shows a part of the intermittent time division multiplexed signal AUD3.

The intermittent time division multiplex signal AUD3 output from the time axis processing circuit 15 is supplied to the data selector 12. This data selector 12 normally has an input terminal 160.
Although the input digital video signal from is selected and output, when the output insertion area instruction signal SEL1 from the timing generation circuit 11 becomes "H", the time axis processing circuit 15
The intermittent time division multiplex signal AUD3 from is selected and output. As a result, the intermittent time division multiplex signal AUD3 is inserted within a predetermined period designated by the insertion area designation signal SEL1 of the horizontal sync area of the input digital video signal, as shown in FIG.
As shown in (h), a multiplexed signal DATA in which a time division multiplexed signal is inserted in the input digital video signal is obtained.

This output multiplexed signal DATA is parallel / parallel
The sample data of the bit number n2 is supplied to the serial conversion circuit 16 and converted into serial data output from the least significant bit in 1-bit units, for example, and output from the output terminal 210 via the line drive circuit 17 for transmission. To be done. In this case, the bit frequency of this serial data is n2 × Vck.

Next, the receiving system of this embodiment will be described with reference to FIG. However, in the figure, 1 is serial /
Parallel conversion circuit, 2 synchronization detection circuit, 3 timing generation circuit, 4 memory control circuit, 5 audio / video separation circuit, 6 3 sample synthesis circuit, 7 memory, 8 audio data processing circuit, 9 Audio channel division circuit, 100 is an input terminal, 110, 12
0, 130, 140 and 150 are output terminals.

In FIG. 1, the received serial data input from the input terminal 100 is supplied to the serial / parallel conversion circuit 1, and the digital video signal and the digital audio signal obtained by the data selector 12 in FIG. 2 are time-divided. Multiplexed signal DATA of bit number n2
(FIG. 3 (h)) Parallel multiplexed signal DATA
'Is formed. The multiplexed signal DATA ′ is supplied to the audio / video separation circuit 5 and the synchronization detection circuit 2.

The synchronization detection circuit 2 detects horizontal and vertical synchronization signals from the multiplexed signal DATA 'and supplies them to the timing generation circuit 3. Based on these horizontal and vertical synchronizing signals, the timing generating circuit 3 outputs a signal having a frequency equal to the sampling frequency FS of digital audio data (hereinafter referred to as FS signal) and a signal having twice the frequency of this FS signal (hereinafter referred to as FS signal). 2FS signal), a signal having a frequency four times that of the FS signal (hereinafter referred to as 4FS signal), a read clock Ack having an integer multiple frequency of the 4FS signal, and the timing generation circuit 11 shown in FIG. The serial / parallel conversion circuit 1 corresponds to the insertion area instruction signal SEL1.
An insertion area instruction signal SEL1 'for instructing an insertion period of an intermittent time division multiplex signal such as a digital audio signal in the multiplex signal DATA' output from is generated. FS signal, 2FS signal, 4FS signal and read clock Ack
Is supplied to the memory control circuit 4, and 4FS
The signal is supplied to the audio data processing circuit 8 and the insertion area designating signal SEL1 'is supplied to the audio / video separation circuit 5, respectively.

In the audio / video separation circuit 5, the insertion area designating signal SEL1 'causes the sampling frequency Vck to be the same as the digital video signal having the sampling frequency Vck and the bit number n2 from the multiplexed signal DATA' from the serial / parallel conversion circuit 1. Are separated into an intermittent time division multiplexed signal of bit number n2. At this time, in the digital video signal, the original data is stored in the area where the intermittent time division multiplex signal is inserted (here, since this insertion area is an area within the horizontal synchronization signal, the horizontal synchronization signal Level data) is replaced. This digital video signal is output from the output terminal 110 to the outside.

On the other hand, the intermittent time division multiplexed signal separated by the audio / video separation circuit 5 is supplied to the 3-sample combining circuit 6, and the sample data having the bit number n2 is combined into threes to obtain the original bit number (n1 + 2). ), An intermittent time division multiplex signal having a sampling frequency of Vck / 3 is formed. This 3
The intermittent time division multiplexed signal output from the sample synthesis circuit 6 is time-axis processed in the memory 7, and the division processing circuit 1 of FIG.
A continuous time-division multiplexed signal on the time axis with the same number of bits (n1 + 2) as the time-division multiplexed signal AUD1 input to 4 is obtained. The time-axis processing operation will be described below.

That is, by the memory control circuit 4,
The write enable signal RE is generated from the FS signal, the 2FS signal, the 4FS signal, the read clock Ack, and the enable gate signal GP formed in the audio data processing circuit 8 as will be described later, which are generated by the timing generation circuit 3 as described above. It is formed. This read enable signal R
When E is "H", the memory 7 is in the read mode.

The memory 7 is synchronized with the signal of frequency Vck / 3 (where Vck is the sampling frequency of the digital video signal) based on the frame pulse signal and the line pulse signal detected by the synchronization detection circuit 2. A write reset signal RST-W 'of one frame period is formed, whereby writing is started, and the sampling frequency Vck / 3 from the three-sample synthesis circuit 6 and the number of bits (n
1 + 2) the insertion area instruction signal SE output from the timing generation circuit 3 by the write clock of the frequency Vck / 3 synchronized with the sample data of the intermittent time division multiplex signal.
During the "H" period of L1 ', the intermittent time division multiplexed signal from the 3-sample synthesis circuit 6 is written. Then, the sample data of the written intermittent time division multiplex signal from the memory 7 is read by the read clock Ack whose timing coincides with the "H" period of the read enable signal RE from the memory control circuit 4. The read sample data is held by a latch circuit or the like until the next sample data is read, and is supplied to the audio data processing circuit 8. This reading is started by a read reset signal RST-R 'formed on the basis of the frame pulse signal and the line pulse signal detected by the synchronization detecting circuit 2, and this read reset signal RST-R' is the above-mentioned FS.
It is synchronized with the signal.

4, when the frame pulse signal and the line pulse signal detected by the synchronization detection circuit 2 are shown in FIGS. 4A and 4B, the write reset signal RST-W 'is shown in FIG. , (F) in the figure shows the read reset signal RS
T-R '.

Here, the frequency of the read clock Ack is an integral multiple of the frequency of the 4FS signal as described above, but the frequency of the read enable signal RE in the "H" period will become apparent later, but it is time-divided. When the digital audio signal in the multiplexed signal has 4 channels, the frequency F
It is four times S, and therefore the sampling frequency of the time division multiplexed signal output from the memory 7 is 4FS. That is, the sample frequency of one line of the sample data inserted in the horizontal synchronizing signal period of the digital video signal is converted from Vck / 3 to 4FS. Therefore, the time division multiplexed signal output from the memory 7 is the same as the time division multiplexed signal AUD1 having the sampling frequency 4FS and the number of bits (n1 + 2) supplied to the division processing circuit 14 of FIG.

The time division multiplexed signal output from the memory 7 is supplied to the audio data processing circuit 8. The audio data processing circuit 8 determines the number of channels of the digital audio signal in the supplied time division multiplexed signal,
An enable gate signal GP corresponding to the result of this judgment is formed and sent to the memory control circuit 4, the frequency of the read enable signal RE is controlled according to the number of channels of this digital audio signal, and even if this number of channels changes. The digital data of each channel is correctly read from the memory 7.

A time-division multiplexed signal AUD2 ', which will be described later, output from the audio data processing circuit 8 is supplied to an audio channel demultiplexing circuit 9, and digital audio data is supplied to each channel by channel instruction signals CHM and CHL added thereto. Separated, the digital audio signals of the sampling frequency FS and the bit number n1 of each channel are separately obtained. And channel 1
The digital audio signal of (CH1) is output terminal 12
0 to the channel 2 (CH2) digital audio signal from the output terminal 130, the channel 3 (CH3) digital audio signal from the output terminal 140, and the channel 4 (CH4) digital audio signal output terminal 1
50 are output respectively.

Next, a specific example of the memory control circuit 4 and the audio data processing circuit 8 in FIG. 1 will be described with reference to FIG. However, 18 is a channel pulse generation circuit, 19 is an enable signal selection circuit, 20, 21
Are latch circuits, 22-24 are delay circuits, 25-27 are channel comparison circuits, 28 is an enable gate signal generation circuit, 29 is a latch pulse generation circuit, 220, 230, 2
Reference numerals 40, 250, 260 denote input terminals, 270, 280 denote output terminals, and the portions corresponding to those in FIG.

First, the operation of this specific example will be described with reference to FIG. 6 in the case where the number of channels of the received time division multiplexed signal does not change and the number of channels is four.

The FS signal, the 2FS signal, and the 4FS signal shown in FIGS. 6A, 6B, and 6C from the timing generation circuit 3 of FIG. 1 are input from the input terminals 220, 230, and 240, respectively. Similarly, a read clock Ack having an integral multiple frequency of the 4FS signal from the timing generation circuit 3
Are input from the input terminal 250 and are supplied to the channel pulse generation circuit 18, respectively. In the channel pulse generation circuit 18, when the FS signal and the 2FS signal are simultaneously “L”, an “H” edge pulse EN1 (FIG. 6 (d)) that is phase-locked with the rising edge of the 4FS signal is generated. , FS signal is “L”, 2FS signal is “H”, edge pulse EN2 of “H” (FIG. 6E) synchronized in phase with the rising edge of 4FS signal is FS signal “H”, When the 2FS signal is “L”, when the “H” edge pulse EN3 (FIG. 6 (f)) phase-locked with the rising edge of the 4FS signal is “H” at the same time, the FS signal and the 2FS signal are Edge pulse EN4 of "H" phase-synchronized with the rising edge of the 4FS signal (Fig. 6 (g))
Are generated respectively. These edge pulses EN1 and EN
2, EN3 and EN4 are pulses having a pulse width longer than one cycle and shorter than two cycles of the read clock Ack,
The signals are supplied to the enable signal selection circuit 19, respectively.

The enable signal selection circuit 19 receives an edge pulse EN when the enable gate signal GP output from the enable gate signal generation circuit 28 is "L".
One of EN1, EN2, EN3, and EN4 is selected and supplied as "H" read enable signal RE from output terminal 270 to memory 7 (FIG. 1). In the memory 7, as described above, the read clock Ack when the read enable signal RE is "H" causes the number of bits (n
1 + 2) sample data is read.

The enable gate signal generating circuit 2 in the audio data processing circuit 8 is described below.
When the number of channels of the digital audio data signal in the time division multiplexed signal is 4, the enable signal selection circuit 19 outputs edge pulses EN1 and EN.
An enable gate signal GP for selecting all 2, EN3, EN4 in order is generated.

On the other hand, in the audio data processing circuit 8, the number of bits read from the memory 7 (FIG. 1) (n
1 + 2) time division multiplexed signal is supplied from the input terminal 260 to the latch circuit 20, and the channel instruction signals CHM and CHL added to this time division multiplexed signal are supplied to the channel comparison circuits 25, 26 and 27. Along with
The delay circuits 22, 23, 24 sequentially delay the time corresponding to one cycle of the 4FS signal.

The delayed channel designating signals CHM1 and CHL1 delayed by the time corresponding to one cycle of the 4FS signal output from the delay circuit 22 are compared with the input channel designating signals CHM and CHL by the channel comparison circuit 25, and the delayed channel designating signals CHM and CHL are compared. When the signal CHM1 and the input channel designating signal CHM and the delay channel designating signal CHL1 and the input channel designating signal CHL both match, the output becomes "H", and when at least one of them does not match, the comparison output COMP1 which becomes "L" is generated. .. Similarly, the delay channel instruction signals CHM2 and CHL delayed by a time corresponding to two cycles of the 4FS signal output from the delay circuit 23.
2 is compared with the input channel indication signals CHM and CHL in the channel comparison circuit 26, and the delay channel indication signal CHM2 and the input channel indication signal CHM, the delay channel indication signal CHL2 and the input channel indication signal CHL.
Are high when both match, and are low when at least one of them does not match.
2 is generated. The delayed channel designating signals CHM3, CHL3 delayed by the time corresponding to three cycles of the 4FS signal output from the delay circuit 24 are compared with the input channel designating signals CHM, CHL by the channel comparison circuit 27 to obtain the delayed channel designating signal CHM3. When the input channel designating signal CHM, the delay channel designating signal CHL3, and the input channel designating signal CHL match each other, it becomes "H", and when at least one of them does not match, a comparison output COMP3 which becomes "L" is generated.

The channel comparison circuit 25 performs the comparison operation during the period when the FS signal is "L" and the 4FS signal is "H" within the period when the FS signal is "L" and the FS signal is "H". H ”, 2FS signal is“ L ”, and 4FS signal is“ H ”during period comparison operation,
The channel comparison circuit 27 performs the comparison operation during the period in which the 4FS signal is "H" within the period in which both the FS signal and the 2FS signal are "H". Therefore, these channel comparison circuits 2
5, 26 and 27 are sequentially shifted by the period of the 4FS signal to perform the comparison operation.

Therefore, the fact that the comparison output COMP1 of the channel comparison circuit 25 becomes "H" means that the input terminal 2
In the time-division multiplexed signal input from 60, the sample data and the sample data following the sample data are the same channel sample data. Similarly, the comparison output COMP2 of the channel comparison circuit 26
Is "H", which means that in the time division multiplexed signal input from the input terminal 260, the sample data and the sample data placed one by one are the sample data of the same channel, The comparison output COMP3 of the channel comparison circuit 27 becomes “H”, which means that in the time division multiplexed signal input from the input terminal 260, the sample data of the same channel and the sample data of the two samples placed from the sample data of the same channel. It means that. When the number of channels of the digital audio signal in the time division multiplexed signal input from the input terminal 260 is 4, the time corresponding to one cycle of the 4FS signal is equal to the sampling period of digital data in this time division multiplexed signal. From Fig. 6 (h)
, The channel comparison circuits 25, 26,
The comparison outputs COMP1, COMP2, COMP3 of 27 are all "L".

The comparison outputs COMP1, COMP2, COMP3 of the channel comparison circuits 25, 26, 27 are supplied to the enable gate signal generation circuit 28. Rice burger
The output signal generation circuit 28 receives the comparison outputs COMP1, C
When the OMP2 and COMP3 are all "L", an enable gate signal GP which becomes "L" and otherwise becomes "H" is generated and supplied to the enable signal selecting circuit 19 and the latch pulse generating circuit 29. .. In the enable signal selection circuit 19, the edge pulse E output from the channel pulse generation circuit 18 during the "L" period of the enable gate signal GP.
N1, EN2, EN3 and EN4 are selected and supplied as a write enable signal RE from the output terminal 270 to the memory 7 of FIG.

The number of channels of the digital audio signal in the time division multiplexed signal input from the input terminal 260 is 4
In the case of a channel, from the above, the enable gate signal GP output from the enable gate signal generation circuit 28 is always "L", and therefore the edge pulses EN1 and EN from the channel pulse generation circuit 18 are generated.
2, EN3 and EN4 are all sequentially and repeatedly selected to become the read enable signal RE (FIG. 6 (i)), which is supplied from the output terminal 270 to the memory 7 (FIG. 1). The frequency of the read enable signal RE in this case is equal to the frequency of the 4FS signal. Therefore, the original time division multiplexed signal having a sampling frequency of 4FS can be obtained from the memory 7.
This time division multiplexed signal is input from the input terminal 260.

Further, the latch pulse generating circuit 29, for example, a 4FS signal (FIG. 6 (c)) based on the enable gate signal GP from the enable gate signal generating circuit 28.
The same frequency as the edge pulses EN1 and EN
A latch pulse 4FS 'is generated which is delayed by a period of one cycle of the read clock Ack or more than 2, EN3 and EN4. Further, the latch pulse generating circuit 29 receives the enable gate signal GP from the enable gate signal generating circuit 28.
Becomes "H", it becomes "H" at the rising edge of the latch pulse 4FS ', and when this enable gate signal GP becomes "L", a pulse becomes "L" at the falling edge of the latch pulse 4FS'. The latch pulse LP is generated by taking the logical sum of the pulse and the latch pulse 4FS '. When the number of channels of the digital audio signal in the time division multiplexed signal input from the input terminal 260 is 4, the enable gate signal GP from the enable gate signal generation circuit 28 is always "L". As shown in FIG. 6 (j), the latch pulse LP and the latch pulse 4FS 'are equal.

The latch pulse 4FS 'latches the sample data of the time division multiplexed signal input from the input terminal 260 in the latch circuit 20, and the output sample data AUD1' (FIG. 6 (k)) of the latch circuit 20 is latch circuit 30. Is latched by the latch pulse LP. This latch circuit 3
0 time-division multiplexed signal AUD2 '(FIG. 6).
(L)) is supplied from the output terminal 280 to the audio channel division circuit 9 in FIG. When the number of channels of the digital audio signal in the time division multiplex signal input from the input terminal 260 is 4, the time division multiplex signal AUD2 ′ output from the latch circuit 21 is input to the time division multiplex signal from the input terminal 260. The multiplexed signal is delayed by one cycle of the 4FS signal.

As described above, when the maximum number of channels of the received time division multiplexed signal is four and the number of channels does not change, the sample data of each channel should be obtained at the original correct sampling frequency. become.

Next, the case where the number of channels is changed from four to one will be described with reference to FIG. In this case, this one channel is channel 1 (CH1).

When the time division multiplexed signal to be transmitted is composed of only one channel of digital audio signal, in the transmission system shown in FIG. 2, the data selector 13 inputs digital audio of channel 1 (CH1) input from the input terminal 170. Select only signals. Although the sample frequency of this digital audio signal is FS, the sample frequency is made equal to the sample frequency Vck of the digital video signal as described above when it is multiplexed with the digital video signal and transmitted. In the receiving system shown, the sample frequency must be the original FS. The audio data processing circuit 8 makes this possible.

When shifting from the transmission of the 4-channel digital audio signal to the transmission of only the 1-channel digital audio signal of the channel 1 (CH1), the time division multiplexed signal output from the data selector 13 of FIG.
Up to the channel change time, the sample frequency is 4FS and the sampling frequency is 4FS. From the channel change time, only the channel 1 (CH1) digital audio signal is included and the sample frequency is F.
It becomes S. As a result, the sampling frequency of the digital audio signal of each channel becomes FS over the entire time axis. The audio data processing circuit 8 shown in FIG. 5 causes the memory 7 to be read so that the sampling frequency of each channel becomes the same FS even if the channel number of the digital audio signal changes in this way.

In FIGS. 5 and 7, assuming that t is the number of channels of the received digital audio signal of the time division multiplex signal, the time division multiplex signal consists of four channels of digital audio signal until time t. As described in FIG. 6, the memory control circuit 4 is 4F.
A read enable signal RE having a frequency of S is output, and a time division multiplexed signal having a sampling frequency FS and a bit number (n1 + 2) is obtained from the memory 7.

After the time t, the time division multiplexed signal read from the memory 7 is based on only the digital audio signal. Therefore, the sequential sample data of the time division multiplexed signal is CH1-1, CH1-2, CH1-. 3,
...... Then, first, sample data CH from the memory 7
When 1-1 is read, the input channel designating signals CHM, CHL are delayed designating signals CHM1, CHL1,
Since it does not match any of CHM2, CHL2, CHM3, and CHL3, the channel comparison circuits 25, 26, 27
Of the comparison outputs COMP1, COMP2, COMP3 are all zero, and therefore, one cycle of the 4FS signal causes the next read enable signal R from the memory control circuit 4.
E is output and the next sample data CH1-2 is read. When this sample data CH1-2 is read, as shown in FIG. 7D, the channel instruction signals CHM and CHL input from the input terminal 260 indicate channel 1 for the sample data CH1-2, and The delay channel instruction signals CHM1 and CHL1 output from the delay circuit 22 also indicate channel 1 for the sample data CH1-1, as shown in FIG. The comparison output COMP1 becomes "H". However, at this time,
The comparison output COMP2 of the channel comparison circuits 26 and 27,
COMP3 is "L".

As described above, in the delay circuit 22, the FS signal is "L" and the 2FS signal is "H",
While the 4FS signal is "H", the channel indication signal CH
M, CHL and delay channel indication signals CHM1, CHL
1 is compared. Therefore, "H" of this 4FS signal
The comparison output COM of the channel comparison circuit 25 only during the period
P1 will be "H".

The comparison output COMP1 from the channel comparison circuit 25 is supplied to the enable gate signal generation circuit 28, which becomes "H" in phase synchronization with the rising edge of the comparison output COMP1 and the next edge pulse EN1. An enable gate signal GP of "H" for a period of three cycles of the 4FS signal which becomes "L" in phase synchronization with the falling edge is generated. That is, "L" of this enable gate signal GP is
As is clear from comparing FIGS. 6 and 7, the edge pulse E
It is a period of one cycle of the 4FS signal from the rising edge of the 4FS signal including N2 to the next rising edge.

The enable gate signal GP is supplied to the enable signal selection circuit 19 so that the enable signal selection circuit 19 does not select the edge pulse during the "H" period. As a result, the enable signal selection circuit 19 selects only the edge pulse EN2 and supplies it as the read enable signal RE from the output terminal 270 to the memory 7. Read enable signal RE by this edge pulse EN2
Is 4 times the period of the 4FS signal from the read enable signal RE (this is due to the edge pulse EN2) immediately before the enable gate signal GP becomes "H", that is, F
This is delayed by one cycle of the S signal, and at this time, the memory 7 reads the next sample data CH1-3. Note that the sample data CH1-2 is held during this period. When this sample data CH1-3 is read,
Similarly, the channel instruction signals CHM, CHL and the delayed channel instruction signals CHM1, CHL1 match, the comparison output of the channel comparison circuit 25 becomes "H", and the above operation is repeated again.

As a result, thereafter, the read enable signal RE of the frequency FS composed of the edge pulse EN2 is obtained.
Is output from the enable signal selection circuit 19, and as a result, the sample data CH1-1 immediately after the time t is a period of one cycle of the 4FS signal.
Sample data CH1-2, CH1-3, ... Of the time-division multiplexed signal consisting of only the digital audio signal of the above are the frequency of the read enable signal RE, that is, the frequency FS.
Is read from the memory 7.

The enable gate signal GP generated by the enable gate signal generating circuit 28 is also supplied to the latch pulse generating circuit 29. As described above, the enable gate signal generating circuit 28 enables the enable gate signal GP.
Based on the above, for example, with the same frequency as the 4FS signal (FIG. 7 (c)) and with the edge pulses EN1, EN2, EN3, E
When a latch pulse 4FS '(FIG. 7 (i)) which is delayed from N4 by one cycle of the read clock Ack or more is generated and the enable gate signal GP becomes "H", the rising edge of this latch pulse 4FS' is generated. "H"
When the enable gate signal GP becomes "L", a pulse which becomes "L" at the falling edge of the latch pulse 4FS 'is generated, and this pulse and the latch pulse 4FS are generated.
L'and the latch pulse LP (Fig. 7 (j))
To generate. This latch pulse LP is the same as the latch pulse 4FS 'while the enable gate signal GP is "L", but when the enable gate signal GP becomes "H", it is "H" at the rising edge of the first latch pulse 4FS' thereafter. Then, when the enable gate signal GP becomes "L" next, the first latch pulse 4FS 'thereafter.
Becomes "L" at the falling edge of. That is, the latch pulse LP has one rising edge each time the enable gate signal GP becomes “H”, and the rising edge is the first 4FS ′ signal immediately after the enable gate signal GP becomes “H”. It is synchronized with the rising edge of. Therefore, the latch pulse LP is a pulse whose period is equal to the period of the FS signal and whose "H" period is 7/8 times the period of the FS signal.

The latch circuit 20 outputs each sample data of the time division multiplexed signal from the input terminal 260 to the latch pulse 4
The latch circuit 21 latches at FS '(that is, at a frequency of 4FS), and the latch circuit 21 latches the output AU of the latch circuit 20 at the latch pulse LP.
Latch D1 '(FIG. 7 (k)). The output AUD2 '(FIG. 7 (l)) of the latch circuit 21 is supplied from the output terminal 280 to the audio channel separation circuit 9 of FIG.

Here, since the latch pulse 4FS 'is delayed from the read enable signal RE by one cycle or more of the read clock Ack, the sample data read from the memory 7 is certainly latched, and after the time t, The first sample data CH1-1 is the latch circuit 20.
Is latched by the latch circuit 21 after being delayed by one cycle of the 4FS signal, but is not latched by the latch circuit 21 while the enable gate signal GP becomes “H” and the reading of the memory 7 is prohibited. The same sample data 20 held in the latch circuit of the memory 7 is repeatedly latched four times, and after the fourth latch, this sample data is latched by the latch circuit 21.

In the time division multiplexed signal AUD1 'output from the latch circuit 20, immediately after the time t, the sample data C
The time interval between H1-1 and CH1-2 is twice the cycle of the 4FS signal, but in the time-division multiplexed signal AUD2 'output from the latch circuit 21, as shown in FIG. Time point (this is 4 more than the original time t
After one cycle of the FS signal), the sampling cycle of the sample data becomes FS.

As described above, the channel comparison circuit 25 detects the change in the number of channels, and in response thereto, the frequency of the read enable signal RE is immediately changed to the frequency corresponding to the new number of channels. Even if the number of channels of the digital audio signal is changed in the field or frame which is a writing unit, the frequency of the read enable signal RE immediately follows the change and becomes the frequency corresponding to the new number of channels. Therefore, even if the number of channels of the digital audio signal is changed, the sampling frequency of each channel of the time division multiplexed signal AUD2 'output from the latch circuit 21 is always the same as the original frequency. The frequency becomes FS, and there is no excess or deficiency of data when converting the digital audio signals of the respective channels into analog.

Next, the case where the number of channels is changed from four to two will be described with reference to FIG. In this case, the two channels are channel 1 (CH1) and channel 2 (CH2).

When the time-division multiplexed signal to be transmitted is a 2-channel digital audio signal, in the transmission system shown in FIG.
The channel 1 (CH1) digital audio signal input from 0 and the channel 2 (CH2) digital audio signal input from the input terminal 180 are 2F.
The signals are alternately selected in the cycle of the S signal and time division multiplexed. Therefore, the sampling frequency of each of these digital audio signals in the obtained time division multiplexed signal is FS,
When this is multiplexed with a digital video signal and transmitted,
As described above, since the sample frequency is made equal to the sample frequency Vck of the digital video signal, those sample frequencies Vck must be the original frequency FS in the receiving system shown in FIG. The audio data processing circuit 8 also enables this.

Channel 4 (CH1), Channel 2 (CH2) from the 4-channel digital audio signal
When the number of channels shifts to the 2-channel digital audio signal of, the time division multiplexed signal output from the data selector 13 of FIG. 2 is a 4-channel digital audio signal until the channel change time, and the channel is changed from the channel change time. Sample data of digital audio signals of 1 (CH1) and channel 2 (CH2) are alternately arranged, and the sampling frequency of the time division multiplex signal up to the channel change time is 4FS.
However, the sampling frequency after the channel change is set to 2FS. As a result, the sampling frequency of each channel becomes FS over the entire time axis. The audio data processing circuit 8 shown in FIG. 5 causes the memory 7 to be read such that the sampling frequency of each channel becomes the same FS even if the channel number of the digital audio signal changes in this way.

5 and 8, assuming that t is the number of changing channels, the time-division multiplexed signal consists of 4-channel digital audio signals until time t.
As described above, the memory control circuits 4 to 4F
A read enable signal RE having a frequency of S is output, and a time division multiplexed signal having a sampling frequency of 4FS and a bit number (n1 + 2) is obtained.

Here, the sequential sample data of the time division multiplexed signal by the digital audio signals of channel 1 and channel 2 read from the memory 7 after time t are respectively CH1-1, CH1-2, CH1-3 ,. , C
H2-1, CH2-2, CH2-3, ... Sampling data CH1-1 from the memory 7, then CH2-1
Is read, the input channel indication signal CH
M and CHL are delay channel indication signals CHM1 and CHL
1, CHM2, CHL2, CHM3, CHL3 do not match, and the comparison outputs COMP1, COMP2, COMP3 of the channel comparison circuits 25, 26, 27 are all zero, and therefore these sample data CH1-1, C
H2-1 is obtained for each cycle of the 4FS signal.

Next, when the sample data CH1-2 is read, as shown in FIG. 8 (d), the input channel designating signals CHM and CHL indicate channel 1 for the sample data CH1-2 and are output from the delay circuit 22. The delayed channel indication signals CHM1 and CHL1 to be generated are shown in FIG.
As shown in (e), the channel 2 for the sample data CH2-1 is shown, and the delay channel instruction signals CHM2 and CHL2 output from the delay circuit 23 are as shown in FIG.
As shown in (f), channel 1 for sample data CH1-1 is shown. Therefore, the input channel instruction signals CHM and CHL do not match the delay channel instruction signals CHM1 and CHL1 output from the delay circuit 22, and the comparison output COMP1 of the channel comparison circuit 25 becomes "L", but the input channel instruction signal CHM, CHL and the delay channel instruction signal CHM output from the delay circuit 23
2 and CHL2 coincide with each other, and the comparison output COMP2 of the channel comparison circuit 26 becomes "H". In this case, as described above, the channel comparison circuit 26 outputs the FS signal of "H", 2
Since the comparison operation is performed during the period when the FS signal is "L" and the 4FS signal is "H", the channel comparison circuit 2 during this period.
The comparison output COMP2 of 6 becomes "H". During the "H" period of the comparison output COMP2, the comparison output CO in the case of FIG.
It is delayed by one cycle of the 4FS signal from the "H" period of MP1. In this case, the comparison output COMP3 of the channel comparison circuit 27 is also "L".

The comparison output COMP2 from the channel comparison circuit 26 is supplied to the enable gate signal generation circuit 28, becomes "H" in phase synchronization with the rising edge of the comparison output COMP2, and the next edge pulse EN1 is supplied. An enable gate signal GP (FIG. 8 (i)) which becomes "L" in phase with the falling edge is generated. This enable gate signal GP is the "H" level of the comparison output COMP1 when the "H" period of the comparison output COMP2 is as described above.
7 is delayed from the period by one cycle of the 4FS signal and the timing of the falling edge is the same as in the case of FIG.
It becomes equal to the "L" period of the enable gate signal GP shown in (g) extended after one cycle of the 4FS signal. Therefore, the "L" level of this enable gate signal GP
As is apparent from comparison between FIGS. 6 and 8, the period is two cycles of the 4FS signal including the edge pulses EN2 and EN3 and being phase-synchronized with the 4FS signal.

The enable gate signal GP is supplied to the enable signal selection circuit 19 so that the enable signal selection circuit 19 does not select the edge pulse during the "H" period. As a result, the enable signal selection circuit 19 selects only the edge pulses EN2 and EN3 and supplies the read enable signal RE (FIG. 8 (j)) from the output terminal 270 to the memory 7. Since the read enable signal RE in this case consists of the edge pulse EN2 and the edge pulse EN3, the read enable signal RE (FIG. 7 (h)) in FIG. 7 is added with the edge pulse EN3. ..

The sample data CH2-2 is read from the memory 7 by the read enable signal RE by the edge pulse EN2, and then the sample data CH1-3 is read from the memory 7 by the read enable signal RE by the edge pulse EN3. This sample data CH2-2
Is read out from the memory 7, FIG.
Clearly from (e) and (f), the channel comparison circuit 2
Comparison results COMP1, COMP from 5, 26, 27
2, COMP3 are all "L", and the enable gate signal GP output from the enable gate signal generation circuit 28 is held at "L" as it is, but the next sample data CH1-3 is read from the memory 7. 8D, 8E, 8F, the comparison result COMP2 of the channel comparison circuit 26 becomes "H", and the enable gate signal GP output from the enable gate signal generation circuit 28 becomes Again 3 of the period of 4FS signal
It becomes “H” for a double period. Then, the above operation is repeated again.

As described above, the read enable signal RE after the time t becomes a pulse having the same cycle as the FS signal composed of the edge pulses EN2 and EN3 (2 immediately after the time t).
The two read enable signals are also edge pulses EN2, EN
3). The read enable signal RE by the edge pulse EN2 contributes to the reading of the sample data on the channel 1, and the read enable signal RE by the edge pulse EN3 contributes to the reading of the sample data CH1-2 on the channel 1.

As a result, after the time t, first, the sample data CH1-1 on the channel 1 and the sample data CH2-1 on the channel 2 are equal to one cycle of the 4FS signal.
It is read from the memory 7 at a double time interval, but after that,
The sample data of channel 1 and the sample data of channel 2 are alternately read from the memory 7, and the sample data of channel 1 is 3 of the cycle of the 4FS signal.
Double time length, sample data on channel 2 is 4FS
The time length is three times the signal period.

Further, the enable gate signal generation circuit 28
The enable gate signal GP generated in step (4) is also supplied to the latch pulse generation circuit 29, and latch pulses 4FS '(FIG. 8 (k)) and LP (FIG. 8 (l)) are generated as described above.
Is formed. However, as shown in the figure, when the enable gate signal GP becomes "H", the latch pulse LP rises at the first rising edge of the subsequent gate pulse 4FS ', and then the enable gate signal GP changes. When it goes to "L", it falls at the first trailing edge of the subsequent gate pulse 4FS ', so that "H" period is 4
It is 2.5 times the cycle of the FS signal, and the "H" pulse occurs at the same cycle as the FS signal. Then, during the “H” pulse, “H” having the same phase as the 4FS ′ signal
There will be a pulse of.

Each sample data read from the memory 7 by the latch pulse 4FS 'and input from the input terminal 260 is latched by the latch circuit 20, and the output time division multiplexed signal AUD1' (FIG. 8 (m ))
Is latched in the latch circuit 21 by the latch pulse LP. The output of the latch circuit 21 is a time division multiplexed signal AU.
D2 ′ (FIG. 8 (n)) is supplied to the audio channel separation circuit 9 of FIG. 1 via the output terminal 280.

In the time division multiplex signal AUD1 ', as shown in FIG.
As is clear from (m), the sample data in channel 1 and the sample data in channel 2 are alternately arranged from the time t when the number of channels is changed, but the sample data CH1 in channel 1 immediately after the time t. -1, C
The time interval of H1-2 is twice the cycle of the 4FS signal, not the cycle of the FS signal. On the other hand, in the time division multiplexed signal AUD2 ′, as is apparent from FIG. 8 (n), the sample data in the channel 1 and the sample data in the channel 2 are alternately arranged from the time when the number of channels is changed, Sample data on channel 1 is 4F
The time length is 1 time the cycle of the S signal, and the sample data on the channel 2 has the time length 3 times the cycle of the 4FS signal. As a result, the sampling frequency of these channels becomes equal to the original sampling frequency FS, and the sampling frequency of the time division multiplexed signal AUD2 ′ (FIG. 8 (n)) is 2
It is equivalent to FS and equivalent to the time division signal AUD having the number of bits (n1 + 2) in FIG.

Next, the case where the number of channels is changed from four to three will be described with reference to FIG. In this case, the two channels are channel 1 (CH1), channel 2 (CH2), and channel 3 (CH3).

When the time-division multiplexed signal to be transmitted consists of 3-channel digital audio signals, in the transmission system shown in FIG.
The channel 1 (CH1) digital audio signal input from 0, the channel 2 (CH2) digital audio signal input from the input terminal 180, and the channel 3 (CH3) digital audio signal input from the input terminal 190 are input. Time-division multiplexing is performed by sequentially and repeatedly selecting for each period of 1/3 of the cycle of the FS signal. Therefore, each of these multiplexed digital audio signals has a sample frequency of FS. However, when multiplexing this digital audio signal and transmitting it, as described above, the sample frequency is equal to the sample frequency Vck of the digital video signal. Therefore, in the receiving system shown in FIG. 1, those sampling frequencies must be the original FS. The audio data processing circuit 8 also enables this.

Here, the sequential sample data of the time division multiplexed signal by the digital audio signals of CH1 and CH2 is the same as that in the case of FIG. 7, and the sequential sample data of the time division multiplexed signal by the digital audio signal of CH3 is changed. CH3-1, CH3-2, CH3-3, ... Now, assuming that t in FIG. 9 is the time when the number of channels is changed, as is clear from the above description, after time t, first, the sample data CH1-1 and channel 2 of channel 1 are first acquired.
Sample data CH2-1 and channel 3 sample data CH3-1 are sequentially stored in the memory 7 in the cycle of the 4FS signal.
Read from the channel comparison circuit 25, 2 during this period.
Comparative outputs COMP1, COMP2, CO from 6, 27
MP3 is all "L". When the next sample data CH1-2 of channel 1 is read from the memory 7, as shown in FIGS. 9D and 9E, the channel comparison circuit 2
The comparison output COMP3 from FIG. 6 (FIG. 9 (g)) becomes "H". In this case, as described above, the channel comparison circuit 2
Since 7 performs the comparison operation during a period in which both the FS signal, the 2FS signal are "H" and the 4FS signal is "H", the comparison output COMP3 of the channel comparison circuit 27 becomes "H" during this period. The "H" period of the comparison output COMP3 is delayed by one cycle of the 4FS signal from the "H" period of the comparison output COMP2 in the case of FIG. In this case,
The comparison outputs COMP1 of the channel comparison circuits 25 and 26,
COMP2 is "L" as shown in FIG. 9 (f).

The comparison output COMP3 from the channel comparison circuit 27 is supplied to the enable gate signal generation circuit 28, becomes "H" in phase synchronization with the rising edge of the comparison output COMP3, and the next edge pulse EN1 is supplied. An enable gate signal GP (FIG. 8 (h)) which becomes "L" in phase synchronization with the falling edge is generated. This enable gate signal GP is the "H" level of the comparison output COMP2 when the "H" period of the comparison output COMP3 is as described above.
8 is delayed from the period by one cycle of the 4FS signal, and the timing of the falling edge is the same as in the case of FIG.
It becomes equal to the "L" period of the enable gate signal GP shown in (i) extended after one cycle of the 4FS signal. Therefore, the "L" level of this enable gate signal GP
As is clear from comparison between FIG. 6 and FIG. 9, this is a period of 3 cycles of this 4FS signal which is phase-synchronized with the 4FS signal including the edge pulses EN2, EN3, EN4.

The enable gate signal GP is supplied to the enable signal selection circuit 19 so that the enable signal selection circuit 19 does not select the edge pulse during the "H" period. As a result, the enable signal selection circuit 19 selects the edge pulses EN2, EN3, EN4 and outputs the read enable signal RE (FIG. 9 (i)) at the output terminal 270.
To the memory 7. Then, from the memory 7, the sample data CH2-2 of the channel 2 is read by the read enable signal RE by the edge pulse EN2, the sample data CH3-2 of the channel 3 is read by the read enable signal RE by the edge pulse EN3, and the edge pulse EN4.
The sample data CH1-3 of the channel 1 are read by the read enable signal RE according to.

These sample data CH2-2, CH3
-2 is read from the memory 7, the comparison results COMP1 from the channel comparison circuits 25, 26 and 27,
COMP2 and COMP3 are all "L", and the enable gate signal GP output from the enable gate signal generation circuit 28 is held at "L" as it is, but the next sample data CH1-3 is read from the memory 7. 9D and 9E, the comparison result COMP3 of the channel comparison circuit 27 becomes "H", and the enable gate signal GP output from the enable gate signal generation circuit 28 is again the 4FS signal. 1 of the cycle
It becomes “H” for a double period. Then, the above operation is repeated again.

As described above, the read enable signal RE
Is composed of the edge pulses EN2, EN3, EN4, and is obtained by adding the edge pulse EN4 to the read enable signal RE (FIG. 8 (j)) in the case of FIG. EN4 is arranged in the cycle of the FS signal.

In this case, when the sample data of the channel 1 is read, the reading from the memory 7 is prohibited only once, so that after the time t, as shown in FIG.
As shown in (d), the time length of the sample data of channels 2 and 3 is the time length of one cycle of the 4FS signal, but only the time length of the sample data of channel 1 is the time length of two cycles of the 4FS signal. Become.

As a result, after time t, first, 4FS
Sample data CH1-1 on channel 1, sample data CH2-1 on channel 2, sample data CH3- on channel 3 at a time interval of one time the signal period.
1, the sample data CH1-2 of channel 1 is read from the memory 7, and the sample data of these channels is repeatedly read in that order, but the enable signal RE does not include an edge pulse.
Only the sample data on channel 1 has a time length twice the cycle of the 4FS signal. That is, the time-division multiplexed signal output from the memory 7 is the sample data on the channel 1 having a time length twice the cycle of the 4FS signal, and the sample data on the channels 2 and 3 each having a time length once the cycle of the 4FS signal. The sample data array of will be repeated.

Further, the enable gate signal generation circuit 28
The enable gate signal GP generated in step (4) is also supplied to the latch pulse generation circuit 29, and as described above, the latch pulse 4FS '(FIG. 9 (j)), LP (FIG. 9).
(K)) is formed. However, this latch pulse LP
Is the enable gate signal G, as shown in FIG.
When P becomes "H", it rises at the first rising edge of the subsequent gate pulse 4FS ', and when the enable gate signal GP becomes "L", the subsequent gate pulse 4FS'.
The period becomes "H" for two cycles of the 4FS signal that falls at the first falling time of "'. Since the "H" period occurs in the cycle of the FS signal, two "H" periods equal to the gate pulse 4FS 'occur between the "H" periods.

Each sample data read from the memory 7 by the latch pulse 4FS 'and inputted from the input terminal 260 is latched by the latch circuit 20, and the output time division multiplexed signal AUD1' (FIG. 9 (l ))
Is latched in the latch circuit 21 by the latch pulse LP. The output of the latch circuit 21 is a time division multiplexed signal AU.
D2 ′ (FIG. 9 (m)) is supplied to the audio channel separation circuit 9 of FIG. 1 via the output terminal 280.

Also in this case, in the time division multiplex signal AUD1 'output from the latch circuit 20, the time interval between the sample data CH1-1 and CH1-2 in the channel 1 is 3 of the cycle of the 4FS signal immediately after the time t. However, in the time division multiplexed signal AUD1 ′ output from the latch circuit 20,
The sampling frequency of the sample data of each channel is equal to the original FS, and the sampling frequency of the time division multiplexed signal AUD2 'is equivalent to 2FS, which is equivalent to the time division signal AUD having the number of bits (n1 + 2) in FIG. Is. Therefore, when the digital audio signal of each channel is converted into an analog signal, excess or deficiency of data does not occur.

Although one embodiment of the present invention has been described above, the present invention is not limited to this embodiment. That is, in the specific example shown in FIG. 5, the falling edge of the enable gate signal GP output from the enable gate signal generation circuit 28 is set to the falling edge of the edge pulse EN1 after channel comparison. Although the phases are synchronized, the falling edge of the enable gate signal GP may be in the period from the falling edge of the edge pulse EN1 after channel comparison to the rising edge of the next edge pulse EN2. It is possible to obtain exactly the same effect as in the embodiment described above.

Further, in the above embodiment, the case where the number of channels of the digital audio signal is set to 4 and changed to 1 channel, 2 channels or 3 channels has been described, but the present invention is not limited to this and, for example, 3 channels are used.
The present invention can be applied even when the digital audio signal of a channel changes to one channel, two channels, or four channels, and in general, it is possible to arbitrarily cope with the change in the number of channels.

Further, in the above embodiment, the signal multiplexed with the digital video signal is the digital audio signal, but the present invention is not limited to this, and any digital data signal can be applied.

Furthermore, in the above embodiment, the reset signal for resetting the address of the memory has the frame period of the digital video signal as a unit, but the present invention is not limited to this, and is generally an integer of the field period of the digital video signal. The reset signal may be formed in a unit of a period equal to twice the period.

Furthermore, in the above embodiment, the time division multiplexed signal is multiplexed during the horizontal synchronizing signal period of the digital video signal, but it may be inserted during another period such as the vertical synchronizing signal period. ..

[0091]

As described above, according to the present invention,
A field of the digital video signal which becomes a writing unit in a memory for time axis conversion of a time division multiplex signal of a desired digital data signal of a predetermined number of channels which is inserted and transmitted during a predetermined period of the digital video signal or Even if the number of channels of the digital data signal is changed during the frame period, the sampling frequency of each channel can be set to the original sampling frequency. Therefore, excess and deficiency of data can be prevented and noise can be prevented. be able to.

[Brief description of drawings]

FIG. 1 is a block diagram showing a receiving system of an embodiment of a digital signal transmission device according to the present invention.

FIG. 2 is a block diagram showing a transmission system of an embodiment of a digital signal transmission device according to the present invention.

FIG. 3 is a timing chart of signals of respective parts for explaining the operation of the transmission system shown in FIG.

4 is a timing chart showing a frame pulse and a line pulse of a digital video signal, a memory reset pulse in the time axis processing circuit in FIG. 2, and a memory reset pulse in FIG.

5 is a block diagram showing a specific example of a memory control circuit and an audio data processing circuit in FIG. 1. FIG.

FIG. 6 is a timing chart showing the operation of the specific example shown in FIG. 5 when the number of channels is not changed.

FIG. 7 is a timing chart showing an operation example of the specific example shown in FIG. 5 when the number of channels is changed.

FIG. 8 is a timing chart showing another operation example of the specific example shown in FIG. 5 when the number of channels is changed.

9 is a timing diagram showing still another operation example of the specific example shown in FIG. 5 when the number of channels is changed.

[Explanation of symbols]

 1 serial / parallel conversion circuit 4 memory control circuit 5 audio / video separation circuit 7 memory 8 audio data processing circuit 9 audio channel separation circuit 11 timing generation circuit 12, 13 data selector circuit 14 divisions Processing circuit 15 Time axis processing circuit 16 Parallel / serial conversion circuit 18 Channel pulse generation circuit 19 Enable signal selection circuit 20, 21 Latch circuit 22-24 Delay circuit 25-27 Channel comparison circuit 28 Enable gate signal generation circuit 29 Latch pulse generation circuit.

Claims (4)

[Claims] 1. A first means for time-division multiplexing different digital data signals of n channels (n ≧ 1) into one continuous digital data stream, and the digital data stream is digital video. The signal is divided for each period of the horizontal or vertical synchronizing signal, the digital data of each division is time-axis compressed into an intermittent time division multiplexed signal, and the intermittent data is inserted into a predetermined area of the horizontal or vertical synchronizing of the digital video signal. Second means for time-axis-multiplexing the time-division multiplexed signal with the digital video signal, and converting the digital video signal with the time-division multiplexed intermittent time-division multiplexed signal into serial data in 1-bit units for transmission. Third means, fourth means for receiving the serial data, and converting the received serial data into parallel data to reconstruct the digital video signal. And a sixth means for separating and extracting the intermittent time division multiplexed signal from the reconstructed digital video signal, sequentially writing, and expanding the time axis to read out as a digital data string, and the memory means. Seventh means for constantly detecting the number n of channels of the digital data signal in the read digital data sequence and setting the read frequency of the memory to a frequency corresponding to the detected number n of channels; The digital data string read from the memory means can be made equivalent to the digital data obtained by the first means even when the number of channels of the digital data signal is changed. A digital signal transmission device characterized by the above. 2. The method according to claim 1, wherein the seventh means is
Let n be the maximum number of channels of the digital signal that can be transmitted.
', And n = n', the sampling cycle of the digital data sequence by the first means is T, and the channel of the digital data read from the sixth means and K times (K times) from this channel. = 1, 2, ..., n'-
1) Eighth means for comparing with the channel of the digital data previously read from the sixth means, K channel before the channel of the digital data read from the sixth means When the channel of the digital data read from the sixth means coincides with, the read operation by the sixth means is performed (n′−
K) ninth means for stopping for a period of T, a channel of the digital data read from the sixth means, and a channel of the digital data read from the sixth means K times before this And when the two coincide with each other, the digital data read from the sixth means is delayed by a period of (n'-K) T.
0 means, and a digital signal transmission device characterized by the above. 3. The sixth means according to claim 1, wherein the cycle of the reset signal for the write address and the read address is L times the field cycle of the digital video signal (L = 1, 2, 3). , ...) is a digital signal transmission device. 4. The digital data signal according to claim 1, 2 or 3, wherein the digital data signal has a number M of bits to which redundant bits are added, and the number of bits of the digital video signal is m (where M> m). ), And
The second means is an eleventh means for dividing the sample data of the digital audio signal having the bit number M into J pieces (where J = 2, 3, ...) Of the sample data having the bit number m. From the eleventh means, the sample data sequence is divided into periods of the horizontal or vertical synchronizing signal of the digital video signal, and the sample data sequence of each division is time-axis compressed to obtain the sample frequency of the digital video signal. Twelfth means for making intermittent time division multiplexed signals of equal sample frequency, and the time axis compressed sample data sequence of each section of the intermittent time division multiplexed signal is at least one of a horizontal or vertical synchronization area of the digital video signal. And a thirteenth means for time-axis multiplexing.