JPH0592686U - Failure detection device - Google Patents

Failure detection device

Info

Publication number
JPH0592686U
JPH0592686U JP4095992U JP4095992U JPH0592686U JP H0592686 U JPH0592686 U JP H0592686U JP 4095992 U JP4095992 U JP 4095992U JP 4095992 U JP4095992 U JP 4095992U JP H0592686 U JPH0592686 U JP H0592686U
Authority
JP
Japan
Prior art keywords
fail
circuit
value
counter
abnormality
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP4095992U
Other languages
Japanese (ja)
Other versions
JP2606324Y2 (en
Inventor
光彦 西本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Koyo Seiko Co Ltd
Original Assignee
Koyo Seiko Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koyo Seiko Co Ltd filed Critical Koyo Seiko Co Ltd
Priority to JP1992040959U priority Critical patent/JP2606324Y2/en
Publication of JPH0592686U publication Critical patent/JPH0592686U/en
Application granted granted Critical
Publication of JP2606324Y2 publication Critical patent/JP2606324Y2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Abstract

(57)【要約】 【目的】 ハードウエアにより故障検出対象装置の複数
の故障を夫々正確に判別可能とする。 【構成】 フェイル条件判定回路1にて予め設定した電
動パワーステアリング装置の操舵補助用のモータの駆動
電流目標値と、モータ電流の検出値とを比較し、検出値
が目標値よりも低いか、又は高いかを検出してモータの
動作状態を判定し、夫々の動作状態に応じて発振器3か
ら異なる周波数のクロックを発振させてカウンタ4に入
力させる一方、フェイル検出回路2にて予め設定した目
標値と検出値とに基づきフェイル発生の有無を判別し、
フェイル発生時にフェイル検出信号をカウンタ4に出力
して計数を開始させ、カウンタ4が所定個数のクロック
を計数すると異常確定信号を出力させることとする。
(57) [Abstract] [Purpose] It is possible to accurately determine a plurality of failures in a failure detection target device by hardware. A drive current target value of a motor for assisting steering of an electric power steering device set in advance by a fail condition determination circuit 1 and a detected value of a motor current are compared to determine whether the detected value is lower than the target value. Alternatively, the operating state of the motor is determined by detecting whether or not it is high, and a clock of a different frequency is oscillated from the oscillator 3 according to each operating state and input to the counter 4, while the target set in advance by the fail detection circuit 2 is set. Based on the value and the detected value to determine the presence or absence of fail,
When a failure occurs, a failure detection signal is output to the counter 4 to start counting, and when the counter 4 counts a predetermined number of clocks, an abnormality confirmation signal is output.

Description

【考案の詳細な説明】[Detailed description of the device]

【0001】[0001]

【産業上の利用分野】[Industrial applications]

本考案はハードウエアで電動パワーステアリング装置等における各種故障の検 出を可能とした故障検出装置に関する。 The present invention relates to a failure detection device capable of detecting various failures in an electric power steering device or the like with hardware.

【0002】[0002]

【従来の技術】[Prior Art]

電動パワーステアリング装置において、操舵補助力を出力するモータの駆動電 流の検出値と目標値との比較に基づいて故障を検出する場合、予め所定の時定数 を定めておき、検出値が目標値から外れた状態が時定数以上となったとき、故障 発生と判定してモータの停止、クラッチ解除等の措置が採られるようになってい る。 In an electric power steering system, when a failure is detected based on the comparison between the detected value of the drive current of the motor that outputs the steering assist force and the target value, a predetermined time constant is set in advance and the detected value is the target value. When the condition that is out of the range exceeds the time constant, it is determined that a failure has occurred and measures such as stopping the motor and releasing the clutch are taken.

【0003】[0003]

【考案が解決しようとする課題】[Problems to be solved by the device]

ところが上述した如き従来の装置にあっては、例えば急操舵時には操舵補助用 のモータに逆起電力が生じ、モータ駆動電流が流れ難くなるため、検出値が急操 舵中に目標値よりも低くなるが、このような現象を故障発生と誤認しないために は時定数を長く、例えば0.5sec程度とする必要がある。 However, in the conventional device as described above, a counter electromotive force is generated in the motor for assisting steering during sudden steering, which makes it difficult for the motor drive current to flow, so the detected value is lower than the target value during rapid steering. However, in order to prevent this phenomenon from being mistaken for failure, it is necessary to set the time constant long, for example, about 0.5 sec.

【0004】 しかし、一方検出値が目標値を越える過大状態となった場合には、安全性確保 の面から、例えば0.03sec 程度で即時に故障発生と判断する必要があるため、前 述した如き一種類の時定数のみを設定する構成では正確な故障検出が難しいとい う問題があった。 本考案はかかる事情に鑑みなされたものであって、その目的とするところはハ ードウエアにて故障の種類に応じて異常確定時間を変更し、複数の故障を正確に 検出し得るようにした故障検出装置を提供するにある。On the other hand, if the detected value exceeds the target value and becomes excessive, it is necessary to immediately determine that a failure has occurred, for example, in about 0.03 seconds from the viewpoint of ensuring safety. Therefore, as described above. There is a problem that it is difficult to accurately detect faults with a configuration that sets only one type of time constant. The present invention has been made in view of such circumstances, and the purpose thereof is to change the abnormality determination time in hardware according to the type of failure so that a plurality of failures can be accurately detected. It is to provide a detection device.

【0005】[0005]

【課題を解決するための手段】[Means for Solving the Problems]

本考案に係る故障検出装置は、異常検出対象装置の動作状態を検出する回路と 、該検出回路で検出した動作状態に応じて前記異常検出対象装置の異常を確定す る時間を変更する回路と、前記検出回路で検出した動作状態が前記異常確定時間 変更回路で設定された異常確定時間に達したとき異常確定信号を出力する手段と を具備することを特徴とする。 A failure detection device according to the present invention comprises a circuit for detecting an operating state of an abnormality detection target device, and a circuit for changing a time for establishing an abnormality of the abnormality detection target device according to an operation state detected by the detection circuit. Means for outputting an abnormality confirmation signal when the operation state detected by the detection circuit reaches the abnormality determination time set by the abnormality determination time changing circuit.

【0006】[0006]

【作用】[Action]

本考案にあっては、異常確定時間変更手段によって異常検出対象装置の動作状 況に応じた異常確定時間の設定が可能となり、各種の異常夫々を正確に検出し得 る。 According to the present invention, the abnormality confirmation time changing means can set the abnormality confirmation time according to the operation state of the abnormality detection target device, and each of the various abnormalities can be accurately detected.

【0007】[0007]

【実施例】【Example】

以下本考案をその実施例を示す図面に基づき具体的に説明する。図1は本考案 に係る故障検出装置のブロック図であり、図中1はフェイル条件判定回路、2は フェイル検出回路を示している。フェイル条件判定回路1は予め設定入力されて いる目標値、例えば電動パワーステアリング装置の故障を検出する場合には操舵 補助用のモータの駆動電流目標値と逐次検出した検出値とを比較し、例えば検出 値が目標値よりも低い場合にはフェイル条件B、検出値が目標値よりも高い場合 にはフェイル条件Aと判定し、夫々に対応した信号を発振器3へ出力するように なっている。発振器3はフェイル条件判定回路1から入力された各信号に応じて 周波数の異なるクロックをカウンタ4に出力するよう構成されている。 Hereinafter, the present invention will be specifically described with reference to the drawings showing an embodiment thereof. FIG. 1 is a block diagram of a failure detecting device according to the present invention, in which 1 is a fail condition judging circuit and 2 is a fail detecting circuit. The fail condition determination circuit 1 compares a target value that is preset and input, for example, when detecting a failure of the electric power steering device, with a target value of a drive current of a motor for steering assist and a detected value that is sequentially detected. If the detected value is lower than the target value, the fail condition B is determined, and if the detected value is higher than the target value, the fail condition A is determined, and the corresponding signals are output to the oscillator 3. The oscillator 3 is configured to output a clock having a different frequency to the counter 4 according to each signal input from the fail condition determination circuit 1.

【0008】 一方フェイル検出回路2には同様の目標値と検出値とが入力されるようになっ ており、入力された目標値と検出値とを比較し、検出値が目標値よりも所定値以 上低い場合、又は検出値が目標値よりも所定値以上高い場合には夫々フェイル発 生と判断し、カウンタ4に計数を開始させるべく信号を出力するようになってい る。カウンタ4はフェイル検出回路2からの検出信号に基づいてクロックのカウ ントを開始し、予め定めた個数n個だけカウントすると異常確定信号を出力する ようになっている。On the other hand, the same target value and detection value are input to the fail detection circuit 2, and the input target value and detection value are compared, and the detection value is a predetermined value higher than the target value. When it is lower than the above value, or when the detected value is higher than the target value by a predetermined value or more, it is determined that the failure has occurred, and a signal is output to the counter 4 to start counting. The counter 4 starts counting the clock based on the detection signal from the fail detection circuit 2, and outputs an abnormality confirmation signal when counting a predetermined number n.

【0009】 図2,図3は発振器3から発振されるクロック、フェイル条件判定回路1,フ ェイル検出回路2及びカウンタ4の各出力信号波形を示す波形図であり、図2は フェイル条件判定回路1がフェイル条件Bと判定した場合を、また図3は同じく フェイル条件判定回路1がフェイル条件Aと判定した場合を夫々示している。2 and 3 are waveform diagrams showing respective output signal waveforms of the clock oscillated from the oscillator 3, the fail condition judging circuit 1, the fail detecting circuit 2 and the counter 4, and FIG. 2 is a fail condition judging circuit. 1 shows the case where the fail condition B is judged, and FIG. 3 shows the case where the fail condition judgment circuit 1 judges the fail condition A as well.

【0010】 図2(c) に示す如くフェイル条件判定回路1がフェイル条件Bと判定してフェ イル条件判定信号Bを出力している場合には、図2(a) に示す如く発振器3から 周期T1 のクロックが発振され、カウンタ4へ入力される。フェイル検出回路2 が図2(b) に示す如くフェイルを検出するとフェイル検出信号をカウンタ4へ出 力し、カウンタ4 が計数を開始する。カウンタ4がクロックをn個計数すると、 換言すればフェイル検出回路2がフェイル発生を検出してからT1 ×n時間後に カウンタ4から図2(d) に示す如く異常確定信号が出力される。これによって操 舵補助用のモータの停止等の措置が採られることとなる。When the fail condition judging circuit 1 judges that the fail condition is B and outputs the fail condition judging signal B as shown in FIG. 2 (c), the oscillator 3 is output from the oscillator 3 as shown in FIG. 2 (a). A clock having a cycle T 1 is oscillated and input to the counter 4. When the fail detection circuit 2 detects a fail as shown in FIG. 2 (b), it outputs a fail detection signal to the counter 4, and the counter 4 starts counting. When the counter 4 counts n clocks, in other words, the counter 4 outputs an abnormality confirmation signal as shown in FIG. 2 (d) T 1 × n time after the fail detection circuit 2 detects the occurrence of the failure. As a result, measures such as stopping the motor for steering assistance will be taken.

【0011】 一方フェイル条件判定回路1が図3(c) に示す如くフェイル条件Bと判定した 状態から変化してフェイル条件Aと判定したときは、フェイル条件判定信号Bが Aに切り換わり、図3(a) に示す如く発振器3は周期T1 より短い周期T2 のク ロックに周波数を切り換えて発振する。またフェイル検出回路2が図3(b) に示 す如くフェイル発生を検出すると、カウンタ4がクロックの計数を開始し、クロ ックを同じくn個数えると、換言すればフェイル検出回路2がフェイル発生を検 出してからT2 ×n時間後に図3(d) に示す如くカウンタから異常確定信号が出 力され、同様に操舵補助用のモータの停止等の措置が採られる。つまり、検出値 が目標値よりも高いフェイル条件Aの場合は、検出値が目標値よりも低いフェイ ル条件Bの場合よりも異常確定時間が短くなるようになされている。On the other hand, when the fail condition judging circuit 1 changes from the condition judged as the fail condition B as shown in FIG. 3 (c) to the fail condition A, the fail condition judging signal B is switched to A, As shown in 3 (a), the oscillator 3 oscillates by switching the frequency to the clock of the period T 2 shorter than the period T 1 . When the fail detection circuit 2 detects the occurrence of a failure as shown in FIG. 3 (b), the counter 4 starts counting clocks and counts the same number of clocks, that is, the fail detection circuit 2 fails. An abnormality confirmation signal is output from the counter as shown in FIG. 3 (d) after T 2 × n hours from the occurrence detection, and similarly, measures such as stopping the motor for steering assist are taken. That is, in the fail condition A in which the detected value is higher than the target value, the abnormality determination time is shorter than in the fail condition B in which the detected value is lower than the target value.

【0012】 なお、上述の実施例においてはフェイル条件判定回路1は検出値が目標値より も低いか又は高いかによって異常検出対象装置の動作状態を2つに弁別して発振 器3から2種類のクロックを出力する場合について説明したが、何らこれに限ら ず、異常検出対象装置の動作状態夫々に応じて2以上のクロックを発振器3から 出力するようにしてもよいことは勿論である。In the above-described embodiment, the fail condition determination circuit 1 discriminates the operating state of the abnormality detection target device into two depending on whether the detected value is lower or higher than the target value, and selects two types from the oscillator 3. Although the case where the clock is output has been described, the present invention is not limited to this, and it goes without saying that two or more clocks may be output from the oscillator 3 in accordance with the respective operating states of the abnormality detection target device.

【0013】[0013]

【考案の効果】[Effect of the device]

以上の如く本考案装置にあっては異常確定時間変更回路によって、異常検出対 象装置の動作状態に応じた異常確定時間の設定が可能となり、各種の異常夫々を 正確に判定することが出来る等、本考案は優れた効果を奏するものである。 As described above, in the device of the present invention, it is possible to set the abnormality confirmation time according to the operating state of the abnormality detection target device by the abnormality confirmation time changing circuit, and it is possible to accurately determine each type of abnormality. The present invention has excellent effects.

【図面の簡単な説明】[Brief description of drawings]

【図1】本考案に係る故障検出装置のブロック図であ
る。
FIG. 1 is a block diagram of a failure detection device according to the present invention.

【図2】フェイル条件判定回路がフェイル条件Bと判定
したときの各信号の波形図である。
FIG. 2 is a waveform diagram of each signal when the fail condition determination circuit determines that the fail condition is B.

【図3】フェイル条件判定回路がフェイル条件Aと判定
したときの各信号の波形図である。
FIG. 3 is a waveform diagram of each signal when the fail condition determination circuit determines the fail condition A.

【符号の説明】[Explanation of symbols]

1 フェイル条件判定回路 2 フェイル検出回路 3 発振器 4 カウンタ 1 Fail condition judgment circuit 2 Fail detection circuit 3 Oscillator 4 Counter

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 【請求項1】 異常検出対象装置の動作状態を検出する
回路と、該検出回路で検出した動作状態に応じて前記異
常検出対象装置の異常を確定する時間を変更する回路
と、前記検出回路で検出した動作状態が前記異常確定時
間変更回路で設定された異常確定時間に達したとき異常
確定信号を出力する手段とを具備することを特徴とする
故障検出装置。
1. A circuit for detecting an operating state of an abnormality detection target device, a circuit for changing a time for determining an abnormality of the abnormality detection target device according to an operating state detected by the detection circuit, and the detection circuit. A failure detection device, comprising: means for outputting an abnormality confirmation signal when the detected operation state reaches the abnormality confirmation time set by the abnormality confirmation time changing circuit.
JP1992040959U 1992-05-22 1992-05-22 Failure detection device Expired - Fee Related JP2606324Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1992040959U JP2606324Y2 (en) 1992-05-22 1992-05-22 Failure detection device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1992040959U JP2606324Y2 (en) 1992-05-22 1992-05-22 Failure detection device

Publications (2)

Publication Number Publication Date
JPH0592686U true JPH0592686U (en) 1993-12-17
JP2606324Y2 JP2606324Y2 (en) 2000-10-23

Family

ID=12595028

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1992040959U Expired - Fee Related JP2606324Y2 (en) 1992-05-22 1992-05-22 Failure detection device

Country Status (1)

Country Link
JP (1) JP2606324Y2 (en)

Also Published As

Publication number Publication date
JP2606324Y2 (en) 2000-10-23

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