JPH0593761A - Semiconductor integrated circuit - Google Patents

Abstract

(57) [Abstract] [Purpose] To provide a semiconductor integrated circuit in which the controllability of a circuit block can be improved with only one test terminal. A selecting means for selectively transmitting a non-inverted signal and an inverted signal of an output signal of a preceding circuit block 1 between one test terminal 3 and two circuit blocks 1 and 2 to a succeeding circuit block 2. 4 is provided. When it is desired to invert the input signal of the circuit block 2 for testing the circuit block 2, it can be realized by setting the test terminal 3 to the low level.
Further, in order to restore the input signal of the circuit block 2 to the original, the test terminal 3 may be set to the high level. That is, it is possible to easily control the input signal of the circuit block 2 in the subsequent stage without operating the circuit block 1 in the previous stage.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit composed of a plurality of circuit blocks.

[0002]

2. Description of the Related Art In the prior art, in order to improve the controllability of a certain circuit block, a test terminal 8, a test signal input terminal 9 and the test signal are provided between the circuit block and the preceding circuit block as shown in FIG. The selection circuit 7 configured to select the input signal from the test signal input terminal 9 and the output signal of the circuit block 5 by the terminal 9 and transmit the selected signal to the circuit block 6.

[0003]

However, in the prior art, it is necessary to provide two test terminals, a test terminal and a test signal input terminal.

Therefore, an object of the present invention is to provide a semiconductor integrated circuit which can improve the controllability of a circuit block with only one test terminal.

[0005]

A semiconductor integrated circuit according to the present invention is a semiconductor integrated circuit composed of a plurality of circuit blocks, wherein one test terminal and a test terminal between two circuit blocks are provided in the preceding stage. It is characterized in that it has a selecting means for selectively transmitting the non-inverted signal and the inverted signal of the output signal of the circuit block to the subsequent circuit block.

[0006]

According to the above configuration of the present invention, the normal signal and the inverted signal of the output signal of the circuit block at the preceding stage can be selectively transmitted to the circuit block at the following stage by the test terminal.

[0007]

FIG. 1 shows an embodiment of a semiconductor integrated circuit of the present invention. Reference numeral 1 is a circuit block, 3 is a test terminal, and 4 is a test terminal 3 for a normal signal and an inverted signal of the output signal of the circuit block 1.
Means for selectively transmitting to the circuit block 2 by
Is a circuit block which receives the output signal of the selection means 4.

When the test terminal 3 is set to the high level, the output signal of the circuit block 1 is transmitted to the circuit block 2 as it is. When the test terminal 3 is set to the low level, the inverted signal of the output signal of the circuit block 1 is transmitted to the circuit block 2. In a normal use state, the test terminal 3 is set to a high level so that the output signal of the circuit block 1 is transmitted to the circuit block 2. When it is desired to invert the input signal of the circuit block 2 for testing the circuit block 2, it can be realized by setting the test terminal 3 to the low level.
Further, in order to restore the input signal of the circuit block 2 to the original, the test terminal 3 may be set to the high level. That is, the input signal of the circuit block 2 can be easily controlled without operating the circuit block 1.

[0009]

As described above, in the semiconductor integrated circuit of the present invention, the normal signal and the inverted signal of the output signal of the preceding circuit block are selectively provided between one test terminal and the two circuit blocks. By providing the selecting means for transmitting to the circuit block in the subsequent stage, the circuit block in the subsequent stage can be controlled without operating the circuit block in the previous stage, and the testability can be improved.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a semiconductor integrated circuit of the present invention.

FIG. 2 is a conventional test circuit configuration diagram.

[Explanation of symbols]

 1 circuit block 2 circuit block 3 test terminal 4 selection means 5 circuit block 6 circuit block 7 selection circuit 8 test terminal 9 test signal input terminal

Claims (1)

[Claims] 1. In a semiconductor integrated circuit composed of a plurality of circuit blocks, one mode switching terminal (hereinafter,
A test terminal) and a selecting means between the two circuit blocks for selectively transmitting the normal signal and the inverted signal of the output signal of the circuit block at the preceding stage to the circuit block at the succeeding stage by the test terminal. Semiconductor integrated circuit.