JPH0593763A - Method and device for testing electronic circuit device - Google Patents

Abstract

(57) [Abstract] [Purpose] To enable testing of one integrated circuit in an electronic circuit device composed of two integrated circuits while the two are connected. [Structure] A three-state buffer is provided at the output terminal of the other integrated circuit, this buffer is set to a high impedance state, and a test signal is applied to the connection line of both circuits to test one integrated circuit. [Effect] It is possible to perform a test by directly applying a test signal to one integrated circuit while both circuits are electrically connected.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method and apparatus for testing an electronic circuit device for in-circuiting one electrically connected semiconductor circuit.

[0002]

2. Description of the Related Art An electronic circuit device includes two integrated circuits A,
In many cases, B is electrically connected. For example, microprocessor and peripheral circuits, gate array and print controller,
There are many equal numbers. In such a device, there is an in-circuit test method for testing one integrated circuit B while electrically connecting both integrated circuits A and B. Conventionally, when the two integrated circuits A and B are connected to each other, the two circuits cannot be electrically separated from each other. Therefore, it is impossible to apply a test signal to the integrated circuit B, which is only the test target, and the other test circuit is not the test target The test signal is applied to the integrated circuit A, and the output of the other integrated circuit A is applied to the one integrated circuit B. That is, in order to test one integrated circuit B, it was necessary to electrically interpose the other integrated circuit A.

[Problems to be Solved by the Invention]

The conventional in-circuit test method is an indirect method in which the other integrated circuit A for which a test is unnecessary is interposed, and the reliability of the test is lacking. Further, the test signal of the integrated circuit B is given from the integrated circuit A, but in order to generate this test signal from the integrated circuit A, the integrated circuit A
It is necessary to devise the input signal to the device, and therefore, as the integrated circuit A becomes more complicated, the devising becomes necessary.

This state is shown in FIG. The integrated circuit A has various functions such as a gate array / LSI / ASIC, and the integrated circuit B is a peripheral circuit (driving circuit such as a printer or CRT). In order to implement the in-circuit test method while electrically connecting both integrated circuits A and B, it is necessary to apply a simulation pattern signal from the in-circuit tester. The figure shows an example in which three simulation pattern signals P ₁ , P ₂ , and P ₃ are respectively applied to different input terminals to output one test signal S. In this way, in order to obtain one test signal S, simulation patterns P ₁ , P ₂ and P ₃ according to the internal configuration of the integrated circuit A are created,
This is applied to separate input terminals.

It is an object of the present invention to apply a test signal directly to the integrated circuit B while the integrated circuits A and B are connected to each other without passing through the integrated circuit A, so that the integrated circuit B can be tested. A method and an apparatus for testing a circuit device are provided.

[0006]

According to the present invention, a test signal is applied from an in-circuit tester to an integrated circuit B by setting an output terminal of the integrated circuit A in an output prohibited state (claim 1).

Further, according to the present invention, a three-state buffer is provided at the output end of the integrated circuit A, and this is controlled to a high impedance state so that a test signal is applied to the integrated circuit B (claim 2).

[0008]

According to the present invention, the integrated circuits A and B can be electrically separated from each other, so that the test can be performed with both circuits connected (claims 1 and 2).

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a diagram showing an embodiment of the test apparatus of the present invention.
The present embodiment is characterized in that the 3-state buffer 10 is provided at the output terminal of the integrated circuit A. 3-state buffer 1
0 means a buffer having the function of forcibly setting the output terminal to the high impedance state by the output enable signal applied to the input terminal 1 in addition to the function of the normal 2-state buffer. The high impedance state causes the integrated circuit A to be in an output prohibited state, that is, a state in which A and B are electrically separated.

At the time of testing, an output enable signal is applied from the input terminal 1 to bring the 3-state buffer 10 into a high impedance state. In this state, the in-circuit tester T is connected to one point on the connection line L. Then, the in-circuit tester T generates a test signal according to the test purpose. This test signal is input only to the integrated circuit B to test the integrated circuit B. The test result is displayed on a CRT or the like in the tester T for evaluation.

According to this embodiment, only the integrated circuit B can be tested while the integrated circuits A and B are electrically connected. At this time, all that is required is the 3-state buffer 10 and the output enable signal,
The advantage is that accurate tests can be performed with only simple changes. The three-state buffer 10 is an example, and the purpose can be achieved by merely providing an electric switch.
Further, the same test can be performed on an electronic circuit device having three or more integrated circuits.

[0012]

According to the present invention, in an electronic circuit device having two integrated circuits, it is possible to directly test only one of the integrated circuits while the two circuits are connected.

[Brief description of drawings]

FIG. 1 is a diagram showing an embodiment of a test apparatus of the present invention.

FIG. 2 is a diagram showing a conventional test apparatus.

[Explanation of symbols]

 A, B Integrated circuit T In-circuit tester L Connection line 10 3-state buffer

Claims (2)

[Claims] 1. An electronic circuit device comprising a first integrated circuit and a second integrated circuit connected to the first integrated circuit via a connecting line, wherein an output terminal of the first integrated circuit is provided. A test method for an electronic circuit device, wherein an output is prohibited, and a test signal of the in-circuit tester is applied to the connection line under this condition to test the second integrated circuit. 2. A first integrated circuit, a second integrated circuit connected to the first integrated circuit via a connection line, and a three-state buffer provided at an output end of the first integrated circuit, In the electronic circuit device, the control means for bringing the buffer into a high impedance state during a test, and the in-circuit tester connected to the connection line in the high impedance state and applying a test signal to the second integrated circuit, A test device for electronic circuit equipment.