JPH0593764A - Inspecting apparatus for logic circuit - Google Patents

Abstract

PURPOSE:To enable the reducing of burden on a hardware for testing by a method wherein a data for testing is stored and read out through a scan pass register to store to collate it with the contents of a writing register. CONSTITUTION:When a clock generator 1 sends out a clock signal 4, a decremental counter 2 performs a computation of -1 per clock. A writing register 5 performs a shifting by one bit each per clock to send out an output signal 11 to a scan pass register 10 of a circuit 8 to be tested. A reading signal 12 of an output of the register 10 is inputted into a reading register 9 sequentially. Therefore. the contents of the register 5 are transmitted to the register 9. When the contents of a counter 2 is down to zero, a detector 3 sends out a stop signal to the generator 1 and the generator 1 stops the operation. As a result. the registers 5, 10 and 9 are also stopped. The contents of the register 9 are sent out to a higher order device through a data bus 6 to collate the contents written into the register 5 thereby checking the propriety of the action of the register 10.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an inspection device for a logic circuit used in an arithmetic unit of a computer, and more particularly to an inspection device for inspecting a part of scan path registers of its constituent elements.

[0002]

2. Description of the Related Art A logic circuit used for an arithmetic unit of a computer is composed of a sequential circuit and a combinational circuit. A conventional inspection device for inspecting a scan path register which constitutes the sequential circuit is , The individual scan path registers that are included in the circuit under test and operate individually during normal operation are connected in series to form a continuous scan path register. A register having a bit string having the same length as the bit string of the register is connected in series to the circuit under test, a specific test pattern is written in the register, and the scan pattern is read out through the continuous scan path register to obtain each scan path register. The normality test of
We analyze the location of obstacles when they occur.

[0003]

The conventional scan path register inspection apparatus for a logic circuit as described above requires a register having a bit string having a continuous length of scan path registers of a circuit under test, and The same length of specific test data is needed to write. In general, the length of continuous scan path registers of a logic circuit differs depending on the type of the logic circuit. Therefore, in the conventional scan path register inspection device for a logic circuit, it is necessary to prepare a register and test data corresponding to each type of the logic circuit, so that a considerable burden is placed on both software and hardware. It has the drawback of being expensive. In addition, since all bits of the continuous scan path register are compared at the time of the test, it is difficult to speed up the test.

[0004]

SUMMARY OF THE INVENTION A logic circuit inspection apparatus according to the present invention includes a clock generator for sending a clock signal and inputting a stop signal to stop the operation, and an arbitrary value for starting the operation. Can be set to a value (-1) for each clock of the clock signal from the clock generator
A subtraction counter for performing the subtraction, a detector that detects when the content of the subtraction counter becomes "0" and sends the stop signal to the clock generator, and stores test data in advance. A write register that shifts bit by bit by the clock signal and sends the output signal to the scan path register of the circuit under test, and the test data through the scan path register of the circuit under test. And a read register for reading and storing the clock signal and sending it to the upper device when the sending of the clock signal is stopped, and an input setting circuit for setting the scan path register of the circuit under test to the test mode.

[0005]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention.

In FIG. 1, the input setting circuit 7 includes individual flip-flops which constitute each scan path register included in the circuit under test 8 which operates individually in the normal operation (normal mode). It is a circuit for setting the scan path register in the test mode by connecting in series to form a continuous scan path register. The circuit under test 8 has a scan path register 10 therein, and sets the scan path register 10 to the test mode in response to a command from the input setting circuit 7.

The write register 5 usually has a length of about 16 to 32 bits, and test data is written in advance via the data bus 6. The subtraction counter 2 is set with a numerical value obtained by adding the length of the scan path register 10 and the length of the write register 5 of the circuit under test 8, and subtracts by the clock signal 4 from the clock generator 1. In the detector 3, the content of the subtraction counter 2 is "0".
When that happens, it is detected and a stop signal 10 is sent to the clock generator 1. The read register 9 reads the test data of the write register 5 via the scan path register 10 of the circuit under test 8 and temporarily stores it.

When the clock generator 1 starts its operation, the logic circuit inspecting apparatus having the above-mentioned configuration operates on the clock signal 4 to the subtraction counter 2, the write register 5, the scan path register 10 and the read register 9.
Is sent. The subtraction counter 2 is 1 of the clock signal 4.
(-1) is subtracted for each clock. Write register 5
Shifts the output signal 11 by 1 bit for each clock of the clock signal 4 and outputs the output signal 11 to the scan path register 1
Send to 0. Since the output terminal of the scan path register 10 is connected to the input terminal of the read register 9, the read signal 12 output from the scan path register 10 is sequentially input to the read register 9. Therefore, the contents of the write register 5 are transmitted to the read register 9 via the scan path register 10.

When the content of the subtraction counter 2 becomes "0",
The detector 3 operates and sends a stop signal 13 to the clock generator 1. As a result, the operation of the clock generator 1 is stopped, and accordingly, the operations of the write register 5, the scan path register 10 and the read register 9 are also stopped. At this point, all the contents of the write register 5 have been transferred to the read register 9. Therefore, it is checked whether the operation of the scan path register 10 is normal by sending the contents of the read register 9 to the host device via the data bus 6 and collating the contents with the contents written in the write register 5 there. ..

By preparing a plurality of types of test data to be written in the write register 5 and sequentially executing them, it is possible to check the dependence of the operation of the scan path register 10 on the pattern of the test data.

[0012]

As described above, the inspection apparatus for a logic circuit according to the present invention stores the test data in the write register, and reads it out through the scan path register of the circuit under test. The test hardware and the software for creating the test data are stored in the register, and when the test data is read, the data is collated with the contents written in the write register. There is an effect that the burden of can be reduced. There is also an effect that the test can be speeded up.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

[Explanation of symbols]

 1 clock generator 2 subtraction counter 3 detector 4 clock signal 5 write register 6 data bus 7 input setting circuit 8 circuit under test 9 read register 10 scan path register 11 output signal 12 read signal 13 stop signal

Claims (2)

[Claims] 1. A clock generator for transmitting a clock signal and inputting a stop signal to stop the operation, and a value at the time of starting the operation can be set to an arbitrary value. A subtraction counter that subtracts (-1) for each clock of the clock signal, and when the content of the subtraction counter becomes "0", it is detected and the stop signal is sent to the clock generator. A detector for storing the test data in advance, a write register for storing the test data in advance, shifting the output bit by bit by the clock signal, and transmitting the output signal to the scan path register of the circuit under test, and the test data. A read register for reading and storing via the scan path register of the circuit under test and sending it to the upper device when the sending of the clock signal is stopped. And a logic circuit inspecting device. 2. A clock generator for sending a clock signal and inputting a stop signal to stop the operation, and a value when starting the operation can be set to an arbitrary value. A subtraction counter that subtracts (-1) for each clock of the clock signal, and when the content of the subtraction counter becomes "0", it is detected and the stop signal is sent to the clock generator. A detector for storing the test data in advance, a write register for storing the test data in advance, shifting the output bit by bit by the clock signal, and transmitting the output signal to the scan path register of the circuit under test, and the test data. A read register for reading and storing via the scan path register of the circuit under test and sending it to the upper device when the sending of the clock signal is stopped. And an input setting circuit that sets the scan path register of the circuit under test to a test mode.