JPH0594328A - Debugger and emulator - Google Patents

Abstract

PURPOSE:To provide a debugger which can monitor the execution condition of other microprocessor through a shared bus without providing a special exclusive-use circuit in plural microprocessor systems. CONSTITUTION:An address bus ABUS and a data bus DBUS interfaced with a target system are shared with a microprocessor EMPU for emulation to substitute-control the target system and a control processor SMPU for emulation control and to the same bus, a break circuit 7, etc., are linked. A control processor has an input output combination port PA11-0/A19-8 connected directly to the bus and an output port to output the input from a port and when a microprocessor for emulation acquires a bus right and performs the emulation, the information of the address bus is fetched from the input output combination port, and the fetched information can be monitored through the output port at the external part.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to miniaturization of hardware in a debug device in which resources on a system sharing a bus among a plurality of microprocessors are used, and a technique effective when applied to an emulator, for example. Regarding

[0002]

2. Description of the Related Art Emulators are sometimes used in the development of microprocessor application equipment. The emulator has a debug target microprocessor or a microprocessor with the same function as the debug target. This microprocessor controls the user system (target system) while executing and stopping the user program, enabling hardware and software debugging. It is something to do.

Generally, an emulator has a microprocessor for controlling the emulator in addition to a microprocessor for executing emulation (emulation microprocessor). During execution of the emulation, a control microprocessor (control processor) is provided. ) Monitors the execution status of the emulation microprocessor. For example, the information of the address bus and the information of the data bus during the execution of emulation can be fetched and displayed on the console in real time to enable monitoring. Incidentally, as an example of a document describing such a technique, there are pages 78 to 82 in "All About Microcomputer Development" 1989.6.20 by Denpa Shimbun.

The present inventor intends to downsize the emulator by commonly connecting the emulation microprocessor and the control processor to a bus connected to the target system and connecting a trace circuit and a break circuit to the bus. investigated. At this time, the control processor sets a break condition in the break circuit and a trace start address in the trace circuit to set conditions for emulation. Since the emulation microprocessor and the control processor share a bus, it is necessary to interpose a selector or a buffer between both microprocessors and the bus to control the bus right. To enable real-time monitoring of bus information during emulation, connect the bus to the data input pin of the control processor via a buffer or latch when the emulation microprocessor has acquired the bus right. , The buffer or latch must be readable as a register on the external memory space of the control processor.

[0005]

However, even if the control processor and the emulation microprocessor share the bus, various buffer circuits and latch circuits are required for bus right control and real-time monitoring of emulation. Then, the present inventor has found that the circuit scale of the emulator cannot be sufficiently achieved by those circuits. In particular, as microprocessors become more highly integrated, the circuit scale for emulation of microprocessor-applied systems is inevitably increasing, and measures to reduce the size of these circuits are needed to improve the usability of emulators. is necessary.

An object of the present invention is to provide a multi-microprocessor system without providing a special dedicated circuit.
It is an object of the present invention to provide a debug device capable of monitoring the execution states of other microprocessors via a shared bus. Another object of the present invention is to achieve miniaturization of an emulator in which the emulation microprocessor and the control processor share a bus.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0008]

The outline of a typical one of the inventions disclosed in the present application will be briefly described as follows.

That is, in a system in which a plurality of microprocessors share a bus, at least one of the microprocessors has an I / O port and an output port for outputting an input from the port. An output port is directly coupled to the bus, the bus information when another microprocessor has the bus right is fetched from the I / O port, and the fetched information can be externally monitored via the output port. Is.

In the microprocessor having the I / O port, the I / O port is used as a bus signal output port in response to the acquisition of the bus right, and the I / O port is used as the bus signal input port in response to the abandonment of the bus right. Has an operation mode of

When the above system is applied to an emulator, the bus interfaced with the target system is shared by an emulation microprocessor for acting control of the target system and a control microprocessor for emulation control. A trace circuit and a break circuit are coupled to the bus. The control microprocessor has an I / O port directly connected to the bus and an output port for outputting an input from the port, and the bus information when the emulation microprocessor has a bus right. Is taken in from the I / O port, and the taken information can be externally monitored via the output port.

[0012]

According to the above means, the I / O port directly connected to the bus functions as an output port, so that the microprocessor having the I / O port acquires the bus right and performs the bus access. When the microprocessor relinquishes the bus right, the I / O port is made to function as an input port so that the bus access information from other microprocessors is taken in from the I / O port functioning as the input port. Is output to the outside from another output port. This allows bus information to be monitored in real time. In this way, by directly connecting the I / O port to the shared bus of multiple microprocessors and fetching the bus information to be monitored by selecting the function of the I / O port, the state of the shared bus can be monitored without requiring a special circuit. To achieve downsizing of the system.

[0013]

1 is a block diagram of an emulator 1 according to an embodiment of the present invention. In the figure, EMPU is an emulation microprocessor for acting on behalf of a target system (not shown) connected via the user interface circuit 10. In the figure, SMPU is a control processor for controlling the emulator. Both microprocessor SMP
U and EMPU are address bus ABUS and data bus D
Share the BUS. Control processor SMPU
Are equipped with peripheral circuits such as ROM, RAM, and communication interface, and address bus ABUS
And a port connected to the data bus DBUS and an input / output port terminal. According to this embodiment, among the addresses of the control processor SMPU, the upper addresses A19 to A8 are the control processor SM.
It is assigned to an I / O port that can also be used as an I / O port by register setting in the PU. In FIG. 1, this port is shown as PA11-0 / A19-8. Therefore, the port PA11-0 / A19-8 of the control processor SMPU outputs an address to the address bus ABUS and rewrites the control register of the port to generate the address bus ABUS.
The contents of can be captured. When the emulation microprocessor EMPU has acquired the bus right and is performing emulation, the control processor S
The address information taken in by the MPU from the port PA11-0 / A19-8 is sent to the display device of the system development device 2 via the communication interface and the output port, and the information of the address bus at the time of emulation is displayed in real time on the display device. Enable monitoring while displaying.

In order to reduce the size of the emulator, the address bus ABUS and the data bus DBUS are shared by the microprocessors SMPU and EMPU. Address A1 of control processor SMPU
9 to A8 are directly coupled to corresponding signal lines of address bus ABUS, and addresses A7 to A0 are coupled to corresponding signal lines of address bus ABUS via buffer 3. Address A1 of the emulation microprocessor EMPU
9 to A0 are connected to the address bus ABUS via the buffer 4. The data bus DBUS is a data bus DBU for both microprocessors SMPU and EMPU.
It is directly connected to S.

An emulation control circuit 5, an emulation RAM 6, a break circuit 7, a trace circuit 8, a RAM 9 and a user interface circuit 10 are connected to the address bus ABUS and the data bus DBUS as circuits unique to the emulator. The break circuit 7 monitors the states of the data bus DBUS and the address bus ABUS, and breaks the emulation operation when the state reaches the preset state. The trace circuit 8 has a data bus DBUS and an address bus AB.
Information such as US is sequentially traced and stored for each bus cycle. The emulation RAM 6 is a memory for substituting for a data memory or a program memory that should be included in a target system (not shown). RA
M9 is used by the control processor SMPU as a primary storage area for other data. The emulation control circuit 5 monitors the emulation state and exchanges control information and the like with the control processor SMPU.

Address bus ABUS and data bus DB
Bus right to US is control processor SMP
U controls the switching to the outside depending on the state of the port PC0 terminal. That is, the port PC0 terminal is pulled up and the port terminal PC0
The buffer 3 receives a signal determined according to the output state of the buffer, and the buffer 4 receives the inverted signal. This allows
One of the buffers 3 and 4 is activated according to the output state of the port terminal PC0.

In the control processor SMPU, the port PC1 terminal functions as a reset terminal and is pulled up. The emulation microprocessor EMPU receives the output of the NOR gate 11 which receives the pull-up signal and the external reset signal RES as two reset terminals / RES.

FIG. 2 shows the control processor SMPU.
An example block diagram is shown. The microprocessor SMPU shown in the figure is formed on one semiconductor substrate such as a silicon substrate by a known semiconductor integrated circuit manufacturing technique. The microprocessor SMPU is not particularly limited, but a central processing unit (CPU) that controls the entire control.
20, a wait controller 2 that controls insertion of wait states according to a wait request signal from the outside
1. Data primary storage area or the central processing unit 2
RAM 22 used as a work area of 0, ROM 23 in which operation programs of the central processing unit 20 are stored,
Interrupt controller 24 for controlling interrupt requests from inside and outside, serial communication interface 25 for controlling serial transfer of data, 8-bit timer 2
6, pulse-wise modulation timer 27, 16-bit free running timer 28, A / D converter 29,
The circuit block including the watchdog timer 30 and the like is connected to predetermined ones of the address bus IAB, the upper data bus UDB, and the lower data bus LDB. The interface with the outside is from the first port 41 to the ninth
This is done via port 49.

In the extended mode in which the external memory space is also used as the program address space, the fifth port 45 and the sixth port 46 are assigned to the I / O port PA11-0 / A19-8 shown in FIG. The 4-port 44 is an output port assigned to the addresses A7 to A0. In this operation mode, the serial communication interface 25 interfaces with the outside through the ninth port 49. The data input / output port D7-0 of FIG. 1 is assigned to the third port 43, and the port PC0 terminal, port PC1 terminal, and port PB terminal of FIG. 1 are assigned to the second port 42. The other ports function as input / output ports for various access control signals such as read / write signals and interrupt signals.

Next, the operation of the emulator 1 shown in FIG. 1 will be described. The user interface circuit 10 is coupled to a microprocessor mounting area of the target system via an interface cable or the like, and the control processor SMPU is incorporated in the ninth port 49.
Is connected to the system development device 2 via.

When the system is started, the reset signal is forcibly input to the control processor SMPU by the port PC1 terminal.
U is in the system bus available state. In this state, the control processor SMPU has the port PA11-0 / A.
19-8 is internally set as an output port of the address signals A19 to A8, various emulation execution conditions are set in the break circuit and the trace circuit, and the execution program of the emulation microprocessor EMPU is loaded into the emulation RAM 6. After that, the ports PA11-0 / A19-8 are internally set as input port terminals, the port PC0 terminal is set to low level, the bus use right is switched to the emulation microprocessor EMPU, and the port PC1 terminal is set to low level. Emulation Microprocessor EM
Start emulation by PU.

During execution of emulation, the control processor SMPU controls execution of emulation and monitors the execution state through the input / output port terminal PB, and at the same time, the port PA11-functioning as an input port.
0 / A19-8 to execute program addresses A19-A of the microprocessor EMPU for emulation
Take in 8. The fetched program address is transferred to the system development device 2 via the serial communication interface and displayed on the display device so that the execution state of the program can be monitored in real time.

When a break occurs thereafter, the emulation microprocessor EMPU executes the SLEEP instruction set in the RAM 9, for example, and stops the operation. As a result, the control processor SM
The PU acquires the bus right and controls the transfer of the information accumulated in the trace circuit 8 to the system development device 2 side.

According to the above embodiment, there are the following effects.

(1) Input / output port PA of the control processor SMPU whose function is selected as an input port when the emulation microprocessor EMPU has acquired the bus right and is performing emulation.
11-0 / A19-8 is an execution program address A19- of the emulation microprocessor EMPU.
Take in A8. The fetched program address is transferred to the system development device 2 via the serial communication interface and displayed on the display device so that the execution state of the program can be monitored in real time.

(2) Therefore, the execution of another microprocessor sharing the bus without providing a dedicated circuit for defining and arranging the latch circuit holding the information of the address bus in the external address space of the control processor. The status can be monitored via the shared bus.

(3) By the above (2), it is possible to reduce the size of the emulator in which the emulation microprocessor and the control processor share the bus.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the embodiments and various modifications can be made without departing from the scope of the invention. Yes. For example,
In the microprocessor SMPU of the above embodiment, the output ports of the addresses A7 to A0 have been described as output-only ports, but the present invention is not limited to this, and input / output ports may also be assigned to the addresses. Also,
The information to be monitored via the I / O port is not limited to the target program or user program,
It may be data bus information. A bus to which information to be monitored is transferred may be connected to the I / O port.
If it is not necessary to access the bus for transmitting the information to be monitored, the bus for transmitting the signal may be connected to the input-only port.

In the above description, the invention mainly made by the present inventor was applied to an emulator which is a field of application which is the background of the invention. However, the present invention is not limited thereto, and various board products and the like. It can be widely used for debugging of microprocessor application devices.

The present invention can be applied to a multiprocessor system that shares at least a bus under the condition that the operating states of some microprocessors can be monitored through other microprocessors.

[0031]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, without providing a dedicated circuit for defining and arranging a latch circuit or the like for holding bus information in the external address space of the control processor, the execution states of other microprocessors sharing the bus can be shared. There is an effect that it can be easily monitored via. Furthermore, when the present invention is applied to an emulator, there is an effect that it is possible to achieve miniaturization of an emulator in which the emulation microprocessor and the control processor share a bus.

[Brief description of drawings]

FIG. 1 is a block diagram of an emulator according to an embodiment of the present invention.

2 is a block diagram of an example of a control processor included in the emulator of FIG.

[Explanation of symbols]

1 Emulator 2 System Development Device 3, 4 Buffer 5 Emulation Control Circuit 6 Emulation RAM 7 Break Circuit 8 Trace Circuit 9 RAM 10 User Interface Circuit SMPU Control Processor (Control Microprocessor) EMPU Emulation Microprocessor ABUS Address Bus DBUS Data Bus PA11 -0 / A19-8 Input / output port A7-0 Address output dedicated port D7-0 Data input / output port 20 Central processing unit 41 to 49 ports

Claims (3)

[Claims] 1. A system in which a plurality of microprocessors share a bus, wherein at least one of the microprocessors has an input / output port and an output port for outputting an input from the port. The I / O port is directly coupled to the bus, the bus information when another microprocessor has the bus right is taken in from the I / O port, and the taken information can be externally monitored through the output port. Debug device. 2. The microprocessor having the I / O port uses the I / O port as a bus signal output port in response to the acquisition of the bus right, and the I / O port uses the bus signal in response to the bus right abandonment. 2. The debugging device according to claim 1, which has an operation mode of being an input port. 3. An emulation microprocessor for proxy control of a target system, a control microprocessor for emulation control, a bus to which both processors are commonly connected, and a trace circuit respectively connected to the bus. And a break circuit, and an interface circuit for connecting the bus to a target system, wherein the control microprocessor has an input / output port directly connected to the bus and an output for outputting an input from the port. An emulator that has a port and takes in the bus information from the I / O port when the emulation microprocessor has a bus right, and can externally monitor the taken information through the output port.