JPH0594427A - Fault monitor system for decentralized processor system - Google Patents

Abstract

PURPOSE:To easily operate the fault processing of a decentralized processor system. CONSTITUTION:A sub-processor system 1 is equipped with a port 11, and logical '1' and '0' signals are outputted through the port 11 to a monitoring signal line 4 of a communication line 3 by a program. A main processor system 2 is equipped with a retriggerable monostable multivibrator 21 which inputs the monitoring signal from the sub-processor system 1 as a trigger signal, and outputs a signal having a pulse width which is longer than the one cycle of the monitoring signal, and shorter than the two cycles of the monitoring signal. The output of the pertinent retriggerable monostable multivibrator 21 is inputted to the interruption terminal of a CPU 22. The retriggerable monostable multivibrator 21 detects that the monitoring signal is not periodically outputted due to the abnormal operation of the sub-processor system 1.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a fault monitoring system for a distributed processor system, and more particularly to a fault monitoring system for a distributed processor system for realizing a fault detection system for a secondary processor system.

[0002]

2. Description of the Related Art In a conventional distributed processor system, as a method of monitoring the operation of a sub processor system, a command for operation monitoring is periodically transmitted from the main processor system to the sub processor system, and the sub processor system is operated as described above. There is a timer monitoring method in which when a command is received, a response command to the command is sent back, and the main processor system monitors the response from the sub processor system.

[0003]

The above-described conventional operation monitoring method has a problem that both the main processor system and the sub processor system need a program for processing a command for operation monitoring. There was a problem that a load was added to the processing. Also, there is a problem that the traffic of the communication circuit increases because the above-mentioned command and response command are transmitted and received on the communication circuit. Furthermore, in the secondary processor system, it is necessary to process the operation monitoring command asynchronously with the original processing, and the program is complicated. However, there was a problem that bugs are likely to occur.

[0004]

A fault monitoring system for a distributed processor system according to the present invention comprises a main processor system,
In a distributed processor system including a sub processor system that performs distributed processing under the control of the main processor system, and a communication circuit that connects the main processor system and the sub processor system, the main processor system is the sub processor system. In order to monitor the operation, one signal line is added to the communication circuit, the sub processor system has a port connected to one end of the signal line, and the program of the sub processor system alternates to the port. Has a writing means for periodically writing data of logic "1" and "0", and one main processor system has "1" sent from the sub processor system to one end of the signal line. , "0" alternating signal is input as a trigger signal and its output is the CP of the main processor system. Leave connection to the interrupt input, and has a retriggerable monostable multivibrator for generating a pulse signal having a period shorter than two periods longer than one period of the trigger signal.

[0005]

In the present invention, the fault processing of the distributed processor system is facilitated.

[0006]

FIG. 1 is a block diagram showing an embodiment of the present invention. In FIG. 1, 2 is a main processor system,
Reference numeral 1 denotes a sub-processor system that performs distributed processing under the control of the main processor system 2, 3 is a communication circuit that is a communication path for connecting the main processor system 2 and the sub-processor system 1 for communication, and 4 is the communication circuit 3 It is a monitoring signal line provided inside. The sub processor system 1 includes the CPU 12, the program memory 13 and the CP.
The U bus 14 is further provided with a port 11 for outputting a signal for monitoring the operation of the main processor system 2 to the supervisory signal line 4, and the program memory 13 periodically sends a signal "1" to the port 11. , And a signal "0" are written alternately.

On the other hand, the main processor system 2 is the CPU 2
2 and a program memory 23 and a CPU bus 24, and further has a retriggerable monostable multivibrator 21 which inputs the monitoring signal line 4 and outputs a pulse signal of a constant cycle. The output of the table multivibrator 21 is the CPU 2
2 is connected to the interrupt terminal. Further, the program memory 23 stores a program which is activated by the above-mentioned interrupt and analyzes an interrupt factor to perform an abnormal process of the sub processor system 1. Here, the CPU 12 and the program memory 13 of the sub processor system 1 constitute a writing unit that alternately writes data of logic “1” and “0” to the port 11.

As described above, since the main processor system 2 monitors the operation of the sub processor system 1, one supervisory signal line 4 is added to the communication circuit 3, and the supervisory signal line 4 is added to the sub processor system 1. Of the secondary processor system 1 has a writing means for writing data of logical "1" and "0" alternately to the port 11, and one main processor To the system 2, a signal of alternating "1" and "0" sent from the sub processor system 1 is input to one end of the monitoring signal line 4 as a trigger signal, and its output is interrupted by the CPU 22 of the main processor system 2. It has a retriggerable monostable multivibrator 21 that is connected to the input and generates a pulse signal with a period longer than 1 period and shorter than 2 periods of the trigger signal. To have.

FIG. 2 is a time chart used to explain the operation of FIG. 1. (a) shows a write signal of the port 11, (b) is an output signal of the port 11, and (c) is a retriggerable signal. The output signal of the monostable multivibrator 21 is shown.

Next, the operation of the embodiment shown in FIG. 1 will be described with reference to FIG. First, the CP of the sub processor system 1
The U12 reads out a program written in the program memory 13 in advance and operates. Here, the program incorporates a program that is started up periodically when the program is operating normally and writes logic "1" and "0" alternately to the port 11. Then, in accordance with the operation of this program, the write signal a shown in FIG. 2A and the data of logic “1” or logic “0” are output to the port 11 and are output to the monitor signal line 4 connected to the port 11. The output signal b of the port 11 shown in FIG. 2B, which changes periodically, is output. Then, when an abnormal operation such as a runaway occurs in the sub processor system 1, the program for generating the monitoring signal is also not started, and therefore writing to the port 11 is not performed regularly,
The output signal b of the port 11 output to the monitoring signal line 4 also becomes abnormal.

Next, in the main processor system 2, the output signal b of the port 11 coming through the supervisory signal line 4 is input to the trigger terminal of the retriggerable monostable multivibrator 21. Here, the retriggerable monostable multivibrator 21 has an output pulse width set so as to generate a pulse longer than one cycle and shorter than two cycles of the trigger signal. Then, while the sub-processor system 1 operates normally and the output signal b of the port 11 periodically arrives, the output of the retriggerable monostable multivibrator 21 is retriggered and thus becomes a logic "1". Although fixed, if the operation of the sub-processor system 1 becomes abnormal and the signal does not change for more than 2 cycles, the retriggerable monostable multivibrator 2
The output of 1 changes to logic "0". The output of the retriggerable monostable multivibrator 21 is connected to the interrupt terminal of the CPU 22.
2 is interrupted. An interrupt processing program previously written in the program memory 23 is activated by this interrupt, the cause of the interrupt is analyzed, and abnormal processing for the sub processor system 1 is performed.

[0012]

As described above, according to the present invention, the failure processing of the distributed processor system is facilitated. Therefore, in the distributed processor system, the program of each processor system is not complicated, and complicated processing is possible. There is an effect that the main processor system can easily monitor the operation of the sub processor system without adding hardware.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a time chart used for explaining the operation of FIG.

[Explanation of symbols]

 1 Sub Processor System 2 Main Processor System 3 Communication Circuit 4 Monitoring Signal Line (Signal Line) 11 Port 12 CPU 13 Program Memory 14 CPU Bus 21 Retriggerable Monostable Multivibrator 22 CPU 23 Program Memory 24 CPU Bus

Claims (1)

[Claims] 1. A distributed processor system comprising a main processor system, a sub processor system for performing distributed processing under the control of the main processor system, and a communication circuit connecting the main processor system and the sub processor system, The main processor system adds one signal line to the communication circuit to monitor the operation of the sub processor system, and the sub processor system has a port connected to one end of the signal line, The program of the processor system has write means for periodically writing data of logic "1" and "0" alternately to the port, and one main processor system has the sub processor at one end of the signal line. The signal of the alternating "1" and "0" sent from the system is input as a trigger signal, and the output Power is connected to the interrupt input of the CPU of the main processor system, and a retriggerable monostable multivibrator for generating a pulse signal having a cycle longer than one cycle and shorter than two cycles of the trigger signal is distributed. Fault monitoring method for processor system.