JPH0594988A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0594988A JPH0594988A JP25402891A JP25402891A JPH0594988A JP H0594988 A JPH0594988 A JP H0594988A JP 25402891 A JP25402891 A JP 25402891A JP 25402891 A JP25402891 A JP 25402891A JP H0594988 A JPH0594988 A JP H0594988A
- Authority
- JP
- Japan
- Prior art keywords
- film
- polyimide resin
- metal wiring
- insulating film
- resin film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 16
- 229920001721 polyimide Polymers 0.000 claims abstract description 26
- 239000009719 polyimide resin Substances 0.000 claims abstract description 23
- 229910052751 metal Inorganic materials 0.000 claims abstract description 17
- 239000002184 metal Substances 0.000 claims abstract description 17
- 239000011347 resin Substances 0.000 claims abstract description 6
- 229920005989 resin Polymers 0.000 claims abstract description 6
- 239000000758 substrate Substances 0.000 claims description 5
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 abstract description 9
- 239000010931 gold Substances 0.000 abstract description 9
- 229910052737 gold Inorganic materials 0.000 abstract description 9
- 239000011229 interlayer Substances 0.000 abstract description 8
- MAKDTFFYCIMFQP-UHFFFAOYSA-N titanium tungsten Chemical compound [Ti].[W] MAKDTFFYCIMFQP-UHFFFAOYSA-N 0.000 abstract 1
- 238000000034 method Methods 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 239000004642 Polyimide Substances 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 3
- 150000004767 nitrides Chemical class 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000010410 layer Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Formation Of Insulating Films (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は半導体装置に関し、特に
多層配線を有する半導体装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device having multi-layer wiring.
【０００２】[0002]
【従来の技術】多層配線を有する半導体装置の層間絶縁
膜の上面を平坦化する方法としてプラズマＣＶＤ絶縁膜
とＳＯＧ膜を組み合わせた方法、ポリイミド系樹脂膜を
塗布する方法などがある。2. Description of the Related Art As a method of flattening the upper surface of an interlayer insulating film of a semiconductor device having a multilayer wiring, there are a method of combining a plasma CVD insulating film and an SOG film, a method of applying a polyimide resin film, and the like.
【０００３】図２は従来の半導体装置の一例を示す半導
体チップの断面図である。FIG. 2 is a sectional view of a semiconductor chip showing an example of a conventional semiconductor device.
【０００４】図２に示すように、シリコン基板１の上に
設けた酸化シリコン膜２の上に金属配線３を形成した
後、金属配線３と密着性の良い絶縁膜５、例えばＣＶＤ
法により形成した窒化シリコン膜（以下ＣＶＤ窒化膜と
記す）を薄く被着し、さらに平坦化用のポリイミド系樹
脂膜４を厚く塗布して層間絶縁膜が形成される。As shown in FIG. 2, after the metal wiring 3 is formed on the silicon oxide film 2 provided on the silicon substrate 1, an insulating film 5 having good adhesion to the metal wiring 3, for example, CVD.
A silicon nitride film (hereinafter referred to as a CVD nitride film) formed by the method is thinly applied, and a polyimide resin film 4 for planarization is thickly applied to form an interlayer insulating film.
【０００５】[0005]
【発明が解決しようとする課題】この従来の半導体装置
では、配線の段差により層間絶縁膜の上面に図３に示す
段差１０が生じて平坦性が悪くなる。多層配線におい
て、この段差が累積されると、上層配線の微細化ができ
なくなるという問題があった。In this conventional semiconductor device, the flatness is deteriorated due to the step 10 shown in FIG. 3 on the upper surface of the interlayer insulating film due to the step of the wiring. In the multi-layer wiring, if the step is accumulated, there is a problem that the upper wiring cannot be miniaturized.
【０００６】また、金属配線３として金配線を用い、絶
縁膜５としてポリイミド系樹脂膜４とは異種の金配線と
密着性が良く、流動性の高い接着用のポリイミド系樹脂
膜を用いた場合、この接着用のポリイミド系樹脂膜は密
着性を良くするため薄く塗布することが必要である。こ
のため、金配線の上面の端部には被着されず露出してい
ることがあり、金配線と平坦化用ポリイミド系樹脂膜が
直接接することとなり、後工程の熱処理によりこの部分
ではがれが生じることがある。In the case where a gold wiring is used as the metal wiring 3 and an adhesive polyimide resin film having high fluidity and good adhesion with a gold wiring different from the polyimide resin film 4 is used as the insulating film 5. The polyimide resin film for adhesion needs to be thinly applied to improve the adhesion. For this reason, the gold wiring may be exposed at the end portion of the upper surface without being deposited, and the gold wiring and the planarizing polyimide resin film are in direct contact with each other. May occur.
【０００７】[0007]
【課題を解決するための手段】本発明の半導体装置は半
導体基板上に設けた金属配線と、前記金属配線の側面に
接して設け上面が前記金属配線の上面と同一平面を有す
る第１のポリイミド系樹脂膜と、前記金属配線を含む前
記第１のポリイミド系樹脂膜の表面に薄く形成した前記
金属配線と密着性の良い絶縁膜と前記絶縁膜上に厚く形
成した前記第１のポリイミド系樹脂膜と同種の第２のポ
リイミド系樹脂膜とを有する。In a semiconductor device of the present invention, a first polyimide having a metal wiring provided on a semiconductor substrate and an upper surface which is provided in contact with a side surface of the metal wiring and whose upper surface is flush with the upper surface of the metal wiring. -Based resin film, an insulating film having good adhesion to the metal wiring thinly formed on the surface of the first polyimide-based resin film including the metal wiring, and the first polyimide-based resin thickly formed on the insulating film And a second polyimide resin film of the same type as the film.
【０００８】[0008]
【実施例】次に、本発明について図面を参照して説明す
る。DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.
【０００９】図１（ａ）〜（ｄ）は本発明の一実施例の
製造方法を説明するための工程順に示した半導体チップ
の断面図である。FIGS. 1A to 1D are sectional views of a semiconductor chip in the order of steps for explaining a manufacturing method according to an embodiment of the present invention.
【００１０】まず、図１（ａ）に示す様に、シリコン基
板１の上に酸化シリコン膜２を堆積した後、密着用及び
バリア用のチタン・タングステン膜７及び金膜８を順次
堆積してパターニングした配線を形成する。First, as shown in FIG. 1A, after depositing a silicon oxide film 2 on a silicon substrate 1, a titanium / tungsten film 7 for adhesion and a barrier and a gold film 8 are sequentially deposited. A patterned wiring is formed.
【００１１】次に、図１（ｂ）に示す様に、配線を含む
表面に平坦化用のポリイミド系樹脂膜４を１．５μｍの
厚さに塗布し、樹脂膜を硬化させる熱処理を行い、ポリ
イミド系樹脂膜４の上にフォトレジスト膜９を３μｍの
厚さに塗布する。Next, as shown in FIG. 1B, a planarizing polyimide resin film 4 is applied to the surface including the wiring to a thickness of 1.5 μm, and a heat treatment for hardening the resin film is performed. A photoresist film 9 is applied on the polyimide resin film 4 to a thickness of 3 μm.
【００１２】次に、図１（ｃ）に示す様に、フォトレジ
スト膜９とポリイミド系樹脂膜４を金膜８の上面が露出
するまでエッチバックする。この時、エッチングガスと
して例えばＣＦ4 ガスを用いフォトレジスト膜９とポリ
イミド系樹脂膜４のエッチングレートが同じになる様に
条件を設定する。Next, as shown in FIG. 1C, the photoresist film 9 and the polyimide resin film 4 are etched back until the upper surface of the gold film 8 is exposed. At this time, conditions are set so that the photoresist film 9 and the polyimide resin film 4 have the same etching rate by using, for example, CF 4 gas as an etching gas.
【００１３】次に、図１（ｄ）に示すように、金膜８と
密着性の良い絶縁膜５例えばプラズマＣＶＤ窒化膜を５
０ｎｍの厚さに堆積し、さらにポリイミド系樹脂膜４と
同種のポリイミド系樹脂膜６を１．５μｍの厚さに塗布
して熱処理を行い、上面を平坦化した層間絶縁膜を有す
る半導体装置を構成する。Next, as shown in FIG. 1D, an insulating film 5 having good adhesion to the gold film 8 such as a plasma CVD nitride film 5 is formed.
A semiconductor device having an interlayer insulating film whose upper surface is flattened is deposited to a thickness of 0 nm, a polyimide resin film 6 of the same kind as the polyimide resin film 4 is applied to a thickness of 1.5 μm, and heat treatment is performed. Constitute.
【００１４】なお、絶縁膜５として、ＣＶＤ窒化膜の代
りに平坦化用のポリイミド系樹脂膜とは異種の接着用の
ポリイミド系樹脂膜を０．１μｍの厚さに塗布しても良
く、金膜８の平面にのみ塗布するため密着性が改善され
熱処理によるはがれを生ずることはない。As the insulating film 5, instead of the CVD nitride film, a polyimide resin film for adhesion different from the planarization polyimide resin film may be applied to a thickness of 0.1 μm. Since the coating is applied only to the flat surface of the film 8, adhesion is improved and peeling due to heat treatment does not occur.
【００１５】[0015]
【発明の効果】以上説明したように本発明によれば、従
来例の層間絶縁膜による平坦性が層間絶縁膜の厚さに対
する高低差の比率が３０％であったのに対して１０％以
内まで抑えることができ、多層配線の上層配線の微細化
が容易に実現できるという効果を有する。As described above, according to the present invention, the flatness of the conventional interlayer insulating film is within 10% as compared with the ratio of the height difference to the thickness of the interlayer insulating film of 30%. It is possible to suppress the above, and it is possible to easily realize miniaturization of the upper wiring of the multilayer wiring.
【図１】本発明の一実施例の製造方法を説明するための
工程順に示した半導体チップの断面図。FIG. 1 is a cross-sectional view of a semiconductor chip showing the order of steps for explaining a manufacturing method according to an embodiment of the present invention.
【図２】従来の半導体装置の一例を示す半導体チップの
断面図。FIG. 2 is a sectional view of a semiconductor chip showing an example of a conventional semiconductor device.
１ シリコン基板 ２ 酸化シリコン膜 ３ 金属配線 ４，６ ポリイミド系樹脂膜 ５ 絶縁膜 ７ チタン・タングステン膜 ８ 金膜 ９ フォトレジスト膜 １０ 段差 1 Silicon Substrate 2 Silicon Oxide Film 3 Metal Wiring 4, 6 Polyimide Resin Film 5 Insulating Film 7 Titanium / Tungsten Film 8 Gold Film 9 Photoresist Film 10 Step
Claims (1)
金属配線の側面に接して設け上面が前記金属配線の上面
と同一平面を有する第１のポリイミド系樹脂膜と、前記
金属配線を含む前記第１のポリイミド系樹脂膜の表面に
薄く形成した前記金属配線と密着性の良い絶縁膜と、前
記絶縁膜上に厚く形成した前記第１のポリイミド系樹脂
膜と同種の第２のポリイミド系樹脂膜とを有することを
特徴とする半導体装置。1. A metal wiring provided on a semiconductor substrate, a first polyimide resin film provided in contact with a side surface of the metal wiring and having an upper surface flush with an upper surface of the metal wiring, and the metal wiring. An insulating film that is thinly formed on the surface of the first polyimide resin film and has good adhesion to the metal wiring, and a second polyimide resin that is the same kind as the first polyimide resin film that is thickly formed on the insulating film. A semiconductor device having a resin film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP25402891A JPH0594988A (en) | 1991-10-02 | 1991-10-02 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP25402891A JPH0594988A (en) | 1991-10-02 | 1991-10-02 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0594988A true JPH0594988A (en) | 1993-04-16 |
Family
ID=17259238
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP25402891A Pending JPH0594988A (en) | 1991-10-02 | 1991-10-02 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0594988A (en) |
-
1991
- 1991-10-02 JP JP25402891A patent/JPH0594988A/en active Pending
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