JPH0621053A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH0621053A JPH0621053A JP17631692A JP17631692A JPH0621053A JP H0621053 A JPH0621053 A JP H0621053A JP 17631692 A JP17631692 A JP 17631692A JP 17631692 A JP17631692 A JP 17631692A JP H0621053 A JPH0621053 A JP H0621053A
- Authority
- JP
- Japan
- Prior art keywords
- film
- contact hole
- metal film
- tungsten
- refractory metal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は半導体装置の製造方法に
関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device.
【0002】[0002]
【従来の技術】従来の半導体装置の製造方法は、まず、
図2(a)に示すように、P型シリコン基板1の一主面
に選択的に設けたフィールド酸化膜2により区画した素
子形成領域上に設けたゲート電極3に整合してN型拡散
層4を形成し、ゲート電極3を含む表面に層間絶縁膜5
を形成し、コンタクト孔を形成する。次にコンタクト孔
を含む表面にチタン膜及び窒化チタン膜からなる接着膜
6及びタングステン膜7を順次堆積してSF6 ガスによ
るドライエッチングでタングステン膜7をエッチバック
してコンタクト孔内に埋込んだ後、タングステン膜7を
マスクとしてCl2 ガスによるドライエッチングで接着
膜6を除去する。2. Description of the Related Art A conventional semiconductor device manufacturing method is as follows.
As shown in FIG. 2A, the N-type diffusion layer is aligned with the gate electrode 3 provided on the element formation region partitioned by the field oxide film 2 selectively provided on one main surface of the P-type silicon substrate 1. 4 is formed, and an interlayer insulating film 5 is formed on the surface including the gate electrode 3.
And a contact hole is formed. Next, an adhesion film 6 made of a titanium film and a titanium nitride film and a tungsten film 7 are sequentially deposited on the surface including the contact hole, and the tungsten film 7 is etched back by dry etching with SF 6 gas to be embedded in the contact hole. After that, the adhesive film 6 is removed by dry etching with Cl 2 gas using the tungsten film 7 as a mask.
【0003】次に、図2(b)に示すように、チタン
膜,窒化チタン膜からなる接着膜10をスパッタで堆積
した後アルミニウム膜8及び窒化チタン膜9を堆積して
パターニングし配線を形成していた。Next, as shown in FIG. 2B, an adhesive film 10 made of a titanium film and a titanium nitride film is deposited by sputtering, and then an aluminum film 8 and a titanium nitride film 9 are deposited and patterned to form wiring. Was.
【0004】[0004]
【発明が解決しようとする課題】この従来の半導体装置
の製造方法では、コンタクト孔を含む表面に設けた接着
膜とタングステン膜をエッチバックする際、まず、SF
6 等のガスを用いてタングステン膜をエッチバックして
コンタクト孔内にのみタングステン膜を残した後接着膜
をCl2 ガスを用いてエッチバックしていたため、タン
グステン膜が、接着膜のエッチングでコンタクト孔内に
残すはずのタングステン膜が更にエッチングされ、コン
タクト不良を生じたり、平坦性が悪くなるという問題が
あった。In this conventional method of manufacturing a semiconductor device, when the adhesive film and the tungsten film provided on the surface including the contact holes are etched back, first the SF film is formed.
Since the tungsten film was etched back using a gas such as 6 to leave the tungsten film only in the contact holes, and then the adhesive film was etched back using Cl 2 gas, the tungsten film was contacted by etching the adhesive film. There is a problem that the tungsten film that should be left in the hole is further etched, resulting in contact failure and poor flatness.
【0005】[0005]
【課題を解決するための手段】本発明の半導体装置の製
造方法は、半導体基板上に設けた層間絶縁膜にコンタク
ト孔を形成する工程と、前記コンタクト孔を含む表面に
密着性を向上させる接着膜及び高融点金属膜を順次堆積
する工程と、前記接着膜をエッチングストッパとして前
記高融点金属膜をエッチバックし前記コンタクト孔内に
埋込む工程と、前記高融点金属膜を含む表面に金属膜を
堆積してパターニングし前記高融点金属膜と電気的に接
続する配線を形成する工程とを含んで構成される。A method of manufacturing a semiconductor device according to the present invention comprises a step of forming a contact hole in an interlayer insulating film provided on a semiconductor substrate, and an adhesion for improving adhesion on a surface including the contact hole. A step of sequentially depositing a film and a refractory metal film, a step of etching back the refractory metal film by using the adhesive film as an etching stopper and filling the contact hole, and a metal film on the surface including the refractory metal film. Is deposited and patterned to form a wiring electrically connected to the refractory metal film.
【0006】[0006]
【実施例】次に、本発明について図面を参照して説明す
る。DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.
【0007】図1(a)〜(c)は本発明の一実施例の
製造方法を説明するための工程順に示した半導体チップ
の断面図である。1A to 1C are cross-sectional views of a semiconductor chip showing the order of steps for explaining a manufacturing method according to an embodiment of the present invention.
【0008】まず、図1(a)に示すように、P型シリ
コン基板1の一主面に選択的に形成したフィールド酸化
膜2により素子形成領域を区画し、この素子形成領域上
に設けたゲート電極3に整合してN型拡散層4を形成す
る。次に、ゲート電極3を含む表面に層間絶縁膜5を堆
積して選択的に異方性エッチングし、コンタクト孔を形
成し、N型拡散層4の表面を露出させる。次に、コンタ
クト孔を含む層間絶縁膜5の表面にスパッタ法で厚さ1
0〜200nmのチタン膜及び厚さ10〜200nmの
窒化チタン膜を順次堆積して接着膜6を形成し、接着膜
6の表面にCVD法でタングステン膜7を0.1〜1μ
mの厚さに堆積する。First, as shown in FIG. 1A, an element formation region is partitioned by a field oxide film 2 selectively formed on one main surface of a P-type silicon substrate 1, and the element formation region is provided on this element formation region. The N-type diffusion layer 4 is formed in alignment with the gate electrode 3. Next, an interlayer insulating film 5 is deposited on the surface including the gate electrode 3 and selectively anisotropically etched to form a contact hole to expose the surface of the N-type diffusion layer 4. Next, a thickness of 1 is formed on the surface of the interlayer insulating film 5 including the contact holes by the sputtering method.
A titanium film having a thickness of 0 to 200 nm and a titanium nitride film having a thickness of 10 to 200 nm are sequentially deposited to form an adhesive film 6, and a tungsten film 7 is formed on the surface of the adhesive film 6 by a CVD method in an amount of 0.1 to 1 μm.
Deposit to a thickness of m.
【0009】次に、図1(b)に示すように、SF6 系
ガスを用いた異方性ドライエッチングにより接着膜6の
表面がちょうど露出するまでタングステン膜7をエッチ
バックしてコンタクト孔内にタングステン膜7を埋込
む。ここで、タングステン膜7のエッチングレート30
0〜800nm/minに対して接着膜6のエッチング
レートは0.1nm/min未満であり、接着膜6は殆
んどエッチングされない。Next, as shown in FIG. 1B, the tungsten film 7 is etched back by anisotropic dry etching using SF 6 gas until the surface of the adhesive film 6 is just exposed. The tungsten film 7 is buried in the. Here, the etching rate of the tungsten film 7 is 30
The etching rate of the adhesive film 6 is less than 0.1 nm / min for 0 to 800 nm / min, and the adhesive film 6 is hardly etched.
【0010】次に、図1(c)に示すように、埋込まれ
たタングステン膜6を含む表面にアルミニウム膜8をス
パッタ法により堆積し、目合わせ露光の反射防止膜とし
て窒化チタン膜9をスパッタ法により50〜200nm
の厚さに堆積し、窒化チタン膜9,アルミニウム膜8及
び接着膜6を選択的に順次エッチングしてタングステン
膜6を介してN型拡散層4と電気的に接続する電極配線
を形成する。Next, as shown in FIG. 1C, an aluminum film 8 is deposited on the surface including the buried tungsten film 6 by a sputtering method, and a titanium nitride film 9 is formed as an antireflection film for alignment exposure. 50 to 200 nm by sputtering method
And the titanium nitride film 9, the aluminum film 8 and the adhesive film 6 are selectively and sequentially etched to form an electrode wiring electrically connected to the N-type diffusion layer 4 through the tungsten film 6.
【0011】なお、接着膜6として厚さ150nm程度
のTiW膜を使用してもよく、タングステン膜7との異
常反応がおこり難い利点がある。A TiW film having a thickness of about 150 nm may be used as the adhesive film 6, which has an advantage that an abnormal reaction with the tungsten film 7 is unlikely to occur.
【0012】[0012]
【発明の効果】以上説明したように本発明は、コンタク
ト孔内に埋込むタングステン膜を形成するための、エッ
チバックにおいて、接着膜をエッチバックせず、タング
ステン膜のみをエッチバックすることにより、コンタク
ト孔内部のタングステン膜の減少をおさえることがで
き、アルミニウム膜とのコンタクト不良を防止し、配線
の平坦性を向上させることができるという効果を有す
る。As described above, according to the present invention, in the etching back for forming the tungsten film to be buried in the contact hole, only the tungsten film is etched back without etching the adhesive film. There is an effect that the reduction of the tungsten film inside the contact hole can be suppressed, contact failure with the aluminum film can be prevented, and the flatness of the wiring can be improved.
【図1】本発明の一実施例の説明するための工程順に示
した半導体チップの断面図。1A to 1C are cross-sectional views of a semiconductor chip, which are shown in the order of steps for explaining an embodiment of the present invention.
【図2】従来の半導体装置の製造方法を説明するための
工程順に示した半導体チップの断面図。FIG. 2 is a cross-sectional view of a semiconductor chip showing the order of steps for explaining a conventional method for manufacturing a semiconductor device.
1 P型シリコン基板 2 フィールド酸化膜 3 ゲート電極 4 N型拡散層 5 層間絶縁膜 6,10 接着膜 7 タングステン膜 8 アルミニウム膜 9 窒化チタン膜 1 P-type silicon substrate 2 Field oxide film 3 Gate electrode 4 N-type diffusion layer 5 Interlayer insulating film 6, 10 Adhesive film 7 Tungsten film 8 Aluminum film 9 Titanium nitride film
Claims (1)
タクト孔を形成する工程と、前記コンタクト孔を含む表
面に密着性を向上させる接着膜及び高融点金属膜を順次
堆積する工程と、前記接着膜をエッチングストッパとし
て前記高融点金属膜をエッチバックし前記コンタクト孔
内に埋込む工程と、前記高融点金属膜を含む表面に金属
膜を堆積してパターニングし前記高融点金属膜と電気的
に接続する配線を形成する工程とを含むことを特徴とす
る半導体装置の製造方法。1. A step of forming a contact hole in an interlayer insulating film provided on a semiconductor substrate, a step of sequentially depositing an adhesive film and a refractory metal film for improving adhesion on a surface including the contact hole, A step of etching back the refractory metal film by using the adhesive film as an etching stopper and burying it in the contact hole, and depositing and patterning a metal film on the surface including the refractory metal film to electrically connect the refractory metal film And a step of forming a wiring connected to the semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17631692A JPH0621053A (en) | 1992-07-03 | 1992-07-03 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17631692A JPH0621053A (en) | 1992-07-03 | 1992-07-03 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0621053A true JPH0621053A (en) | 1994-01-28 |
Family
ID=16011457
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17631692A Pending JPH0621053A (en) | 1992-07-03 | 1992-07-03 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0621053A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001358311A (en) * | 2000-06-12 | 2001-12-26 | Nec Corp | Semiconductor device and its manufacturing method |
| KR20130000206A (en) * | 2011-06-22 | 2013-01-02 | 삼성전자주식회사 | Method for manufacturing semiconductor device using etch stop dielectric layer |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04152550A (en) * | 1990-10-16 | 1992-05-26 | Oki Electric Ind Co Ltd | Manufacture of semiconductor device |
-
1992
- 1992-07-03 JP JP17631692A patent/JPH0621053A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04152550A (en) * | 1990-10-16 | 1992-05-26 | Oki Electric Ind Co Ltd | Manufacture of semiconductor device |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001358311A (en) * | 2000-06-12 | 2001-12-26 | Nec Corp | Semiconductor device and its manufacturing method |
| KR20130000206A (en) * | 2011-06-22 | 2013-01-02 | 삼성전자주식회사 | Method for manufacturing semiconductor device using etch stop dielectric layer |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 19980428 |