JPH0595075A - Semiconductor device - Google Patents

Abstract

(57) [Summary] [Structure] TAB using tape with bumps
In the semiconductor device of the type, the material of the protrusion formed on the tip of the inner lead is an Au-Pd plating layer in which the ratio of palladium to gold is 0.01% to 0.5% in atomic ratio, and the protrusion is a semiconductor. The electrodes of the chip are fused and bonded, or a part or all of the palladium of the Au-Pd plated layer is made a white metal other than palladium such as indium, platinum, nickel, etc., and the projection is fused to the electrode of the semiconductor chip. Joined together. [Effect] Since the occurrence of cracks at the joint can be prevented, the joint strength can be maintained initially and in the long term, and the electric resistance can be prevented from lowering, so that a highly reliable semiconductor device can be obtained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device using an insulating film, and more particularly to improving the bonding strength of a bonding portion.

[0002]

2. Description of the Related Art FIG. 7 is a plan view for explaining a conventional semiconductor device using an insulating film, and FIG. 8 is VI-V of FIG.
FIG. 9 is a cross-sectional view taken along line I, FIG. 9 is an explanatory view showing a manufacturing example of the same semiconductor device, and FIG. 10 is a cross-sectional view showing a joined state of the lead and the semiconductor chip. In the figure, 1 is a thickness of 25 to 125 μm in which device holes 2, 2, 2, ... having an area larger than the surface area of a semiconductor chip 7 described later are provided at equal intervals in the length direction.
It is a degree of insulation film. Reference numeral 3 denotes a large number of leads provided on the insulating film 1 and made of a copper metal foil having a thickness of 18 to 35 μm and a width of about 30 to 100 μm.
Is formed. A projecting portion (bump) 3b is formed by half etching on one end of the inner lead 3a. As shown in FIG. 10, the inner lead 3a has a Ni plating layer 4 on its surface, a gold plating layer 5 on the Ni plating layer 4, and the protrusion 3b as a bonding protrusion.
Reference numeral 6 is a sprocket hole for carrying the tape carrier 1. 7 is a semiconductor chip, 7a is a semiconductor chip 7
A gold convex electrode provided on the substrate, 7b is aluminum wiring of the semiconductor chip 7, 7c is an insulating layer for covering the aluminum wiring 7b, 7d is chromium interposed between the aluminum wiring 7b and the convex electrode 7a, It is a barrier metal layer made of titanium, platinum, or the like.

FIG. 9 is an explanatory view showing an example of an apparatus for mounting a semiconductor chip on the tape carrier 1 as described above. The semiconductor chip 7 placed on the chip base 8 is moved to a predetermined position by a positioning guide 9. Positioned. On the other hand, the tape carrier 1 guided by the tape rail 10 and fed by the sprocket in the direction perpendicular to the paper surface stops at the position where the device hole 2 reaches above the semiconductor chip 7, and a large number of aluminum pieces provided on the semiconductor chip 7 are stopped. The electrode 7a and the inner lead 3a of each lead 3 are aligned with the projection 3b covered with the plating layer 4 and the gold plating layer 5 to serve as a bonding projection. Then, the heated bonding tool 11 is lowered to press each inner lead 3a, and the inner lead 3a is formed at a predetermined angle so that the tip end is fused and connected to each aluminum electrode 7a of the semiconductor chip 7.
Next, the tape carrier 1 is moved and each of the semiconductor chip 7 and the leads 3 is sealed with a liquid sealing resin by potting or the like, and then the leads 3 are cut to manufacture a semiconductor device.

[0004]

However, in the semiconductor device as described above, the projection 3b and the semiconductor chip which are covered with the Ni plating layer 4 and the Au plating layer 5 of the inner lead 3a to serve as the bonding projections and the semiconductor chip. In the joint portion where the aluminum electrode 7c of 7 is fused and joined, the metal atom of the metal atom is increased by the resin sealing work after the joining, the thermal screening, or the temperature rise resulting from the high power consumption after being incorporated in the device. Mutual diffusion occurs, which is caused by the progress and brittleness of the intermetallic compound itself, the difference in the coefficient of thermal expansion from the copper inner lead that is the base material, and the Kirkendall effect caused by the difference in the diffusion coefficient of each metal. Due to the formation of holes or cracks, deterioration of the joint portion such as a marked increase in connection resistance and a decrease in joint strength occurred. The graph of FIG. 11 shows the rate of occurrence of open joints at a high temperature of 150 ° C. in the conventional example. After 500 hours, the rate of connection failure (open) due to cracks was 1%.
It is about 0%, and it can be seen that the open occurrence rate is gradually increasing with the passage of time thereafter. Further, FIG. 12 shows a diffusion state in the joint portion in a high temperature standing state. The aluminum electrode 7a of the semiconductor chip 7 and the protrusion 3b of the inner lead 3a in the joint portion after the joint portion is heated at 150 ° C. for 500 hours. It shows the result of analyzing each diffusion state with gold of the Au plating layer 5 covering the X-ray,
It can be seen that gold diffuses throughout the entire joint, which has become an intermetallic compound, but aluminum discontinues along the way. Moreover, the diffusion of this aluminum stopped,
In addition, holes are generated in the portion A where the gold concentration is the minimum. This is due to the Kirkendall effect, which is caused by the fact that the diffusion rate of gold is higher than that of aluminum.

As described above, in the conventional semiconductor device, the protrusion 3b provided at the tip of the inner lead 3a is provided with the Au plating layer 5 via the Ni plating layer 4 to form the bonding projection, and therefore the high temperature is achieved. There was a problem that the joint part deteriorates due to the generation of holes during use and an open occurs.

In order to solve the above-mentioned problems, the ratio of palladium or white metal other than palladium to gold in the bonding projection provided on one side of the tip of the inner lead is 0.01 to 0.5 in atomic weight ratio. % Au-Pd alloy plating or alloy plating of a white metal other than gold and palladium, or a protrusion for joining is formed by the alloy plating to prevent deterioration of the joint at high temperature. .. However, in the above method, although the deterioration of the bonded portion at high temperature is improved, the bonding strength immediately after bonding is low, which causes a secondary problem of lowering the yield.

Therefore, the present invention has been made in order to solve the above-mentioned problems, and does not cause voids or cracks at the joint between the aluminum electrode of the semiconductor element and the joint projection of the inner lead, which is reliable. The purpose of the present invention is to provide a semiconductor device having improved properties with high yield.

[0008]

In a semiconductor device according to the present invention, a semiconductor chip is arranged in a device hole of an insulating film, and a circuit formed on the insulating film is formed on a large number of aluminum electrodes provided on the semiconductor chip. In a semiconductor device in which joining protrusions provided at the tips of inner leads protruding into device holes of a pattern are joined, the protrusions are formed by half etching on one surface of the tip of the inner leads. On the surface of
A barrier layer such as i-plating is provided, and the ratio of palladium to gold is 0.01 to 0.5% A on the plating layer.
The present invention is characterized in that a u-Pd plating layer is provided and the projection is used as a bonding projection.

Further, part or all of the palladium of the Au-Pd plated layer may be at least one white metal selected from white metals other than palladium such as indium, platinum and nickel.

Further, a Sn plating layer or a solder plating layer is provided on the surface of the inner lead, and an Au-Pd plating material having an atomic ratio of palladium to gold of 0.01 to 0.5% is provided on the plating layer. Is provided to form the protrusion as a bonding protrusion, or a barrier layer such as Ni plating is provided on the surface of the inner lead, and a noble metal plating layer such as Au plating is provided on the barrier layer, and the noble metal plating layer is provided on the noble metal plating layer. It is also possible to provide an Au—Pd plated material in which the ratio of palladium to gold is 0.01 to 0.5% in atomic ratio, and use the protrusion as the bonding protrusion.

Further, part or all of the palladium of the Au—Pd plated layer may be at least one white metal selected from white metals other than palladium such as indium, platinum and nickel.

[0012]

According to the present invention, a barrier layer such as Ni plating is provided on the surface of the inner lead having a projection at the tip thereof, and the ratio of paadium to gold is 0.0 in a primitive ratio on the barrier layer.
Since a 1% to 0.5% Au-Pd plating layer is provided to form the protrusion as a bonding protrusion, when the bonding protrusion of the inner lead and the aluminum electrode of the semiconductor chip are fused and bonded, X In the portion where cracks were observed as seen from the line analysis results, that is, the diffusion of aluminum was interrupted, the layer with the highest palladium concentration appeared in the portion with the lowest gold concentration, and the aluminum peak was observed in this portion. This indicates that an Al-Au-Pd ternary alloy was formed in the joint, and the generation of such a ternary alloy prevents the occurrence of cracks in the joint, improves the joint strength, and lowers the electrical resistance. To be prevented.

Also, when part or all of the palladium of the Au--Pd plated layer is a white metal other than palladium such as indium, platinum, nickel, etc., the same function as the above-mentioned palladium is obtained.

Further, a Sn plating layer is provided on the surface of the inner lead, a Ni plating layer is provided on one surface of the Sn plating layer or on the surface of the inner lead, and an Au plating layer is provided on the Ni plating layer. On one side of the tip of the plating layer, the atomic ratio of palladium to gold is 0.01 to
Even when a bonding protrusion is formed by providing a 0.5% Au-Pd plated material, a Ni plating layer is provided on the surface having the protrusion at the tip of the inner lead, and the Au-P is formed on the Ni plating layer.
The same operation is performed when the d-plated layer is provided to form the bonding projection.

[0015]

The details of the present invention will be shown by the following examples.

FIG. 1 is a sectional view showing an embodiment of the present invention, FIG. 2 is an X-ray analysis diagram showing a diffusion state in a high temperature state in a joint portion of the embodiment of the present invention, and FIG. FIG. 4 is a graph showing the relationship between the atomic weight ratio of palladium to gold of Au—Pd alloy plating and the turning strength in the joint portion of the example.
FIG. 4 is a graph showing the relationship between the Au—Pd plated layer and Au—Ni plated layer and Vickers hardness. In the figure, the same configurations as those of the conventional example are designated by the same reference numerals, and the description of the duplicated configurations is omitted. 14 has a protrusion 3b having a height of 10 μm to 15 μm on one side of the tip portion by half etching, and a 0.5 μm thick Ni plating provided on the surface of a copper inner lead 3a having a thickness of 35 μm by electroless plating. layer,
Reference numeral 15 is an Au—Pd plated layer having a thickness of 2 μm provided on the Ni plated layer 14 by electrolytic plating. In this gold plating layer 15, the ratio of palladium to gold is 0.1 in atomic ratio.
It is within the range of 01 to 0.5%. Thus, the Au plating layer 15 is provided on the projection 3b of the inner lead 3a via the Ni plating layer 14 to form the bonding projection.

When Au-Pd alloy plating is used for the joining projection material, as can be seen from the X-ray analysis diagram showing the diffusion state of the joining portion in the high temperature standing state of FIG.
In the diagram showing the conventional example of,
The diffusion of aluminum was stopped, and the layer with the highest palladium concentration appeared in the portion where the gold concentration was the minimum, and the peak of aluminum was observed in this portion, which clearly indicates the formation of the Au-Pd-Al ternary alloy. The formation of such a ternary alloy prevents the joint from cracking. Therefore, the joint strength and electric resistance after being left at a high temperature can be improved. However, as the ratio of palladium or other metal to Au-Pd alloy plated gold applied to the joint projections increases, the joint strength immediately after joining increases. It turned out to be low. FIG. 3 shows the relationship between the concentration of palladium with respect to gold (hereinafter referred to as the palladium concentration) and the turning strength of the joint. According to the graph, when the palladium concentration is 0.005 wt%, the turning strength is 110 g on average, which is almost the same as the case where pure gold is used for the bonding projection.
Next, looking at the case where the palladium concentration is 1 wt%, it can be seen that although the average strength is 20 g, the minimum strength is 0 g, that is, open occurs. When a semiconductor device is manufactured under such circumstances, the manufacturing yield is low, and stable production becomes difficult.

Therefore, Au-Pd applied to the bonding projections
As shown in FIG. 3, the concentration of palladium with respect to gold in the alloy plating needs to be 0.5% or less at which no open occurs. Also, Au-Pd alloy plating is 0.005 wt%
Since it is difficult to obtain a stable supply of the plating solution for depositing the following plating, the practical palladium concentration is 0.01 to
It is 0.5 wt%.

Further, as shown in FIG. 4, when another metal is added to the gold plating, the Vickers hardness becomes high, that is, the plating material becomes hard, and when it is used for the bonding projection, the aluminum electrode 7c of the semiconductor chip is not formed. Although there is a concern that cracks may occur in the insulating film existing in the lower layer, as shown in Table 1, both when palladium and nickel are added to gold, if the atomic ratio to gold is 5% or less, The problem of cracking does not occur at all. Therefore, needless to say, if the palladium concentration is in the range of 0.01 to 0.5 wt%, the insulating film is not cracked.

In the semiconductor device configured as described above,
The aluminum electrode 7c of the semiconductor chip 7 and the Au-Pd plating layer 14 on the protrusion 3b of each inner lead 3a are heated under pressure to fuse and bond to each other.
After heating at 0 ° C for 500 hours, no deterioration of the joint or cracks occurred at all.

[0021]

[Table 1] It has become possible to manufacture semiconductor devices with good yield without the occurrence of open joints.

FIG. 5 is a sectional view showing another embodiment of the present invention. In this embodiment, a Sn plating layer 24 is provided on the surface of the inner lead 3a, and a thickness of partially grown Au—Pd alloy plating in which the ratio of palladium to gold is 0.01% to 0.5% in atomic ratio. 10 μm Au-Pd
The plating layer 25 is grown on another member, and the Au-Pd plating layer 25 is bonded to the Sn plating layer 24 provided on the inner lead 3c by thermocompression bonding to form a bonding projection of the Au-Pd plating material. It is a thing.

FIG. 6 is a sectional view showing another embodiment of the present invention. In this embodiment, a Ni plating layer 34 is also provided on the surface of the inner lead 3a, and the Ni plating layer 34
A thickness obtained by providing an Au plating layer 35 on the top, and partially growing Au-Pd plating in which the ratio of palladium to gold is 0.01 to 0.5% in atomic ratio on one end of the Au plating layer 35. A 10 μm Au-Pd plating layer is provided to
The projections for joining the u-Pd plated material are formed.

Further, the Au-Pd plated layer 36 is grown on another member, and the Au-Pd plated layer 36 is bonded to the gold plated layer 35 provided on the inner lead 3c by thermocompression bonding to bond the Au-Pd plated material. You may form the joining protrusion of.

Part or all of the Au—Pd plated material of the embodiment shown in FIGS. 4 and 5 may be at least one white metal selected from white metals such as indium, platinum and nickel.

[0026]

As described above, a barrier layer of Ni plating or the like is provided on the surface of the inner lead having a projection at the tip, and an Au—Pd plating layer is provided on the barrier layer to bond the projection. Projections or S on the surface of the inner lead
An n-plated layer is provided, a Ni-plated layer is provided on one surface of the tip of the Sn-plated layer or the surface of the inner lead, an Au-plated layer is provided on the Ni-plated layer, and an Au- layer is provided on one side of the tip of the Au-plated layer. Since the Pd-plated material is provided to form the joining protrusion, when the joining protrusion of the inner lead and the aluminum electrode of the semiconductor chip are fused and joined, a ternary alloy of Al-Au-Pd is generated at the joining portion. The generation of such a ternary alloy prevents the occurrence of cracks in the joint portion, can maintain the joint strength in the initial and long-term, and can provide a highly reliable semiconductor device in which the electric resistance does not decrease with high yield. Have.

When part or all of the palladium in the Au-Pd plated layer is made of a white metal other than palladium such as indium, platinum, nickel, etc., cracking of the joint is prevented as in the case of the palladium. There is an effect that the bonding strength can be maintained initially and in the long term, and a highly reliable semiconductor device in which the electric resistance does not decrease can be supplied with high yield.

[Brief description of drawings]

FIG. 1 is a sectional view showing an embodiment of the present invention.

FIG. 2 is an X-ray analysis diagram showing a diffusion state of a joint portion according to an embodiment of the present invention in a high temperature storage state.

FIG. 3 is a graph showing the relationship between the palladium concentration and the turning strength of the joint.

FIG. 4 is a graph showing a relationship between Au-Pd plated layer and Au-Ni plated layer and Vickers hardness.

FIG. 5 is a sectional view showing another embodiment of the present invention.

FIG. 6 is a cross-sectional view showing another embodiment of the present invention.

FIG. 7 is a plan view for explaining a conventional semiconductor device.

8 is a sectional view taken along line VI-VI in FIG.

FIG. 9 is an explanatory diagram showing a manufacturing example of a conventional semiconductor device.

FIG. 10 is a cross-sectional view showing a connection state between inner leads and a semiconductor chip.

FIG. 11 is a graph showing a rate of occurrence of open joints with respect to a high temperature storage time of a conventional example.

FIG. 12 is an X-ray analysis diagram showing a diffusion state in a joint portion of a conventional example in a high temperature standing state.

[Explanation of symbols]

 3 ... Lead 3a ... Inner lead 3b ... Projection 7 ... Semiconductor chip 7a ... Aluminum wiring 7c ... Aluminum electrode 14 ... Ni plating layer 15 ... Au-Pd plating layer

Claims (5)

[Claims] 1. A semiconductor chip is provided in a device hole of an insulating film, and a plurality of aluminum electrodes provided on the semiconductor chip have tips of inner leads protruding into the device hole of a circuit pattern formed on the insulating film. In a semiconductor device formed by joining the joining projections provided on the inner lead, a projection is formed on one surface of the tip of the inner lead by half etching, and a barrier layer such as Ni plating is provided on the surface of the inner lead. The atomic ratio of palladium to gold on the plated layer is 0.01 to
A semiconductor device, wherein a 0.5% Au-Pd plated layer is provided and the projection is used as a bonding projection. 2. The palladium of the Au—Pd plated layer is partially or entirely made of at least one white metal selected from white metals other than palladium such as indium, platinum and nickel. 1. The semiconductor device according to 1. 3. A semiconductor chip is disposed in a device hole of an insulating film, and a plurality of aluminum electrodes provided on the semiconductor chip have tips of inner leads protruding into the device hole of a circuit pattern formed on the insulating film. In a semiconductor device formed by joining the joining projections provided in each of the above, a Sn plating layer or a solder plating layer is provided on the surface of the inner lead, and the ratio of palladium to gold in atomic ratio is on the plating layer. 0.01-0.5% Au
-A semiconductor device characterized in that a Pd plated material is provided and the projection is a bonding projection. 4. A semiconductor chip is arranged in a device hole of an insulating film, and a plurality of aluminum electrodes provided on the semiconductor chip have tips of inner leads protruding into the device hole of a circuit pattern formed on the insulating film. In a semiconductor device formed by joining the joining projections provided on the inner lead, a barrier layer such as Ni plating is provided on the surface of the inner lead, and a noble metal plating layer such as Au plating is provided on the barrier layer, Au having a ratio of palladium to gold of 0.01 to 0.5% in atomic ratio on the noble metal plating layer.
-A semiconductor device characterized in that a Pd plated material is provided and the projection is a bonding projection. 5. A part or all of the palladium of the Au—Pd plated layer is at least one white metal selected from white metals other than palladium such as indium, platinum and nickel. The semiconductor device according to claim 3 or claim 4.