JPH0595272A - Signal drive method for lsi - Google Patents
Signal drive method for lsiInfo
- Publication number
- JPH0595272A JPH0595272A JP3166081A JP16608191A JPH0595272A JP H0595272 A JPH0595272 A JP H0595272A JP 3166081 A JP3166081 A JP 3166081A JP 16608191 A JP16608191 A JP 16608191A JP H0595272 A JPH0595272 A JP H0595272A
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- JP
- Japan
- Prior art keywords
- line
- signal line
- main signal
- level
- changes
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims description 9
- 101150079361 fet5 gene Proteins 0.000 abstract 1
- 230000037431 insertion Effects 0.000 abstract 1
- 238000003780 insertion Methods 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 4
- 230000005540 biological transmission Effects 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000003111 delayed effect Effects 0.000 description 1
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- Electronic Switches (AREA)
- Logic Circuits (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明はＬＳＩの信号駆動方法、
特に、大きなチップ上の長距離のＬＳＩの信号駆動方法
に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an LSI signal driving method,
In particular, it relates to a signal driving method for a long-distance LSI on a large chip.
【０００２】[0002]
【従来の技術】従来、この種の信号駆動方法は抵抗の低
いアルミニウムなどの金属の配線で駆動回路同士を接続
するだけであった。2. Description of the Related Art Conventionally, this type of signal driving method has merely connected the driving circuits to each other by wiring of metal such as aluminum having a low resistance.
【０００３】[0003]
【発明が解決しようとする課題】上述した従来のＬＳＩ
の信号駆動方法は、駆動回路を金属配線でつなぐだけな
ので配線の長さが伸びると抵抗や容量が増える為配線が
伸びる程遅延時間は線長の増分以上に増えてしまうとい
う欠点がある。DISCLOSURE OF THE INVENTION The conventional LSI described above
The signal driving method of (3) has a drawback that the delay time increases more than the increment of the line length as the wiring length increases because the resistance and the capacitance increase as the length of the wiring length increases because the driving circuit is simply connected by the metal wiring.
【０００４】また、長い配線を分割して駆動する場合、
通常インバータを使用する為論理が反転しない様に複数
個駆動回路を入れねばならず、また信号線は分断される
ので、あまりに多く分割すると駆動回路の遅延時間の分
よけいに遅くなってしまうという欠点がある。Further, when driving by dividing a long wiring,
Since a normal inverter is used, multiple drive circuits must be inserted so that the logic will not be inverted, and the signal lines are divided, so if too many divisions are used, the delay time of the drive circuit will be delayed, which is a drawback. There is.
【０００５】さらに、従来の駆動回路では、通常のロジ
ック用の論理素子を使用しているので、駆動能力の調整
は難しい。Further, since the conventional drive circuit uses the logic element for the normal logic, it is difficult to adjust the drive capacity.
【０００６】[0006]
【課題を解決するための手段】本発明のＬＳＩの信号駆
動方法は、信号線を伝える主信号線と、主信号線より若
干遅れて時間を伝える副信号線と、主信号が“１”の時
ＯＮする主信号線のプルアップ用ＮＭＯＳＦＥＴと、そ
のＮＭＯＳＦＥＴと電源線の間に直列に接続している副
信号が“１”になるときＯＮになるＮＭＯＳＦＥＴと、
主信号が“０”の時ＯＮする主信号線のプルダウン用Ｐ
ＭＯＳＦＥＴと、そのＰＭＯＳＦＥＴとグランド線の間
に直列に接続している副信号が“０”のときＯＮになる
ＰＭＯＳＦＥＴを有している。According to a method of driving an LSI of the present invention, a main signal line for transmitting a signal line, a sub signal line for transmitting time slightly later than the main signal line, and a main signal of "1" are provided. A pull-up NMOSFET for the main signal line that is turned on when the sub-signal connected in series between the NMOSFET and the power supply line is "1", and an NMOSFET that is turned on when the sub-signal is "1".
P for pulling down the main signal line that turns ON when the main signal is "0"
It has a MOSFET and a PMOSFET connected in series between the PMOSFET and the ground line and turned on when the sub signal is "0".
【０００７】[0007]
【実施例】図１は本発明の一実施例を示す回路図であ
る。本発明の駆動回路２０は、ドライバー３１からの信
号を伝える主信号１と、ドライバー３１から遅延回路３
２を通って主信号線１と逆相でしかも若干遅れて信号を
伝える副信号線２と、主信号線１と副信号線２のデータ
でＯＮ ＯＦＦするＭＯＳＦＥＴ５〜８及び信号の低レ
ベルを保持する為のグランド線４と高レベルを保持する
為の電源線３とから構成される。FIG. 1 is a circuit diagram showing an embodiment of the present invention. The drive circuit 20 of the present invention includes a main signal 1 for transmitting a signal from the driver 31 and a delay circuit 3 from the driver 31.
Holds a sub-signal line 2 which transmits a signal in a phase opposite to that of the main signal line 1 through 2 and a slight delay, MOSFETs 5 to 8 which are turned on / off by the data of the main signal line 1 and the sub-signal line 2, and a low level of the signal. And a power supply line 3 for holding a high level.
【０００８】ドライバー３１の入力が“１”の場合、主
信号線１，副信号線２はそれぞれ“０”，“１”とな
り、ＰＭＯＳＦＥＴ７とＮＭＯＳＦＥＴ５がＯＮ，ＰＭ
ＯＳＦＥＴ８とＮＭＯＳＦＥＴ６がＯＦＦした状態であ
り、主信号線１はドライバー３１のみによってレベルを
保持されている。ドライバー３１の入力が“１”から
“０”に変化すると、まず主信号線１が“０”から
“１”になりＮＭＯＳＦＥＴ６がＯＮに変化し、主信号
線１と電源線３が接続することになり、主信号線１の変
化を助ける。When the input of the driver 31 is "1", the main signal line 1 and the sub signal line 2 are "0" and "1", respectively, and the PMOSFET 7 and the NMOSFET 5 are ON and PM.
The OSFET 8 and the NMOSFET 6 are in the OFF state, and the level of the main signal line 1 is held only by the driver 31. When the input of the driver 31 changes from "1" to "0", the main signal line 1 first changes from "0" to "1", the NMOSFET 6 changes to ON, and the main signal line 1 and the power supply line 3 are connected. And helps change the main signal line 1.
【０００９】そして、副信号線２が遅延回路３２によっ
て若干遅れて“１”から“０”に変化するとＮＭＯＳＦ
ＥＴ５がＯＦＦするので主信号線１は再びドライバー３
１でのみレベルを保持することになる。また、ＰＭＯＳ
ＦＥＴ８はＯＮになる。従って次に主信号線１が“１”
から“０”に変化したら、今度は主信号線１とグランド
４を接続することになる。When the sub-signal line 2 changes from "1" to "0" with a slight delay due to the delay circuit 32, the NMOSF
ET5 is turned off, so main signal line 1 is again driver 3
Only 1 will hold the level. Also, the PMOS
FET8 is turned on. Therefore, next, the main signal line 1 is "1".
When it changes from "0" to "0", the main signal line 1 and the ground 4 are connected this time.
【００１０】従って主信号線１が変化してＭＯＳＦＥＴ
がＯＮすると主信号線１は急速にレベルを変化すること
になる。そして遅れて副信号線２が変化すると主信号線
１が今度は逆方向に変化する為の準備状態となる。Therefore, the main signal line 1 changes and the MOSFET
When is turned on, the level of the main signal line 1 changes rapidly. Then, when the sub signal line 2 changes after a delay, the main signal line 1 is now in a ready state for changing in the opposite direction.
【００１１】図２は、本発明の一使用例のブロック図で
ある。送信回路３０からの信号を駆動回路Ａ２１と駆動
回路Ｂ２２で駆動して受信回路４０に信号を伝えてい
る。駆動回路Ａ２１，駆動回路Ｂ２２はともに図１の駆
動回路２０と同じものである。このように送信回路３０
と受信回路４０の間が遠く１つの駆動回路のみでは能力
が足りない場合、複数個の駆動回路を設けることによ
り、適正な駆動能力を得ることができる。FIG. 2 is a block diagram of one use example of the present invention. The drive circuit A21 and the drive circuit B22 drive the signal from the transmission circuit 30 to transmit the signal to the reception circuit 40. The drive circuit A21 and the drive circuit B22 are the same as the drive circuit 20 of FIG. In this way, the transmission circuit 30
When the distance between the receiving circuit 40 and the receiving circuit 40 is far from each other and the ability is insufficient with only one driving circuit, it is possible to obtain an appropriate driving ability by providing a plurality of driving circuits.
【００１２】図２の様に駆動回路を等間隔に並べる必要
はない。本発明による駆動回路は、入力と出力は同相で
あり送信回路３０と受信回路４０の間に適正な数の駆動
回路を設けることができる。また、主信号線１と駆動回
路２０の交点は交点Ａ１０と交点Ｂ１１のみであり、実
質１点で主信号線１と接続しているので、たやすく設計
変更をして駆動回路２０を追加することもできる。It is not necessary to arrange the drive circuits at equal intervals as shown in FIG. In the drive circuit according to the present invention, the input and the output are in phase, and an appropriate number of drive circuits can be provided between the transmission circuit 30 and the reception circuit 40. Further, the main signal line 1 and the drive circuit 20 intersect only at the intersection points A10 and B11, and since the main signal line 1 is connected at substantially one point, the design circuit can be easily changed to add the drive circuit 20. You can also
【００１３】図３は本発明の駆動回路の詳細を示す斜視
図である。下地に、本発明の駆動回路を構成するＭＯＳ
ＦＥＴ５〜８のチャネルを構成する部分のゲート幅５０
を十分長くしたものを用意しておくことにより、主信号
線１，副信号線２の金属配線部分の長さを調節するだけ
で構成するＭＯＳＦＥＴのゲート幅５０を変えられるの
で適正な能力を持った駆動回路を作ることができる。FIG. 3 is a perspective view showing the details of the drive circuit of the present invention. MOS which constitutes the drive circuit of the present invention on the base
Gate width 50 of the part that constitutes the channel of FETs 5-8
By preparing a sufficiently long cable, the gate width 50 of the MOSFET to be composed can be changed by simply adjusting the length of the metal wiring portion of the main signal line 1 and the sub signal line 2, so that it has an appropriate capability. Drive circuit can be made.
【００１４】[0014]
【発明の効果】以上説明したように本発明は、主信号が
“１”と時ＯＮする主信号線のプルアップ用ＮＭＯＳＦ
ＥＴとそのＮＭＯＳＦＥＴと電源線の間に直列に接続し
ている副信号が“１”になるときＯＮになるＮＭＯＳＦ
ＥＴと、主信号が“０”の時ＯＮする主信号線のプルダ
ウン用ＰＭＯＳＦＥＴと、そのＰＭＯＳＦＥＴとグラン
ド線の間に直列に接続している副信号が“０”のときＯ
ＮになるＰＭＯＳＦＥＴにより駆動回路を構成すること
により、副信号を逆相にして少し遅らすと、主信号線の
信号変化を助けることができる効果がある。As described above, according to the present invention, the pull-up NMOSF of the main signal line is turned on when the main signal is "1".
NMOSF that turns on when the sub signal connected in series between ET and its NMOSFET and the power supply line becomes "1"
ET, a pull-down PMOSFET for the main signal line that turns ON when the main signal is "0", and O when the sub-signal connected in series between the PMOSFET and the ground line is "0".
By constructing the drive circuit with the PMOSFET which becomes N, and making the sub-signal have a reverse phase and delaying it a little, it is possible to help the signal change of the main signal line.
【００１５】さらに、本発明の駆動回路は、入力出力が
同相であり、しかも、主信号線と１ケ所で接続するだけ
でよいので、たやすく長い配線の途中に設け適正な駆動
能力を得ることができる。Further, in the drive circuit of the present invention, since the input and output are in phase, and moreover, it is only necessary to connect to the main signal line at one place, it is easy to provide in the middle of a long wiring and obtain an appropriate drive capability. You can
【００１６】また、本発明の駆動回路のＭＯＳＦＥＴの
ゲート幅を十分長くした下地を用意しておくことによ
り、適正な駆動能力を得ることができる。Further, by preparing an underlayer in which the gate width of the MOSFET of the drive circuit of the present invention is sufficiently long, it is possible to obtain an appropriate drive capability.
【図１】本発明の一実施例を示す回路図である。FIG. 1 is a circuit diagram showing an embodiment of the present invention.
【図２】本発明の一使用例のブロック図である。FIG. 2 is a block diagram of one use example of the present invention.
【図３】本発明の駆動回路の詳細を示す斜視図である。FIG. 3 is a perspective view showing details of a drive circuit of the present invention.
１ 主信号線 ２ 副信号線 ３ 電源線 ４ グランド線 ５，６ ＮＭＯＳＦＥＴ ７，８ ＰＭＯＳＦＥＴ ９ Ｎウェル領域 １０ 交点Ａ １１ 交点Ｂ ２０ 駆動回路 ２１ 駆動回路Ａ ２２ 駆動回路Ｂ ３０ 送信回路 ３１ ドライバー ３２ 遅延回路 ４０ 受信回路 ５０ ゲート幅 1 Main Signal Line 2 Sub Signal Line 3 Power Line 4 Ground Line 5, 6 NMOSFET 7, 8 PMOSFET 9 N Well Region 10 Intersection A 11 Intersection B 20 Drive Circuit 21 Drive Circuit A 22 Drive Circuit B 30 Transmitter Circuit 31 Driver 32 Delay Circuit 40 Receiver circuit 50 Gate width
Claims (3)
若干遅れて信号が送られる副信号線と、主信号線と副信
号線の信号の到達時間の差の間主信号線のデータ変化を
助ける手段を有することを特徴とするＬＳＩの信号駆動
方法。1. Data of a main signal line for transmitting a signal, a sub signal line to which a signal is sent with a slight delay from the main signal line, and a main signal line during a difference in arrival time of signals of the main signal line and the sub signal line. A signal driving method for an LSI, comprising means for assisting change.
に複数個設ける請求項１記載のＬＳＩの信号駆動方法。2. The signal driving method for an LSI according to claim 1, wherein a plurality of driving circuits using the means are provided on a signal wiring.
ＯＳＦＥＴのゲート幅を自由に設定する手段を含む請求
項１記載のＬＳＩの信号駆動方法。3. An M constituting a drive circuit using the means.
The method of driving an LSI signal according to claim 1, further comprising means for freely setting the gate width of the OSFET.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3166081A JPH0595272A (en) | 1991-07-08 | 1991-07-08 | Signal drive method for lsi |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3166081A JPH0595272A (en) | 1991-07-08 | 1991-07-08 | Signal drive method for lsi |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0595272A true JPH0595272A (en) | 1993-04-16 |
Family
ID=15824631
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3166081A Pending JPH0595272A (en) | 1991-07-08 | 1991-07-08 | Signal drive method for lsi |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0595272A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1311636C (en) * | 2002-08-07 | 2007-04-18 | 日本电信电话株式会社 | Drive circuit |
-
1991
- 1991-07-08 JP JP3166081A patent/JPH0595272A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1311636C (en) * | 2002-08-07 | 2007-04-18 | 日本电信电话株式会社 | Drive circuit |
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