JPH0595367A - Cell multiple bus communication control system - Google Patents

Abstract

PURPOSE:To control a bus transmission and reception by a cell unit fairly and without delay in a cell multiple bus communication control system. CONSTITUTION:Each LIF(Line interface circuit) 100 multiplexes a cell transmission right request from a self line to a line 202 by a preliminarily fixed timing from a number of cell request part 40 to a central processing part 200 and outputs the request The central processing part 200 receiving this cell transmission right request arbitrates a transmission permission from the number of cell and a priority in a number of cell request detection part 50 and the transmission permission is multiplexed from a permission data transmission part 60 to a line 201 and transmits the permission. When each LIF 100 detects the transmission permission to self circuit in a permission/timing detection part 30, it performs a transmission instruction to a bus 101 of the cell for a cell transmission part 20.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a cell multiplex bus communication control system, and more particularly to a cell multiplex bus communication control system for controlling communication between a line interface terminating a terminal accommodation line and a relay line and a cell multiplex bus.

[0002]

2. Description of the Related Art A conventional cell multiplex bus communication control system is shown in FIG.
There is a system as shown in FIG. FIG. 4 shows a channel setting method. A time division bus to which a plurality of line interface circuits (LIFs) are connected is divided into units called time slots, and data transmission and reception to and from the time division bus are central. Of the CPU, and determines which time slot is used by which line interface circuit.

FIG. 5 shows a time-division bus centralized arbiter control system in which line interface circuits are connected by a common bus, and data is exchanged in units of frames and packets.

FIG. 6 shows a DQDB method (Distributed Queue Dual).
Bus) system, and each bus is a cell multiplex bus of a number + octet unit. The data transmission to this bus is SG
The line interface circuit, which has received a cell, which is called an empty cell and does not contain data, sent from the (slot generator), can perform data transmission.

However, the closer to SG, the higher the probability of empty cell acquisition is, so arbitration of cell acquisition is performed between the line interface circuits in order to eliminate unfairness.

[0006] The bus communication control method in the above-mentioned conventional channel setting method has a drawback in that it is necessary to perform channel setting or centralized channel management by software in advance during communication. Further, the time division bus centralized arbiter control system has a drawback that cells cannot be exchanged and other circuits are put in a waiting state during transmission of a frame or packet having a long data length.

In the bus communication control method in the DQDB method, cell units can be exchanged, but empty cell acquisition competition is distributed and controlled in each line interface circuit, and the control is performed using the cell multiplex bus. The amount of hardware is large, and there is a drawback in that it is not possible to completely eliminate inequity when the traffic increases transiently.

[0008]

SUMMARY OF THE INVENTION It is an object of the present invention to provide a cell multiplex bus communication control system capable of performing cell-based communication fairly and without delay.

[0009]

According to the present invention, a cell multiplex bus for transmitting a predetermined data capacity as an exchange unit cell and an individual address are respectively assigned to terminate a terminal accommodating line and to connect between the cell multiplex bus and the line. A plurality of line interfaces that perform the interface function of, and a transmission right request bus that is commonly connected to these line interfaces and that transmits a transmission right request of cells from the line to the cell multiplex bus, which is generated from these line interfaces, A cell multiplex bus communication control system including a central processing unit that generates a transmission permission in response to the transmission right request and a transmission permission bus that transmits the transmission permission to the line interface, wherein each of the line interfaces The transmission right request is provided for the number of cells to be transmitted to the cell multiplex bus and the priority information thereof. And means for sending to the transmission right request bus, and means for arbitrating transmission permission according to the priority information and the number of cells in the transmission right request, and means provided for the central processing unit. Means for sending a transmission permission including a transmission permission address to the transmission permission bus based on the arbitration result, and the line interface, each of which is provided with the transmission permission and the transmission permission address matches the own address. And means for transmitting a cell from the line to the cell multiplex bus, and means for receiving a cell from the cell multiplex bus and taking in a cell matching the own address, which is provided in each of the line interfaces. A cell multiplex bus communication control system characterized by including the above is obtained.

[0010]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a system block diagram of an embodiment of the present invention, (A) is a schematic diagram thereof, and (B) is a detailed diagram thereof.

The type of cell multiplex bus in this example is a type in which one end of the transmission side bus 101 and one end of the reception side bus 102 are connected.

A physical address is individually assigned to each of the plurality of line interface circuits 100, and terminal lines and relay lines connected thereto are terminated, and an interface between these lines and the cell multiplex buses 101 and 102. It functions.

A central processing unit 200 is provided to process a transmission right request from these line interface circuits 100 and give a transmission permission. The transmission right request is sent to the transmission right request bus 202, and the transmission permission is sent to the transmission permission bus 201.
Sent to.

Each of the line interface circuits 100 is
Cell transmission unit 2 for transmitting cells from the line to the cell multiplex bus
0 and a cell receiving unit 1 that receives cells from the cell multiplex bus
0, a cell number request unit 40 that generates a transmission right request for requesting transmission of cells to the bus, and a permission to detect transmission permission from the central processing unit and control transmission of cells to be transmitted to the cell multiplex bus It has a timing detection unit 30.

The central processing unit 200 receives a transmission right request from each line interface circuit 100 and arbitrates the transmission right in accordance with a predetermined priority processing system, and a cell number request detecting unit 50 and a permission data transmission for giving a transmission permission. It includes a unit 60 and a timing synchronization unit 70 that determines various operation timings.

FIG. 2 is a block diagram showing further details of FIG. 1, and the same parts as in FIG. 1 are designated by the same reference numerals.
FIG. 3 is a timing chart showing the operation.

When data arrives from the terminal line and the relay line connected to the line interface circuit 100, the cell disassembling unit 22 in the cell transmitting unit 20 disassembles the unit cell into a predetermined formatted unit cell shown in FIG. It To the header portion of the cell, the address of the communication destination determined by the CPU (not shown) and the frame check sequence bit are added for each cell via the signal line 103.

Simultaneously with this disassembly, a cell number acquisition request is sent to the counter section 41 in the cell number request section 40 via the line 105, and at the same time, the cell number and request priority (priority) are sent via the line 106. It is sent to the cell number register 43.

In the counter section 41, the transmission timing is created by the clock (CLK) and the frame pulse signal (FH) transmitted by the timing synchronizing section 70 in the central processing section 200, based on the physical address.

In the request sending unit 42, the number of cells and the priority are formatted via the line 107, and the transmission right request bus is sent at the timing of the line 108 sent by the counter unit 41.
The cell number request is sent to 202 (see the chart of the transmission right request bus of 202 in FIG. 3).

As shown in the transmission right request bus 202 of FIG.
The cell number acquisition requests of the line interface circuit 100 are multiplexed and sent to the request detection unit 52 of the central processing unit 200.
The request detection unit 52 serial-parallel converts the data received in the cell number acquisition request and sends the data to the arbitration unit 51.

The arbitration unit 51 selects one of a plurality of cell acquisition requests based on the priority and the number of cells, for example, using the rotation priority control method, and permits the physical address to be granted via the line 204. A format unit 61 in the transmission unit 60, a cell timing unit 72 in the timing synchronization unit 70
Is continuously transmitted in synchronism with the timing of transmission via line 203. Then, the arbitration unit 51 starts counting down the number of cells of the request for which the permission is given.

As shown in FIG. 3, while permission is being sent to A, B is being sent.
If there is a high priority request from B, the permission to B is prioritized, and after the permission is completed, the permission to A is sent again.

In the format section 61, as shown in FIG. 3, a flag, an address and a flag are formed in a predetermined format in order, and are transmitted to the transmission permission signal bus 201 via the permission transmission section 62 based on the timing of reception via the line 203. .. The format interval of this transmission enable signal bus 201 is a cell multiplex bus.
Similar to 101 and 102.

Then, the permission / timing detection unit 32 of the permission / timing detection unit 30 in the line interface circuit 100 receives the physical address from the central processing unit 200 via the permission reception unit 33, and detects the match / mismatch. If they match, the bus acquisition signal is immediately transmitted to the cell disassembly unit 22 via the timing unit 31 via the line 104. The bus acquisition signal indicates the length of a unit cell and the transmission timing of the cell multiplex bus 101.

Upon receiving the bus acquisition signal, the cell disassembling unit 22 receives the signal and, via the bus transmitting unit 21, sends the cell multiplex bus 10
Send cells to 1.

In the cell receiving unit 10, the address filter unit 12 detects, via the bus receiving unit 11, the addresses of all the cells with the addresses preset by the CPU. The cell is taken in and immediately sent to the cell assembly section 13. The address check timing of the address filter unit 12 is the same as the timing unit 3
1 is being sent out via line 106.

Then, the cell assembling unit 13 assembles cells that arrive in order and sends them to the terminal line and the relay line. Through the above series of control, the terminal line and the relay line can communicate with each other.

[0030]

As described above, according to the present invention, in the cell multiplex bus communication control, the cell multiplex bus acquisition request of the plurality of line interface circuits is made by the cell number request and the priority request, whereby the line interface circuit is obtained. , And the complexity of requesting permission on a cell-by-cell basis is also eliminated.

Then, it is possible to send a permission by the transmission permission signal bus, or to send a cell having a short data length by sending an interrupt while transmitting a cell having a long data length, which makes the bus efficient. In addition, the delay can be reduced.
Further, in terms of software, only address setting is performed, and high-speed processing can be realized.

[Brief description of drawings]

FIG. 1A is a schematic system diagram of an embodiment of the present invention,
(B) is a detailed system block diagram thereof.

2 is a block diagram of an embodiment of the present invention, showing further details of FIG. 1. FIG.

FIG. 3 is a time chart showing the operation of the embodiment of the present invention.

FIG. 4 is a block diagram showing an example of a conventional channel setting method.

FIG. 5 is a block diagram showing an example of a conventional time division centralized arbiter control method.

FIG. 6 is a block diagram showing an example of a conventional DQDB system.

[Explanation of symbols]

 10 Cell Reception Section 11 Bus Reception Section 12 Address Filter Section 13 Cell Assembly Section 20 Cell Transmission Section 21 Bus Transmission Section 22 Cell Disassembly Section 30 Permission Timing Detection Section 31 Timing Section 32 Permission Detection Section 33 Permission Reception Section 40 Cell Number Request Section 41 Counter unit 42 Request transmission unit 43 Cell number register 100 Line interface circuit 101,102 Cell multiplex bus 200 Central processing unit 201 Transmission permission bus 202 Transmission right request bus

Continuation of front page (51) Int.Cl. ⁵ Identification number Office reference number FI technical display area H04L 12/40

Claims (1)

[Claims] 1. A plurality of cell multiplex buses each of which transmits a predetermined data capacity as an exchange unit cell and individual addresses are respectively assigned to terminate a terminal accommodating line, and to form an interface function between the cell multiplex bus and the line. Line interface, and a transmission right request bus which is commonly connected to these line interfaces and which transmits a transmission right request of a cell from the line to the cell multiplex bus, which is generated from these line interfaces, and responds to the transmission right request. A cell multiplex bus communication control system including a central processing unit that generates a transmission permission and a transmission permission bus that transmits the transmission permission to the line interface, the cell multiplexing bus communication control system being provided in each of the line interfaces. The number of cells to be transmitted to the bus and priority information thereof are used as the transmission right request, and the transmission right is required. Means for sending to the request bus, means for arbitrating the transmission permission according to the priority information and the number of cells in the transmission right request, provided for the central processing unit, and means provided for the central processing unit. Means for transmitting a transmission permission including a transmission permission address to the transmission permission bus based on the above, and the cell multiplexing when the transmission permission is received and the transmission permission address matches its own address. A means for transmitting a cell from the line to a bus, and means for receiving a cell from the cell multiplex bus, which is provided in each of the line interfaces, and takes in a cell that matches the own address. Cell multiplex bus communication control system.