JPH0596780A - Image recorder - Google Patents

Abstract

(57) [Abstract] [Object] To provide an image recording apparatus capable of obtaining a high-quality halftone image at low cost by performing PWM control of a fine pulse width step using a clock having a relatively low frequency. .. [Structure] Multivalued image data VDO representing gradation is latched by a latch circuit 25, gamma-corrected by a ROM 26, and input to a decoder 30 via data latches 1 and 2. The clock phase control circuit 31 generates a plurality of clocks K0 to K3 in which the phase of VCLKN is shifted. The decoder 30 outputs a code signal representing a clock selection and a clock to the set signal generation circuit 32 and the reset signal generation circuit 33 based on the input data. The set / reset signal generation circuits 32 and 33 perform printing with a predetermined pulse width based on the input code signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image recording device such as a laser beam printer. In particular, the present invention relates to an image recording apparatus which receives a multi-valued image signal and performs high-quality multi-tone halftone printing based on the signal.

[0002]

2. Description of the Related Art In recent years, laser beam printers using electrophotography have been used in computer output devices, facsimile output units, or so-called digital copying machines for printing image data read from an image scanner.

The laser beam printer used for these prints at a resolution of, for example, 300 dots / inch. Therefore, in order to record a halftone image using a conventional laser beam printer, for example, 300 dots /
A method of recording using a dither method or a density pattern method has been adopted as a conventionally known halftone image recording method using a dot of about inch as a minimum dot unit.

However, in the above-mentioned conventional halftone image recording method, in order to express the density of 64 gradations, for example, a dot matrix composed of 64 dots consisting of 8 dots in the main scanning × 8 dots in the sub scanning is used for the halftone. Since it is expressed as a pixel unit for expression, the resolution of halftone pixels becomes rough.
In the above case, the resolution was significantly reduced to 37.5 pixels / inch, which was not satisfactory in terms of image quality (hereinafter, the pixel / inch is referred to as "line"). If the resolution is increased to 150 lines, the density that can be expressed becomes 4 gradations, and conversely, if the line is 75 lines, the density that can be expressed is 1.
There is a contradictory relationship between the resolution and the expressible density such as 6 gradations.

Generally, a resolution of 200 lines or more and 64
It can be said that it is a relatively high-quality halftone image when the density expression higher than the gradation is possible.

In recent years, a laser beam printer having a resolution of 600 dots / inch has been announced or commercialized. Even when this printer is used, the resolution of the halftone image is 75 lines to express the density of 64 gradations, and although the improvement is made, the image quality is not yet sufficient.

As a first method for improving the above-mentioned inconvenience, a digital multi-valued image signal is received and temporarily converted into an analog signal, and a separately generated periodic analog voltage signal of a triangular wave or a sawtooth wave and the analog signal. There is known a method of obtaining a halftone image by generating a binarized signal in which pulse width modulation is performed by comparing and with a voltage level, and driving a laser by the signal to record.

A method of this kind will be briefly described with reference to FIG. In the figure, a triangular wave voltage signal for reference that is periodically generated and an input density voltage signal obtained by digital-analog converting the input digital image data signal are compared in voltage by an analog voltage comparator, and the comparison result shows A laser is driven by the obtained pulse signal to print a halftone image.

However, the above method requires the use of expensive circuit elements in order to handle high-speed analog signals. In addition, a circuit that requires a volume to adjust the signal voltage in order to correct the variation in the waveform voltage accuracy of the triangular wave, or the element width changes due to environmental changes such as temperature, resulting in a change in the pulse width. There was a problem that the above stability was not sufficient.

In particular, the slope portion of the triangular wave or sawtooth wave is not linear because the charge / discharge using the capacitor is used, and even if the voltage at the start and end points of the waveform is adjusted, It is difficult to eliminate the bending distortion that occurs, and this distortion causes the deterioration of the image quality in the halftone density expression that occurs from the electric circuit. This state is schematically shown in FIG. In the figure, represents the ideal characteristic of the input image density versus the output image density, and represents the characteristic in the conventional example of the triangular wave voltage system. In the present embodiment described below, the following characteristics can be obtained.

Further, since many so-called discrete parts such as resistance elements and capacitors are required in constructing the circuit, it is difficult to integrate the circuit with a small number of parts.

Further, there has been proposed a method of setting a count number of a counter which receives a digital multi-valued signal and counts a high frequency clock according to the digital signal, and digitally obtains a pulse width corresponding to the count number. .. This method has more stable reproducibility of the pulse width than the above-mentioned analog type pulse width modulation circuit, and is stable even with environmental changes such as temperature.

[0013]

However, since the method of digitally obtaining the pulse width adopts the method of counting the clock, there is a limit frequency in the operation of the digital circuit. Therefore, the minimum step width of the obtained pulse width is defined by the limit frequency of the digital circuit. Therefore, there is a limit in improving the gradation.

Many laser beam printers currently available on the market having a printing speed of 300 dots / inch and 8 sheets / minute sell a large number of application software for handling character text. Therefore, according to the embodiment of the present invention, the resolution of the character text, that is, the binary image (300 dots / inch) and the resolution of the multi-valued image obtained by the pulse width modulation (3) are considered in consideration of the compatibility with the application software.
(00 pixels / inch) can be made the same.
As a result, the resolution map on the memory of the binary image and the multivalued image on the host computer connected to the laser beam printer can be made the same, and the ease of handling the data becomes possible.

30 using the laser beam printer
In order to reproduce a halftone image of 0 line, an image clock corresponding to 300 dots / inch can be divided into 64 equal to 1.8 MHz to create 64 step gradations.

However, in this case, the frequency of the clock to be counted by the counter for setting the pulse width is 11
Since the frequency becomes 5.2 MHz, it is difficult or impossible to construct a circuit with standard logic such as TTL or CMOS, and expensive ECL logic had to be constructed. Furthermore, even if the ECL logic is difficult to realize, it is difficult or impossible to print a halftone image having more gradation than 128 steps.

The present invention eliminates the above-mentioned drawbacks of the prior art. By performing PWM control of a fine pulse width step using a clock having a relatively low frequency, a high quality halftone image can be obtained at low cost. An image recording apparatus that can be obtained is provided.

[0018]

In order to achieve the above-mentioned object, the present invention has a phase difference at a predetermined frequency and a conversion means for converting input image data representing a gradation into a code signal representing a pulse width. Generating means for generating a plurality of clock signals, selecting means for selecting one of the plurality of clock signals based on the code signal, and counting means for counting the selected clock signals based on the code signal A pulse generating means for generating a pulse width modulation signal having a predetermined pulse width in accordance with the output of the counting means, and not simply counting clocks when performing digital pulse width modulation, but in advance A plurality of clocks having different phases are generated and pulse width modulation is performed using the clocks. As a result, the pulse width modulation circuit having a higher number of gray scales can be digitally performed by using TTL logic or CMOS logic, and the pulse width modulation circuit can be realized by an integrated circuit such as a gate array. It is possible to inexpensively realize a stable circuit capable of obtaining a high-quality image.

[0019]

Embodiments of the present invention will be described below with reference to the accompanying drawings.

1 and 2 are views showing an engine portion of a laser beam printer to which an embodiment of the present invention is applied.

In the figure, 1 is a recording medium,
A paper cassette 2 holds the paper 1. A sheet feeding unit 3 separates only the uppermost sheet of the sheets 1 placed on the sheet cassette 2 and conveys the leading edge of the separated sheet to a position of the sheet feeding rollers 4 and 4'by a driving unit (not shown). The paper cam rotates intermittently every time the paper is fed, and one paper is fed corresponding to one rotation.

Reference numeral 18 denotes a reflection type photo sensor, which detects the paper absence by detecting the reflected light of the paper 1 through a hole 19 provided at the bottom of the paper cassette 2.

When the paper is conveyed to the roller portion by the paper feed cam 3, the paper feed rollers 4 and 4'rotate while gently pressing the paper 1 to convey the paper 1. When the sheet 1 is conveyed and the leading end reaches the position of the registration shutter 5, the conveyance of the sheet 1 is stopped by the registration shutter, and the paper feed rollers 4 and 4 ′ generate a conveyance torque while slipping on the sheet 1. Keep rotating. In this case, by driving the registration solenoid 6 to release the registration shutter 5 in the upward direction, the paper 1
Is fed to the transport rollers 7, 7 '. The registration shutter 5 is driven in synchronization with the transmission timing of the image formed by the laser beam 20 being formed on the photosensitive drum 11. 21 is a photo sensor,
It is detected whether or not the sheet 1 exists at the location of the resist shutter 5.

Reference numeral 52 is a rotary polygon mirror, which is driven by a motor 53. The laser driver 50 drives the semiconductor laser 51 according to a pulse width modulation signal sent from a halftone signal processing circuit described later.

The laser beam 20 from the semiconductor laser 51 driven by the laser driver 50 is scanned in the main scanning direction by the rotary polygon mirror 52, and the f-θ lens 56 disposed between the rotary polygon mirror 52 and the reflection mirror 54 is moved. After that, it is guided onto the photosensitive drum 11 via the reflection mirror 54, forms an image on the photosensitive drum 11, scans in the main scanning direction, and forms a latent image on the main scanning line 57. In this case, 300
When the printing density is 8 dots / minute (: A4 size or letter size) with a dot / inch printing density, the laser lighting time for recording one dot is about 540 nanoseconds.
When the printing density is 600 dots / inch and the printing speed is 8 sheets / minute, the laser lighting time for recording one dot is about 135 nanoseconds.

The beam detector 55 arranged at the scanning start position of the laser beam 20 is
By detecting 0, the BD signal is detected as a synchronizing signal for determining the image writing timing in the main scanning direction.

After that, the sheet 1 is sent to the photosensitive drum 11 by obtaining the carrying torque by the carrying rollers 7, 7'instead of the paper feeding rollers 4, 4 '. A latent image is formed on the surface of the photosensitive drum 11 charged by the charger 13 by exposure to the laser beam 20. The latent image exposed by the laser beam is visualized as a toner image by the developing device 14, and then the toner image is transferred to the sheet 1 by the transfer charger 15.
Is transferred to the paper surface of. A cleaner 12 cleans the surface of the drum after it is transferred to the paper 1.

The sheet 1 having the toner image transferred thereon is then fixed with the toner images by the fixing rollers 8 and 8 ', and is ejected onto the ejection tray 10 by the ejection rollers 9 and 9'.

Reference numeral 16 denotes a paper feed table, which allows not only paper feed from the paper cassette 2 but also manual paper feed from the paper feed tray 16 one by one. The paper fed to the manual paper feed roller 17 on the paper feed tray 16 by manual feeding is lightly pressed by the manual paper feed roller 17 and the leading end of the paper is a registration shutter like the paper feed rollers 4 and 4 '. It is conveyed until it reaches 5, and slips there. The subsequent transport sequence is exactly the same as when feeding from a cassette.

The fixing roller 8 contains a fixing heater 24, and the surface temperature of the fixing roller 8 is controlled to a predetermined temperature based on the temperature detected by the thermistor 23 which makes a slip contact with the roller surface of the fixing roller. The toner image of No. 1 is thermally fixed. A photo sensor 22 detects whether or not there is a sheet at the positions of the fixing rollers 8 and 8 '.

The printer is connected to the controller through the interface means, and receives a print command and an image signal from the controller to perform a print sequence. The signals transmitted and received by this interface means will be briefly described below.

FIG. 3 is a diagram showing interface signals between the printer engine section and the controller for generating image data. Each of the interface signals shown in the figure will be described below.

The PPRDY signal is a signal sent from the printer to the controller, and is a signal notifying that the printer is in an operable state after the printer is powered on.

The CPRDY signal is a signal sent from the controller to the printer, and is a signal notifying that the controller is powered on and the controller is in an operable state.

RDY signal-a signal sent from the printer to the controller, which is the P
It is a signal indicating that the printing operation can be started or continued at any time when the RNT signal is received. For example, when the printing operation cannot be executed due to the paper cassette 2 running out of paper, the signal becomes "false".

PRNT signal-a signal sent from the controller to the printer, which is a signal for instructing the start of the print operation or the continuation of the print operation. Upon receiving the signal, the printer starts the printing operation.

VSREQ signal-a signal sent from the printer to the controller. When the RDY signal sent from the printer is in the "true" state, the controller makes the PRNT signal "true" to perform the printing operation. This is a signal indicating that the printer is ready to receive image data after the start instruction is sent. In this state, it becomes possible to receive the VSYNC signal described later.

The VSYNC signal is a signal sent from the controller to the printer, and is a signal for synchronizing the sending timing of image data in the sub-scanning direction. Due to this synchronization, the toner image formed on the drum is transferred onto the paper in synchronization with the paper in the sub-scanning direction. This relationship is shown in FIG. In the figure, the image signal VDO is started to be transmitted in synchronization with the BD signal, which will be described later, in the main scanning direction from the time point T1 after the leading edge of the VSYNC signal.

BD signal-a signal sent from the printer to the controller, which is a signal for synchronizing the sending timing of image data in the main scanning direction. Due to this synchronization, the toner image formed on the drum is transferred onto the paper in synchronization with the paper in the sub-scanning direction.
The signal indicates that the scanning laser beam is at the starting point of main scanning. This relationship is shown in FIG. In the figure, the image signal VDO is started to be transmitted when the time T2 has elapsed from the leading edge of the BD signal.

VDO signal-a signal sent from the controller to the printer, which is a signal for transmitting image data to be printed. The signal is VCLK which will be described later.
It is sent in synchronization with the signal. The controller receives code data such as a PCL code transmitted from the host device, generates a character bit signal generated from a character generator corresponding to the code data, or a vector such as a Postscript code transmitted from the host device. A code is received, graphic bit data corresponding to the code is generated, or multivalued data read from an image scanner is generated, and these data are transmitted to the printer as a 6-bit VDO signal of VDO0 to VDO5. The printer modulates the laser according to the signal and prints. Although the VDO signal is 6 bits here, it goes without saying that 8 bits or 10 bits can be applied without departing from the object of the present invention.

VCLK signal-a signal sent from the controller to the printer, which is a synchronizing signal for transmitting and receiving the VDO signal.

VCLKN signal-a signal sent from the controller to the printer, which is synchronized with the VCLK signal, and has a frequency N times that of the VCLK signal.

SC signal-a bidirectional serial signal for bidirectionally transmitting and receiving a "command" which is a signal sent from the controller to the printer and a "status" which is a signal sent from the printer to the controller. .. An SCLK signal, which will be described later, is used as a synchronization signal when transmitting or receiving the signal. Further, an SBSY signal and a CB which will be described later are used as signals for controlling the transmission direction of the bidirectional signal.
The SY signal is used. Here, the “command” is a serial signal of 8 bits, and the controller indicates to the printer whether the paper feeding mode is the mode of feeding from the cassette or the mode of feeding from the manual feed port. This is command information for giving an instruction to the user. The “status” is a serial signal consisting of 8 bits, for example, when the temperature of the fixing device of the printer has not reached the printable temperature, the paper jam condition, or the paper cassette is out of paper. This is information for informing the controller of various states of the printer such as certain ones.

SCLK signal-The printer takes in "commands" or the controller takes "status"
Is a synchronizing pulse signal for taking in.

CBSY signal-This is a signal for occupying the SC signal and the SCLK signal before the controller transmits the "command".

SBSY signal-Printer is in "status"
Is a signal for occupying the SC signal and the SCLK signal before transmitting the signal.

After the VDO signal is input to the printer together with the VCLK signal, it is input to the VDO signal processing unit 101 provided in the printer engine and for performing the signal processing of this embodiment. The VDO signal processing unit converts the input VDO signal by signal processing to be described later, inputs it as a converted signal VDOM to the laser driver 50 of FIG. 2, and drives the semiconductor laser 51 to blink.

The operation of such an interface will be described below.

When the power switch of the printer is turned on and the power switch of the controller is turned on, the printer initializes the internal state of the printer and then sets the PPRDY signal to "true" to the controller. On the other hand, the controller similarly initializes the internal state of the controller and then sets the CPRDY signal to "true" for the printer. With this, the printer and the controller confirm that the respective power supplies have been turned on.

Thereafter, the printer energizes the fixing heater 24 housed inside the fixing rollers 8 and 8 ', and sets the RDY signal to "true" when the surface temperature of the fixing roller reaches a temperature at which fixing is possible. After confirming that the RDY signal is "true", if the controller has data to be printed,
The PRNT signal is made "true" to the printer. When the printer confirms that the PRNT signal is "true", the photosensitive drum 11 is rotated to uniformly initialize the potential on the surface of the photosensitive drum, and at the same time, in the cassette sheet feeding mode, the sheet feeding cam 3 is driven and the leading edge of the sheet is fed. Is conveyed to the position of the resist shutter 5. In the manual feed mode,
The paper manually fed from the paper feed table 16 by the manual paper feed roller 17 is conveyed to the position of the registration shutter 15.
Then, when the printer becomes ready to accept the VDO signal, the VSREQ signal is set to "true". After the controller confirms that the VSREQ signal is "true",
At the same time that the VSYNC signal is set to "true", the VDO signal is sequentially transmitted in synchronization with the BD signal.

Upon confirming that the VSYNC signal has become "true", the printer drives the registration solenoid 6 in synchronization with this and releases the registration shutter 5. As a result, the sheet 1 is conveyed to the photosensitive drum 11. According to the VDO signal, the printer turns on the laser beam when the image should be printed in black and turns off the laser beam when the image should be printed in white, thereby forming a latent image on the photosensitive drum 11, Next, the developing device 14 attaches toner to the latent image and develops the latent image to form a toner image. Then, the toner image on the drum is transferred onto the sheet 1 by the transfer charger 15, fixed by the fixing rollers 8 and 8 ', and then discharged onto the sheet discharge tray.

The first embodiment in which the halftone signal processing circuit of this embodiment is applied to a laser beam printer of 300 dots / inch, 8 sheets / minute, will be described in detail below.
In the first embodiment, as shown in FIG. 5, a pixel section of 300 dots / inch is divided into 128 in the main scanning direction, and
300 by combining each area by printing or non-printing
An example of obtaining a halftone image with 128 line steps will be described.

FIG. 6 is a diagram for explaining the concept of this embodiment.

As shown in FIG. 6, if a pixel of 300 dots / inch is divided into 128 equal parts, even if the digital count method of the conventional example is used, the clock frequency is 230M.
Since the frequency becomes as high as Hz, a count circuit cannot be realized by a TTL or CMOS circuit.

Therefore, in this embodiment, 1/230 of 230 MHz
4 frequency: A clock signal K0 of 57.6 MHz is provided, and clock signals K1, K2, and K3 having the same frequency with phases delayed by 90 degrees are provided, and the four clock signals with the shifted phases are appropriately selected and counted. By doing so, a digital counting method is enabled. As a result, the frequency to be counted is 57.6 MHz, which is a frequency that can be counted by the TTL or CMOS circuit, but the pulse width can be controlled with an accuracy of ¼ of the cycle obtained from this frequency.

The method according to the present embodiment is more effective when applied to a frequency (a clock frequency of 40 MHz or higher) that exceeds the frequency which is generally considered to be limited by TTL or CMOS circuits.

FIG. 7 shows a circuit block of the VDO signal processing unit 101.

In the figure, reference numeral 25 is a data latch circuit which latches an input 6-bit image signal: VDO0 to VDO5 in synchronization with a clock signal VCLK. The 6-bit image data latched by the latch circuit 25 is connected to the address terminals A0 to A5 of the ROM 26. The address data is data D0 stored in the ROM 26.
~ D5 is output. The data D0 to D5 are input to the data latch 1 (28) and the data latch 2 (29).
The flip-flop 27 receives the clock signal VCLK and inverts its output Q and Q-bar signal each time the clock is input, and outputs the inverted signal.

When the Q output is in the "L" state, the data latch 1 (28) is set to the write state and the output thereof is set to high impedance (at this time, the data latch 2).
(29) sets the read state and prohibits data input).

When the Q output is in the "H" state, the data latch 1 (28) is set to the read state and the data input is prohibited (at this time, the data latch 2 (29) is set to the write state and the data is written). Prohibit input).
The outputs of the data latch 1 (28) and the data latch 2 (29) are input to the decoder 30 as data D0 'to D5'. In this way, the data latch 1 (28) and the data latch 2 (29) form a double buffer according to the clock signal VCLK.

Reference numeral 30 is a decoder for inputting data D
Data SD0-SD5 and data RD0-RD5 are generated corresponding to 0'-D5 '. These data are data D
The print widths corresponding to 0'-D5 'are represented, and these data are input to each set signal generation circuit 32 and reset signal generation circuit 33.

Reference numeral 31 is a clock phase control circuit, which is shown in FIG.
As shown in FIG. 5, a clock signal VCLKN is input and clock signals K0, K1, K2, K3 whose phases are shifted by about 90 degrees are generated based on the signal.

A detailed circuit of the clock phase control circuit 31 is shown in FIG.

In the figure, reference numeral 36 is a clock generating circuit, and its concrete circuit is shown in FIG. That is, the clock signal VCLKN is input, and this signal is passed through the delay network formed by the gates so that the clock signals S0 to S are out of phase.
32 is generated.

Generally, the delay time generated by the gate circuit varies considerably among individual gates, but it is preferable that the gate circuit group used here is a gate circuit configured on the same IC package. In this case, the mutual variation of the delay time of each gate can be made relatively small. Further, the variation in the delay time between the packages is 0.6 nanoseconds to 1.8 nanoseconds per gate.
Let's say it is nanoseconds. Such a delay time can be realized by a normal inexpensive CMOS gate array. According to the present embodiment, such variations in delay time can be automatically corrected to obtain clock signals whose phases differ from each other by approximately 90 degrees.

Reference numeral 37 is a phase detection circuit, and its concrete circuit is shown in FIG. Reference numeral 39 denotes a sampling circuit, which is the clock signal S0 (: frequency =
57.6 MHz, cycle = 17.4 nS) and eight different clock signals with different phases: S8, S11, S15, S1
Input 8, S22, S25, S29, S32. Clock signals: S8, S11, S15, S18, S22, S
25, S29, and S32 are sampled by the sampling circuit 39 at the rising edge of the clock signal S0 (that is, when the time corresponding to the period is 17.4 nS).
Sampling data S8 ', S11', S15 ', S1
8 ', S22', S25 ', S29', S32 'are obtained. The eight sampling data are supplied to the encoder circuit 4
At 0, data is latched at the leading edge of the VSYNC signal, and 3-bit code signals: H0 to H2 are generated according to the latched data (here, VSYNC.
Although the example of latching by the C signal is shown, it may be latched at the leading edge of the BD signal). The code signals H0 to H2 are
It is decided as shown in FIG. 11 corresponding to the sampling data. That is, the most optimal clock signal is selected in order to obtain a clock whose phase is shifted by approximately 90 degrees from the sampling result.

For example, as a first example, S8 = "L",
S15 = "H", S18 = "H", S22 = "L", S
When 25 = “L” and S32 = “H”, H0 =
Code signals of "H", H1 = "L", H2 = "L" are generated, and as a second example, S8 = "L", S11 =
"L", S22 = "H", S25 = "H", S29 =
When "L" and S32 = "L", H0 = "H", H
A code signal of 1 = “H” and H2 = “L” is generated.

Although only the above two examples are shown in FIG. 11, the code signals in other cases are similarly determined.

The above-mentioned first example occurs when there is a clock relationship as shown in FIG. In accordance with the code signals H0 to H2 generated in this case, the clock selection circuit 38 outputs the clock signal S16 as the clock output K3, the clock signal S11 as the clock output K2, and the clock output K.
The clock signal S5 is selected as 1, and the clock signal S0 is selected as the clock output K0.

The above second example occurs when there is a clock relationship as shown in FIG. In accordance with the code signals H0 to H2 generated in this case, the clock selection circuit 38 outputs the clock signal S21 as the clock output K3, the clock signal S14 as the clock output K2, and the clock output K.
The clock signal S7 is selected as 1 and the clock signal S0 is selected as the clock output K0.

By doing so, as shown in FIG. 14, four types of clock signals K0, K1, K2, which are out of phase for each phase difference obtained by dividing the period of the clock signal S0 into four equal parts, are obtained.
K3 can be obtained. Since the above control is performed every time the VSYNC signal is input (or each time the BD signal is input), even if variations in the gate delay time of the IC or variations in the delay time due to temperature or the like occur, the control is always performed. It is possible to generate four types of clock signals having substantially equal phase differences.

In this embodiment, the clock signal VCLK
An example of obtaining four kinds of clock signals K0, K1, K2, and K3 having different phases with respect to the leading edge of N has been shown, but a signal obtained by inverting the clock signal VCLKN (clock signal K0) is used as the clock signal K2. Good. In this case,
The duty of the clock signal needs to be 50%.

In the present embodiment, an example using four kinds of clock signals whose phases are divided into four has been described. However, eight kinds of clock signals divided into eight and further 16 kinds of clock signals divided into sixteen are used. It goes without saying that it is good.

Returning to FIG. 7, reference numeral 32 denotes a set signal generation circuit, which is used for the data SD0 to SD5 and the clock signal K0,
K1, K2 and K3 are input and a set signal S is generated based on the logic described later.

Reference numeral 33 is a reset signal generating circuit, which is used for the data SD0 to SD5 and the clock signals K0, K1, K.
2 and K3 are input and the reset signal R is generated based on the logic described later.

A flip-flop circuit 34 generates an output signal VDOM which is set by the set signal S and reset by the reset signal R.

FIG. 16 shows the timing of the above signals.

The clock signal VCLK is obtained as a signal (f _VCLKN = 32 × f _VCLK ) obtained by counting down the clock signal VCLKN by 32 by a controller (not shown). The image signal VDO (VDO0 to VDO5) is input in synchronization with the clock signal VCLK and data latched by the data latch circuit 25. The data is stored in the ROM 26
Address data A0 to A5, and outputs stored data D0 to D5 in the ROM 26 addressed by the signal.
In this embodiment, the output data is 6 bits (D0 to D5).
However, it is not limited to this, and 8 bits (D0 to D
7) etc. may be used.

The ROM 26 functions as so-called gamma correction data conversion for correcting the linearity between the input image data and the printing characteristics of the printer. The data D0 to D5
The data latch 1 (28) and the data latch 2 (29) functioning as a double buffer circuit for the above purpose have the purpose of enabling high-speed access to supplement the access speed of the ROM. That is, ROM generally has an access speed of 80.
The read access speed is 1 to 2 nanoseconds, which is a high-speed operation, though the nanosecond to 150 nanoseconds. The data D0 'to D5' obtained from the double buffer circuit are used as data indicating the density code for the 300-line pixel shown in FIG.
Input to 0.

The decoder 30 prints with the densities of the density codes D0 'to D5' input as shown in FIG.
A signal S designating a black print start point S and a signal R designating a black print end point R, which are set in correspondence with the area of one black print area in the 00-line pixel area, are generated. here,
It is assumed that the black print start point S is on the left side of the center of the 300-line pixel, and the black print end point R is on the right side of the 300-line pixel, that is, 300 lines are printed as the density changes from low density to high density. It is selected so that the black print area extends from the center of the pixel. Here, as described in the above example, the black print region does not necessarily grow from the central portion, but may be grown from the left end or the right end of the 300-line pixel. Further, here, an example is described in which only one black print area is included in a 300-line pixel, but the present invention is not limited to this, and two black print areas are included in a 300-line pixel.
Even if three or four, it does not deviate from the intention of the present invention.

Signals SD0 to SD0 generated from the decoder 30.
SD5 is a code signal for designating the position of the black printing start point S in the black printing area in FIG. 19, and one of the clock signals K0 to K3 is designated by 2 bits of SD4 to SD5. Further, the count number N1 for counting the specified clock signal from the left end of the 300-line pixel is specified by 4 bits of SD0 to SD3. That is, S
The black printing start point S is the position at which the clock signal selected in D4 to SD5 is counted N1 from the left end of the 300-line pixel.

Examples of code correspondence at this time are shown in FIGS.
Shown in.

The set signal generating circuit 32 selects one of the clock signals K0 to K3 according to the black print start point designating code signals SD0 to SD5, and sets the clock to N1.
A set signal S is generated at the time of counting and is input to the set input terminal of the flip-flop circuit 34.

Signals RD0 to RD0 generated from the decoder 30.
RD5 is a code signal for designating the position of the black print end point R in the black print area in FIG. 19, and one of the clock signals K0 to K3 is designated by 2 bits of RD4 to RD5. Further, the count number N2 for counting the designated clock signal from the center of the 300-line pixel is designated by 4 bits of RD0 to RD3. Ie R
The position where the clock signal selected by D4 to RD5 is counted N2 from the center of the 300-line pixel is the black printing end point R.

Examples of code correspondence at this time are shown in FIGS.
Shown in.

The reset signal generating circuit 33 selects one of the clock signals K0 to K3 according to the black print end point designating code signals RD0 to RD5 and sets the clock to 3
A reset signal R is generated at the time when N2 is counted from the center of the 00-line pixel (when K0 is counted 16 or the falling edge point of the VCLK signal), and is input to the reset input terminal of the flip-flop circuit 34.

The flip-flop circuit 34 outputs VDOM at the rising edge of the input set signal S.
The signal is set to "H" level, and the output VDOM signal is reset to "L" level at the rising edge of the input reset signal R.

In this way, a signal for printing the black area in the 300-line pixel is generated, and the signal VDOM is "H".
By turning on the laser at the level and turning off the laser at the “L” level, it is possible to reproduce and print a halftone image in 300-line pixel units. As described above, according to this embodiment, it is possible to generate a pulse width modulated signal by a digital method and print a halftone image.

The above description will be specifically described by taking the pattern of FIG. 19 as an example. In this case, since the black print start point designation code signals SD5 to SD0 are obtained by selecting the clock signal K1 and counting the clock signal 12 times, SD5 = 0, SD4 = 1 and SD3 = 1, SD2 = 1,
SD1 = 0 and SD0 = 0 are set.

Black print end point designation code signals RD5
Since RD0 is obtained by selecting the clock signal K2 and counting the clock signal 5 times, RD5 =
1, RD4 = 0 and RD3 = 0, RD2 = 1, RD1 =
0 and RD0 = 1 are set.

In this embodiment, an example in which the black print start point and the black print end point are designated using a 6-bit code signal has been shown, but it goes without saying that the number of bits of the code signal may be further increased.

20 to 43 show the results of using this embodiment.
It is an example of a halftone pattern of 0-line pixels.

20 to 27 are examples of patterns in which the black print area expands from the central portion of the 300-line pixel.
From FIG. 27 to FIG. 27, the halftone density becomes darker.

28 to 35 are examples of patterns in which the black print area expands from the left end of the 300-line pixel.
From FIG. 35 to FIG. 35, the density of the halftone increases.

Here, similarly, a pattern in which the black region expands from the right end may be adopted.

FIGS. 36 to 43 are examples of patterns in which the black print area is expanded from two locations within the pixel of 300 line pixels, and the density of the halftone becomes darker as it advances from FIG. 36 to FIG.

A second embodiment in which the halftone signal processing circuit of the present invention is applied to a laser beam printer of 600 dots / inch for 8 sheets / minute will be described in detail below.

In the second embodiment, as shown in FIG.
A small section is created by dividing a 00 dot / inch pixel into 32 equal parts in the main scanning direction, and 600 dot / inch pixels are 2 pixels in the main scanning direction and 2 pixels in the sub-scanning direction for a total of 4 pixels.
An example in which a halftone image of 300 lines and 128 steps is obtained by a combination of printing or non-printing each of the sub-divisions, in which each pixel is a pixel unit of halftone expression, will be described.

FIG. 44 is a block diagram of the second embodiment, in which the same numbers or symbols as those in FIG. 7 are the same. In FIG. 45, a flip-flop circuit 35 inputs the BD signal as shown in FIG. 45 and inverts the output level every time the BD signal is input. The output is input as the address A6 of the ROM 26.

When the address data A6 is at "L" level, as shown in FIG. 47, the density code of the upper half of the 300-line pixel obtained by combining 600 dot / inch pixels "A" and "B" is R.
It is output as the output data of the OM 26.

The set signals SD0 to SD5 obtained from the decoder 30 based on the density code are as shown in FIG.
Black print start point S1 for the black area in the upper half of the 300 line pixel
And reset signals RD0 to RD5 are 300
The black printing end point R1 for the black area on the upper half of the line pixel is designated. The set signal generation circuit 32 and the reset signal generation circuit 33 have a cycle of 300 line pixels (: 600 dots /
Double the clock period corresponding to inch) Clock signal V
Clock signal VCLKN that is 16 times the frequency of CLK
The clock signals K0 to K3 having different phases obtained based on the
The first pulse width modulation signal VDOM1 is obtained from 4.

In this way, the upper half of the 300 line pixel is printed as black from S1 to R1 as shown in FIG.

When the address data A6 is at the "H" level, the density code of the lower half of the 300-line pixel, which is a combination of 600 dot / inch pixels "C" and "D", is output as the output data of the ROM 26.

The set signals SD0 to SD5 obtained from the decoder 30 based on the density code are as shown in FIG.
Black print start point S2 for the black area in the lower half of the 300 line pixel
And reset signals RD0 to RD5 are 300
The black printing end point R2 for the black area in the lower half of the line pixel is designated. The set signal generation circuit 32 and the reset signal generation circuit 33 appropriately select the clock signals K0 to K3, count a predetermined number, and obtain the second pulse width modulation signal VDOM2 from the flip-flop 34.

In this manner, the lower half of the 300 line pixel is printed as black from S2 to R2 as shown in FIG.

Therefore, by outputting the same image data for two scans of 600 dots / inch, a halftone image of 300 dots / inch can be generated.

The above description will be more specifically described by taking the pattern of FIG. 48 as an example.

In this case, for the first scan (: 300 line pixel upper half), the black print start point designating code signal SD5.
Since SD0 is obtained by selecting the clock signal K2 and counting the clock signal by 6, SD5 =
1, SD4 = 0 and SD3 = 0, SD2 = 1, SD1 =
1, SD0 = 0 is set. Further, since the black print end point designation code signals RD5 to RD0 are obtained by selecting the clock signal K3 and counting the clock signal 3 times, RD5 = 1, RD4 = 1 and RD3 = 0, RD2.
= 0, RD1 = 1, and RD0 = 1 are set.

Further, for the second scan (: lower half of 300 line pixels), the black print start point designation code signals SD5 to SD5
Since SD0 is obtained by selecting the clock signal K3 and counting the clock signal 6 times, SD5 =
1, SD4 = 1 and SD3 = 0, SD2 = 1, SD1 =
1, SD0 = 0 is set. Further, since the black print end point designation code signals RD5 to RD0 are obtained by selecting the clock signal K2 and counting the clock signal 3 times, RD5 = 1, RD4 = 0 and RD3 = 0, RD2.
= 0, RD1 = 1, and RD0 = 1 are set.

In this embodiment, an example in which the black print start point and the black print end point are designated by using a 6-bit code signal has been shown, but it goes without saying that the number of bits of the code signal may be further increased. In addition, the count for the black print end point has been described in the example of counting from the central portion of the pixel.
It goes without saying that counting from the left end is also possible.

In this way, the upper half of the 300-line pixel is printed by the first scan, the lower half of the 300-line pixel is printed by the second scan, and the main scan is performed twice to complete the 300-line pixel. To be done. In this case, for image data having the same value, the address A6 is stored in the ROM 26 at the "L" level (: 3).
Black print pattern of "00 line pixels" and "H" (: 3)
The lower half of the 00-line pixel) is combined with the black print pattern to reproduce the halftone of the 300-line pixel, and S1, R1 and S2, R2 related to the black print area are previously determined as a pattern to be printed as a pair. There is.

The above situation is schematically shown in FIG.
In the figure, the area shown by the dotted line shows a size of 600 dots / inch, and the area shown by the solid line shows 300 line pixels.

FIGS. 50 to 73 are the results of using this embodiment 30
It shows an example of a halftone pattern in units of 0-line pixels.

50 to 57 are examples of patterns in which the black print area expands from the central portion of the 300-line pixel.
The growth of the black area in the upper half of the line pixel and the growth of the black area in the lower half are performed in substantially the same manner. 50 to 5 in FIG.
As you proceed to 7, the halftone density increases.

FIGS. 58 to 65 are examples of patterns in which the black print area is enlarged from two locations within a 300-line pixel.
The growth of two black areas in the upper half of the 0-line pixel and the growth of two black areas in the lower half are performed in substantially the same manner. In the same figure, the density of the halftone increases as the process proceeds to FIGS. 58 to 65.

66 to 73 are examples of patterns in which the black print area is enlarged from the upper half of the 300-line pixel and then the black print area of the lower half is enlarged, and as the density shifts from low density to high density. First, the upper half black area of the 300-line pixel is grown, and then the lower half black area is grown.

In the same figure, the density of the halftone increases as the process proceeds from FIG. 66 to FIG. 73.

As described above, according to this embodiment, as shown in FIG.
As shown in FIG. 5, the deviation between the input image density and the output image density with respect to the ideal characteristic generated on the electric circuit returns to the point on the ideal characteristic with each cycle of the clock K0, and thus can be minimized.

Further, according to the present embodiment, since the pulse width can be controlled by the digital count, there is an advantage that the circuit can be easily integrated and the pulse width can be stably generated. Since a high-speed pulse signal can be generated, the step of pulse width can be made finer than ever before.

[0120]

As described above, according to the present invention, fine pulse width PWM control can be performed by using a relatively low frequency clock, and a high quality halftone image can be obtained with an inexpensive circuit configuration. You can

[Brief description of drawings]

FIG. 1 is a diagram showing an engine portion of a laser beam printer which is an embodiment of the present invention.

FIG. 2 is a diagram showing details of a laser scanning system of a laser beam printer.

FIG. 3 is a diagram showing interface signals between a printer engine and a controller.

FIG. 4 is a diagram showing interface signals between a printer engine and a controller.

FIG. 5 is a diagram in which one pixel of 300 dots / inch is divided into 128.

FIG. 6 is a diagram for explaining the concept of the present embodiment.

7 is a circuit diagram showing details of a VDO signal processing unit 101 shown in FIG.

8 is a block diagram showing details of a clock phase control circuit 31 of FIG. 7. FIG.

9 is a block diagram showing details of the clock generation circuit in FIG.

10 is a block diagram showing details of a phase detection circuit 37 in FIG.

FIG. 11 is a diagram showing a table used when selecting a clock signal.

FIG. 12 is a diagram showing an example of clock signal selection.

FIG. 13 is a diagram showing an example of clock signal selection.

FIG. 14 is a diagram showing four types of clock signals whose phases are shifted.

FIG. 15 is a diagram showing four types of clock signals whose phases are shifted.

FIG. 16 is a diagram showing a timing when a pulse width modulation signal is created from a clock signal whose phase is shifted.

17 is a diagram showing clock signals selected by a set signal generation circuit 32 and a reset signal generation circuit 33 based on the output of the decoder 30 of FIG.

18 is a diagram showing the number of clocks counted by the set signal generation circuit 32 and the reset signal generation circuit 33 based on the output of the decoder 30 of FIG. 7 to determine the pulse width.

FIG. 19 is a diagram showing a print width determined based on FIGS. 17 and 18.

FIG. 20 is a diagram showing a pattern in which a black print region expands from the center of a 300-line pixel.

FIG. 21 is a diagram showing a pattern in which a black print region expands from the center of a 300-line pixel.

FIG. 22 is a diagram showing a pattern in which a black print region expands from the central portion of a 300-line pixel.

FIG. 23 is a diagram showing a pattern in which a black print region expands from the center of a 300-line pixel.

FIG. 24 is a diagram showing a pattern in which a black print region expands from the center of a 300-line pixel.

FIG. 25 is a diagram showing a pattern in which a black print region expands from the center of a 300-line pixel.

FIG. 26 is a diagram showing a pattern in which a black print region expands from the center of a 300-line pixel.

FIG. 27 is a diagram showing a pattern in which a black print region expands from the center of a 300-line pixel.

FIG. 28 is a diagram showing a pattern in which a black print area expands from the left end of a 300-line pixel.

FIG. 29 is a diagram showing a pattern in which a black print area is enlarged from the left end of a 300-line pixel.

FIG. 30 is a diagram showing a pattern in which a black print region expands from the left end of 300-line pixels.

FIG. 31 is a diagram showing a pattern in which a black print region expands from the left end of a 300-line pixel.

FIG. 32 is a diagram showing a pattern in which a black print area expands from the left end of a 300-line pixel.

FIG. 33 is a diagram showing a pattern in which a black print region expands from the left end of a 300-line pixel.

FIG. 34 is a diagram showing a pattern in which a black print area expands from the left end of a 300-line pixel.

FIG. 35 is a diagram showing a pattern in which a black print region expands from the left end of a 300-line pixel.

FIG. 36 is a diagram showing a pattern in which a black print region is enlarged from two places within a pixel of 300 line pixels.

FIG. 37 is a diagram showing a pattern in which a black print region is enlarged from two positions within a pixel of 300 line pixels.

FIG. 38 is a diagram showing a pattern in which a black print region is enlarged from two places within a pixel of 300 line pixels.

FIG. 39 is a diagram showing a pattern in which a black print region is enlarged from two positions within a pixel of 300 line pixels.

FIG. 40 is a diagram showing a pattern in which a black print region expands from two locations within a pixel of 300 line pixels.

FIG. 41 is a diagram showing a pattern in which a black print region is enlarged from two places within a pixel of 300 line pixels.

FIG. 42 is a diagram showing a pattern in which a black print region is enlarged from two positions within a pixel of 300 line pixels.

FIG. 43 is a diagram showing a pattern in which a black print region is enlarged from two places within a pixel of 300 line pixels.

FIG. 44 is a VDO signal processing unit 10 in the second embodiment.
The block diagram which showed the detail of 1.

45 is a diagram showing the operation of the flip-flop circuit 35 of FIG. 44.

FIG. 46 is a diagram showing a state of one pixel when a halftone is expressed by using four pixels of 600 dots / inch.

FIG. 47 is a diagram for explaining the printing order of four pixels of 600 dots / inch.

FIG. 48 is a diagram showing print start and end positions of four pixels of 600 dots / inch.

FIG. 49 is a schematic diagram showing how a 300-line pixel is divided into an upper half and a lower half for recording.

FIG. 50 is a diagram showing a pattern in which a black print region expands from the central portion of each of the upper half region and the lower half region of 300-line pixels.

FIG. 51 is a diagram showing a pattern in which a black print region expands from the central portion of each of the upper half region and the lower half region of 300-line pixels.

FIG. 52 is a diagram showing a pattern in which a black print region expands from the central portion of each of the upper half region and the lower half region of 300-line pixels.

FIG. 53 is a diagram showing a pattern in which a black print region expands from the center of each of the upper half and lower half of 300-line pixels.

FIG. 54 is a diagram showing a pattern in which a black print region expands from the central portion of each of the upper half region and the lower half region of a 300-line pixel.

FIG. 55 is a diagram showing a pattern in which a black print region expands from the center of each of the upper half region and the lower half region of 300-line pixels.

FIG. 56 is a diagram showing a pattern in which a black print region expands from the center of each of the upper half and lower half of 300-line pixels.

FIG. 57 is a diagram showing a pattern in which a black print region expands from the central portion of each of the upper half region and the lower half region of a 300-line pixel.

FIG. 58 is a diagram showing a pattern in which a black print region is enlarged from two places in each of the upper half region and the lower half region of a 300-line pixel.

FIG. 59 is a diagram showing a pattern in which a black print region is enlarged from two places in each of the upper half region and the lower half region of a 300-line pixel.

FIG. 60 is a diagram showing a pattern in which a black print region expands from two places in each of the upper half region and the lower half region of a 300-line pixel.

FIG. 61 is a diagram showing a pattern in which a black print region is enlarged from two places in each of the upper half region and the lower half region of a 300-line pixel.

FIG. 62 is a diagram showing a pattern in which a black print region is enlarged from two places in each of the upper half region and the lower half region of a 300-line pixel.

FIG. 63 is a diagram showing a pattern in which a black print region is enlarged from two places in each of the upper half region and the lower half region of a 300-line pixel.

FIG. 64 is a diagram showing a pattern in which a black print region is enlarged from two places in each of the upper half region and the lower half region of a 300-line pixel.

FIG. 65 is a diagram showing a pattern in which a black print region is enlarged from two places in each of the upper half region and the lower half region of a 300-line pixel.

FIG. 66 is a diagram showing a pattern in which the black print area is enlarged from the upper half of the 300-line pixel and then the lower black print area is enlarged.

FIG. 67 is a diagram showing a pattern in which the black print area is enlarged from the upper half of the 300-line pixel, and then the lower black print area is enlarged.

FIG. 68 is a diagram showing a pattern in which the black print region is enlarged from the upper half of the 300-line pixel, and then the lower half black print region is enlarged.

FIG. 69 is a diagram showing a pattern in which the black print region is enlarged from the upper half of the 300-line pixel, and then the lower half black print region is enlarged.

FIG. 70 is a diagram showing a pattern in which the black print region is enlarged from the upper half of the 300-line pixel, and then the lower half black print region is enlarged.

FIG. 71 is a diagram showing a pattern in which a black print region is enlarged from the upper half of the 300-line pixel and then a lower black print region is enlarged.

FIG. 72 is a diagram showing a pattern in which a black print region is enlarged from the upper half of 300-line pixels and then a lower black print region is enlarged.

FIG. 73 is a diagram showing a pattern in which the black print region is enlarged from the upper half of the 300-line pixel and then the lower half black print region is enlarged.

FIG. 74 is a diagram for explaining a conventional example.

FIG. 75 is a view for explaining the effect of this embodiment over the conventional example.

[Explanation of symbols]

 8, 8'Fixer 11 Photosensitive drum 14 Developing device 25, 28, 29 Latch circuit 26 ROM 27, 34, 35 Flip-flop 30 Decoder 31 Clock phase control circuit 32 Set signal generation circuit 33 Reset signal generation circuit 51 Semiconductor laser 52 Rotation Polygon mirror 100 printer 101 VDO signal processing unit 200 controller

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification number Reference number within the agency FI Technical indication location H04N 1/23 103 B 9186-5C (72) Inventor Takashi Kawana 3-30 Shimomaruko, Ota-ku, Tokyo No. 2 within Canon Inc. (72) Inventor Tetsuo Saito 3-30-2 Shimomaruko, Ota-ku, Tokyo Within Canon Inc. (72) Inventor Michio Ito 3-30-2 Shimomaruko, Ota-ku, Tokyo Canon Incorporated (72) Inventor Shinichiro Maekawa 3-30-2 Shimomaruko, Ota-ku, Tokyo Canon Inc. (72) Inventor Toshihiko Sato 3-30-2 Shimomaruko, Ota-ku, Tokyo Canon Inc. ( 72) Inventor Hiromichi Yamada, 3-30-2 Shimomaruko, Ota-ku, Tokyo Canon Inc.

Claims (10)

[Claims] 1. A conversion means for converting input image data representing a gradation into a code signal representing a pulse width, a generation means for generating a plurality of clock signals having different phases at a predetermined frequency, and the above-mentioned code signal based on the code signal. Selecting means for selecting one of a plurality of clock signals; counting means for counting the selected clock signals based on the code signal; and pulse width having a predetermined pulse width according to the output of the counting means. An image recording apparatus comprising: a pulse generating unit that generates a modulation signal. 2. The image recording according to claim 1, wherein the means for generating a plurality of clock signals having different phases is constituted by a delay circuit using a plurality of gates existing on the same IC chip. apparatus. 3. The plurality of clock signals are clock signals whose phases are substantially equally divided.
The image recording device described. 4. The image recording apparatus according to claim 1, further comprising a control unit that performs correction control so that the phases of the plurality of clock signals are substantially equally divided. 5. The image recording apparatus according to claim 4, wherein the control unit periodically controls the phase correction of the plurality of clock signals. 6. The frequency of the clock signal is 40 MHz
The image recording apparatus according to claim 1, wherein the image recording apparatus has the above frequencies. 7. The image recording apparatus has a scanning line density of 300.
The image recording apparatus according to claim 1, wherein the image recording device has dots / inch. 8. The image recording apparatus has a scanning line density of 600.
2. The image recording apparatus according to claim 1, wherein the image recording device is dots / inch, and the unit for expressing halftone pixels is 300 pixels / inch. 9. A means for generating a plurality of clock signals having different phases at a predetermined frequency, a selection means for selecting one of the plurality of clock signals, and a counting means for counting the selected clock signals. A flip-flop circuit that is set or reset in response to the counting means, a laser lighting control means that controls lighting of a laser in response to an output of the flip-flop circuit, and a means that generates an image signal representing a gradation A laser by generating a signal for designating any one of the clock signals and designating a clock signal count number in response to the image signal, and controlling the output of the flip-flop circuit according to the signal. Image recording apparatus for recording a halftone image by controlling the lighting time of. 10. An information signal generating means for generating an information signal representing a gradation image, a modulating means for modulating a light beam according to the information signal, and a scanning means for deflecting the light beam to scan a recording medium. In an image recording apparatus for forming an electrostatic latent image on the recording medium by means of a developing means and for visualizing the electrostatic latent image on the recording medium by means of developing means, a plurality of clocks having a predetermined frequency and different phases are used. Means for generating a signal, and means for generating a code signal indicating a count number for selecting and counting one signal from the plurality of clock signals based on the information signal,
Counting means for selecting one clock signal from the plurality of clock signals according to the code signal and counting a predetermined number, and controlling the lighting time of the laser according to the count output of the counting means. An image recording device characterized by.