JPH059812B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a memory backup circuit applied to memory cards and the like.

[Background technology]

Conventionally, many memory backup circuits have been known which switch from an external power supply to a backup battery to read and write data to the memory, that is, to maintain the operating state of the memory, thereby maintaining the memory in a data holding state.

In this data holding state, the CS (chip select) input of the memory IC is at "L" (low level), and as a result, the memory IC is in a read/write disabled state.

This conventional memory backup circuit has a rectifier diode and a rush current prevention diode connected in parallel to the external power supply, and a forward direction to the rush current prevention diode and a parallel connection to the external power supply. It was constructed with a backup battery.

For example, if the operating voltage of a memory IC is 4.5V, the memory backup battery will have a voltage of 4.5V.
I was using one that was rated to keep the temperature.

However, in recent years, it has become necessary to back up memory for long periods of time, and as a result, backup batteries are required to have a low voltage.

For this reason, 3V lithium batteries, for example, have come to be used as long-life memory backup batteries, but when a lithium battery is used as a backup battery, the backup voltage is lower than the operating voltage of the memory IC, so the IC It is necessary to set the memory IC to a data retention state that only holds the stored contents by setting the memory's CS input to "L" to prohibit reading and writing operations. For this reason,
The external power supply voltage is detected by setting the detection voltage to the operating voltage of the memory IC, 4.5V or higher, and the external power supply voltage is
It is necessary to determine that a power outage has occurred before the voltage drops to 4.5V, and even then, the memory must be placed in a data retention state. Alternatively, it was necessary to select a memory IC that could operate up to battery voltage.

However, in the past, if the external power supply voltage suddenly stopped due to a power outage or the like during memory read/write operations, the CS signal would go "L" because the backup state would immediately occur due to the low voltage mentioned above.
The memory is ready for read/write operations before
When the IC's power supply voltage becomes lower than its operating voltage,
As a result, there was a risk that the stored contents would be erased.

In other words, power outage processing that moves the memory IC to data retention state, i.e., written data is destroyed (erased)
In order to process the CS signal to "L" without switching to "L", at least the operating voltage of 4.5V must be applied to the memory IC as the power supply voltage until the CS signal becomes "L". If the backup voltage is immediately applied as soon as the external power supply voltage is stopped, there will not be enough time to handle the power outage.

[Purpose of the invention]

The present invention has been made in view of the above-mentioned drawbacks of the conventional examples, and provides a highly reliable memory that retains read and written data even if the external power supply is suddenly turned off during memory write or read operations. Its purpose is to provide a backup circuit.

[Summary of the invention]

To this end, the present invention includes a power failure detection circuit in which a control signal rises and falls at a memory operation lower limit potential, and a power conversion circuit in which a signal rises and falls at a predetermined potential lower than this memory operation lower limit potential. be.

〔Example〕

The present invention will be explained below based on illustrated embodiments.

FIG. 1 shows a memory backup circuit according to an embodiment of the present invention.

In the figure, 1 is an external power input terminal, from which the external power is applied, and a diode 2 (D ₁ ),
The voltage is applied from the backup power supply terminal 9 to the memory IC (not shown) through the diode 6 (D ₂ ). A diode D ₂ and a diode 7 (D ₃ ) are provided, and a backup battery (for example, a lithium battery) 8 is connected in series with the diode D ₃ in the forward direction.
will be established.

Therefore, the diode _D3 serves to prevent the external power source from flowing into the backup battery 8.

In the present invention, diodes D ₁ and D ₂
A large capacity capacitor 3 is provided in parallel with the backup battery 8 between the two. The capacity of this capacitor 3 is approximately
The voltage of the backup battery 8 is approximately 0.1F, and the voltage of the backup battery 8 is approximately 3V.

Furthermore, in this embodiment, large capacitor 3
A power conversion circuit 4, which will be described in detail later, is provided between the power conversion circuit 4 and the diode _D2 , and a power failure detection circuit 5 is provided in parallel with the power conversion circuit 4. The power failure detection circuit 5 detects the external power supply voltage and detects the memory IC If the minimum operating voltage is 4.5V due to its characteristics (for example, in the case of a 5V IC), the control signal that rises and falls when the external power supply voltage changes beyond this is sent to the control signal terminal 1.
It is output from 0 and used as the memory IC's CS signal.

First, the memory IC is maintained by an external power supply (4.5 V or higher) from the external power input terminal 1 during its operation (reading and writing).

In the data retention state, the data is backed up by the backup battery 8 and its contents are retained. In other words, it supplies a lower limit voltage that allows a 2.2V backup memory to retain data using, for example, a 3V lithium battery.

Next, the operation when the external power supply is turned off will be described.

In this case, turning off the external power supply may mean disconnecting the power outlet or may include cases of power outage, but in any case, in such a case,
The power supply voltage must be lowered below the memory operation lower limit potential after performing power outage processing, that is, changing the CS signal of the memory IC to "L" and retaining the previously read and written contents, and transitioning to the data retention state.

In other words, when the power is turned off, an "L" control signal must first be output from the control signal terminal 10 and supplied to the memory IC as a CS signal in order to keep the memory in a data retention state before the power is turned off. , at that point, the power supply voltage of the memory IC must be held at 4.5V (minimum operating voltage).

FIG. 2 is a timing chart of sections A to E in FIG. 1. Also, V ₁ in B is
The predetermined value is, for example, 4V, which is lower than the memory operation limit potential (for example, 4.5V), and _V2 indicates the memory operation limit potential (for example, 4.5V).

The waveform of C, ie, the output waveform of the power conversion circuit 4, rises and falls at this _V1 , and is held at the memory operating voltage (for example, 5V) from the rise until the fall.

Further, the waveform of E, that is, the output waveform of the power failure detection circuit 5 is designed to rise and fall at _V2 . The falling "L" level signal is used as a control signal for the above-mentioned power outage process for the memory.

Before this control signal is output, if the C signal (and therefore the D signal) is at the memory operating limit voltage.
If the voltage drops below 4.5V, there is no time to process the power outage, and the data that has been read and written will be erased.

However, in the case of the present invention, as is clear from this timing chart, a time sequence of td ₁ or td ₂ is established between the two, and the power outage process is thereby completely completed. 4.5V like this
When the external power supply goes down (actually, when the voltage between the terminals of the large-capacity capacitor 3 drops to 4.5V), the memory is set to a state where it cannot be read or written, and then the voltage is reduced to 3V from the backup battery 8 to maintain the data retention state. It is something to keep.

Incidentally, as shown in A, chattering occurs when plugging and unplugging the outlet.

Next, the power conversion circuit 4, which is an essential element in the present invention, will be explained based on FIGS. 3 and 4.

FIG. 3a is a block diagram of the 4 portions of this power conversion circuit, and FIG. 3b is a characteristic diagram thereof.

As is clear from this characteristic diagram, the input voltage is 4~
5 (V), the output voltage, that is, the potential of C, is held at 5V regardless of changes in the input voltage.

FIG. 4 shows an example of a specific circuit configuration, and the power conversion circuit 4 includes potential detection units 4a, R,
It consists of an oscillation circuit section 4b made up of C.C. and UJT, a power generation section 4c, and a smoothing section 4b.

Incidentally, the power failure detection circuit 5 is also as shown in the figure.

The present invention provides a large-capacity capacitor that stores electrical energy sufficient to operate the memory retention mode after detecting power supply interruption in this way, and furthermore, a power conversion circuit is provided to keep the voltage applied to the memory within the operating voltage range. This is what I did. In the end, by using this power conversion circuit and a large-capacity capacitor, stable backup operation became possible after the power supply was cut off.

The backup battery 8 and other circuit components may be integrated into the case of the backup battery 8, or the circuit may be provided independently of the backup battery.

〔Effect of the invention〕

As described above, the present invention provides, by means of a power conversion circuit,
Even if the external power supply is cut off and the memory is backed up at a backup battery voltage lower than the memory's lower limit operating voltage, the operating voltage can be applied to the memory for the time required to shift the memory to the data retention state. Furthermore, even when an external power source is turned on, the data retention state of the memory can be released after the external power source has stably applied the operating voltage to the memory, thereby preventing the memory contents from being destroyed. It becomes possible to set and release the data retention state of the memory without any hassle. Also, a power supply with a large fluctuation rate can be used. Furthermore, even if it is a 3V battery such as a lithium battery, a single 5V IC can be used.
Backups can be performed stably. Moreover, even if you connect the memory card to the contacts while the main unit's power is on, power is supplied to the memory with a delay after the contacts are turned on, so there is no need to worry about memory damage.

[Brief explanation of the drawing]

Fig. 1 is a backup memory circuit diagram according to an embodiment of the present invention, Fig. 2 is a timing chart of each part thereof, Fig. 3a is a block diagram of the power conversion circuit, Fig. 3b is its characteristic diagram, and Fig. 4 FIG. 1 is a circuit diagram showing an example of a power conversion circuit. 4... Power conversion circuit, 5... Power outage detection circuit.

Claims (1)

[Claims] 1. A backup battery that outputs a voltage lower than the operating lower limit potential of the memory is provided, and when the external power source is turned off, the power source of the memory is switched from the external power source to the backup power source, and the memory is powered up by the backup power source. In a memory backup circuit configured to back up the memory, the external power supply voltage is detected, and when the voltage falls below the operating lower limit potential of the memory, the memory is put into a data retention state, and the external power supply voltage is set to the operating lower limit potential. a power failure detection circuit that generates a control signal that releases the data retention state of the memory when the voltage exceeds a lower limit potential; and a power conversion circuit that rises to a constant potential equal to or higher than the lower limit potential and, when the external power supply voltage becomes lower than the predetermined reference potential, falls from the constant potential and outputs a voltage lower than the voltage of the backup battery. . A memory backup circuit characterized in that the higher of the output voltage of the power conversion circuit and the voltage of the backup battery is used as the power supply voltage of the memory.