JPH04314152A - Memory backup cirucit - Google Patents

Abstract

PURPOSE:To surely prevent the instantaneous fall of supply voltage to a memory at the time of the turning-off of the power supply of main power source. CONSTITUTION:A primary battery 5 for backup is connected to the feeder line 4 of a volatile memory 3 through a limiting resistor 6 and a reverse-current preventing diode 7, and simultaneously, an AND circuit 8 for chip select control circuit which is driven by the power supply from the feeder line 4 and outputs a signal to turn this memory 3 into a non-selecting state to the chip select terminal CS of the memory 3 at the time of the turning-off of the main power source is provided, and in addition, an electric double layer capacitor 10 is connected to the feeder line 4.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory backup circuit for backing up a volatile memory used, for example, as a storage device in a microcomputer system during a power outage.

0002

2. Description of the Related Art Conventionally, microcomputer systems have been constructed using a volatile memory called RAM as a storage device, and as a countermeasure against power outages, in many cases, a method of backing up the memory circuit with a battery has been adopted.

For example, FIG. 2 shows a conventional backup circuit of this type, in which a power supply terminal 1 of a main power supply is connected to a power supply terminal Vcc of a volatile memory 3 via an anode and a cathode of a backflow prevention diode 2. A backup primary battery 5 made of a lithium battery with excellent ambient temperature characteristics and storage characteristics is connected to the power supply line 4 through a limiting resistor 6.
and are connected via the anode and cathode of the backflow prevention diode 7. Note that the limiting resistor 6 is used to limit the short-circuit current of the battery 5 due to a power supply short-circuit or the like and the charging current to the battery 5 due to a short-circuit failure of the diode 7.

[0004] Therefore, when the main power supply is energized,
A power supply voltage of 5V is supplied from the power supply terminal 1 to the memory 3 through the diode 2 and the power supply line 4, and when the main power supply is cut off due to a power outage, etc., when the power supply voltage falls below the battery voltage of 3.6V, the battery voltage increases from the battery 5. 6, a diode 7, and a power supply line 4 to supply it to the memory 3, and data retention in the memory 3 is performed.

By the way, in a configuration in which only the battery 5 is connected to the power supply line 4, there is a risk that memory data may be accidentally destroyed in a transient state due to the main power being cut off. A chip select control circuit is provided which deselects the memory chip and prevents data destruction regardless of the states of read/write control signals, addresses, data, etc.

That is, a TTL-configured two-input type AND circuit 8 is provided whose power supply terminal is connected to the power supply line 4, one input terminal of which is connected to the power supply terminal 1 via a current limiting resistor 9, and the other input terminal is connected to the power supply terminal 1 through a current limiting resistor 9. A chip select signal from a CPU (not shown) is input to the terminal, and the output signal of the AND circuit 8 is inverted and input to the chip select terminal CS of the memory 3.

Since the memory 3 is selected by inputting a low level to the chip select terminal CS, when the main power is turned on, one input terminal of the AND circuit 8 is always held at a high level, and no input is input to the other input terminal. The chip select signal is inverted and input to the terminal CS, enabling chip selection. When the main power supply is turned off, one input terminal of the AND circuit 8 becomes a low level, so a high level is always input to the terminal CS, resulting in a chip non-selected state, and data destruction is prevented.

[0008]

[Problems to be Solved by the Invention] In the memory backup circuit described above, it is possible to deselect the memory 3 when the main power is turned off to prevent its data from being destroyed. In bipolar ICs, a large current normally flows when the gate switches, so there is a problem that the battery voltage drops instantaneously when the power is turned off.

That is, in FIG. 2, when the main power supply is cut off and the power supply voltage falls below the battery voltage of 3.6V, memory is retained by the battery 5, but as the power supply voltage further decreases, the threshold of the AND circuit 8 When the voltage drops below the hold voltage,
Current I (several 10 mA) from power supply line 4 to AND circuit 8
flows. Therefore, at this time, a sudden voltage drop occurs due to the limiting resistor 6 provided on the battery 5 side, and the power supply line 4
There is a risk that the voltage of the memory 3 will momentarily drop below the voltage 2.0V required for memory retention, and as a result, the data in the memory 3 will be erased.

[0010] The present invention has been made with these problems of the prior art in mind, and its purpose is to reduce the instantaneous voltage drop in the battery voltage when the main power supply is turned off. An object of the present invention is to provide a memory backup circuit that can reliably prevent such problems.

[0011]

[Means for Solving the Problems] In order to achieve the above object, in the memory backup circuit of the present invention, a backup battery is connected to the power supply line of the volatile memory via a limiting resistor and a backflow prevention diode. , a chip select control circuit is provided that is driven by the power from the power supply line and outputs a signal to the chip select terminal of the memory to deselect the memory when the main power is turned off, and an electric double layer capacitor is connected to the power supply line. It is characterized by the fact that

0012

[Function] In the memory backup circuit configured as described above, even if a large current momentarily flows from the power supply line to the chip select control circuit that detects this when the main power supply is turned off, the electric double layer capacitor connected to the power supply line Since more current is supplied, there is no instantaneous voltage drop caused by the limiting resistor provided on the battery side.

[0013]

[Example] An example will be explained with reference to FIG. As shown in the figure, the power supply terminal 1 of the main power supply is connected to the power supply terminal Vcc of the volatile memory 3 through the anode and cathode of the reverse current prevention diode 2 and the power supply line 4, and a backup primary battery such as a lithium battery is connected. The battery 5 is connected to the power supply line 4 via a limiting resistor 6 and an anode and a cathode of a backflow prevention diode 7.

Furthermore, an AND circuit 8 for the chip select control circuit which is supplied with power from the power supply line 4 is provided, one input terminal of which is connected to the power supply terminal 1 via a current limiting resistor 9, and the other input terminal A chip select signal from a CPU or the like is input to the input circuit 8, and the output signal of the AND circuit 8 is inverted input to the chip select terminal CS of the memory 3 to control memory selection. A double layer capacitor (supercapacitor) 10 is connected. This capacitor 10 has a capacity that can back up the memory 3 for a short time (for example, 0.5 to 1 hour).

Therefore, when the main power supply is cut off due to a power outage or the like and the power supply voltage drops below the voltage of the capacitor 10, the accumulated charge of the capacitor 10 is discharged to the power supply line 4, and the memory 3 is backed up. When the power supply voltage further decreases below the threshold voltage of the AND circuit 8,
A large current flows from the power supply line 4 to the AND circuit 8 as the gate switches, but since this current is supplied from the capacitor 10, there is no voltage drop in the power supply line 4, and memory retention is maintained.

Furthermore, due to the continuation of the power cut, capacitor 1
As the discharge of 0 progresses and the voltage becomes lower than the battery voltage,
After that, the battery voltage is supplied from the battery 5 to the power supply line 4,
Memory 3 is backed up. In this way, even if a large current flows through the AND circuit 8 when the power is turned off, the capacitor 1
Since the current is supplied by 0, no instantaneous voltage drop occurs due to the limiting resistor 6 as in the conventional case, and the problem of erasing data in the memory 3 is eliminated. Moreover, if the power is cut off for a short time, memory can be retained by the capacitor 10, and there is no need to supply voltage from the battery 5 side at this time, which leads to a longer lifespan of the battery 5.

[0017]

[Effects of the Invention] Since the present invention is constructed as described above, it produces the following effects. When the main power supply is turned off, the current that flows from the power supply line to the chip select control circuit is supplied from the electric double layer capacitor connected to the power supply line, preventing a momentary drop in the supply voltage to the memory. This eliminates the risk of erasing the contents of the memory during power outage, making it possible to safely and stably hold the memory, and also has the effect of improving the life of the backup battery by supplying power with the capacitor.

[Brief explanation of drawings]

FIG. 1 is a wiring diagram showing one embodiment of a memory backup circuit according to the present invention.

FIG. 2 is a wiring diagram of a conventional example.

[Explanation of symbols]

3. Volatile memory 4 Power supply line 5 Primary battery 6 Limiting resistor 7 Diode for backflow prevention 8 AND circuit 10 Electric double layer capacitor

Claims (1)

[Claims] 1. A backup battery is connected to a power supply line of a volatile memory through a limiting resistor and a reverse current prevention diode, and the memory chip is driven by power from the power supply line and is activated when the main power is cut off. 1. A memory backup circuit comprising a chip select control circuit that outputs a signal to a select terminal to set the memory in a non-selected state, wherein an electric double layer capacitor is connected to the power supply line.